forked from KolibriOS/kolibrios
132 lines
3.4 KiB
NASM
132 lines
3.4 KiB
NASM
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$Revision: 1598 $
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SMBUS_PCIE_ADDR equ 0xF00A0000 ; bdf0:20.0 = SB7xx SMBus PCI Config Registers
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LPC_PCIE_ADDR equ 0xF00A3000 ; bdf0:20.3 = SB7xx LPC ISA bridge Config Registers
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SB_SIO_INDEX equ 0x2e
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;---------------------------------------------------------------------
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align 4
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smbus_read_pciconfig:
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; in: dl = reg# | out: eax = data
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mov ebx, SMBUS_PCIE_ADDR
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and edx, 0x0FC
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mov eax, dword [ebx+edx]
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ret
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;------------------------------------------------
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align 4
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smbus_write_pciconfig:
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; in: dl = reg#; eax = data
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mov ebx, SMBUS_PCIE_ADDR
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and edx, 0x0FC
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mov dword [ebx+edx], eax
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ret
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;--------------------------------------------------------------------
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align 4
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lpc_read_pciconfig:
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; in: dl = reg# | out: eax = data
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mov ebx, LPC_PCIE_ADDR
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and edx, 0x0FC
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mov eax, dword [ebx+edx]
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ret
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;------------------------------------------------
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align 4
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lpc_write_pciconfig:
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; in: dl = reg#; eax = data
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mov ebx, LPC_PCIE_ADDR
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and edx, 0x0FC
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mov dword [ebx+edx], eax
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ret
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;--------------------------------------------------------------------
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align 4
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read_sio_cfg:
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; in: al = reg# | out: al = data
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mov dx, SB_SIO_INDEX
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out dx, al
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inc dl
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in al, dx
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ret
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;------------------------------------------------
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align 4
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write_sio_cfg:
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; in: al = reg#; ah = data
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;------------------------------------------------
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mov dx, SB_SIO_INDEX
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out dx, al
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inc dl
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xchg al, ah
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out dx, al
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xchg al, ah
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ret
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;------------------------------------------------
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align 4
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enter_sio_cfg_mode:
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; the magic sequence to unlock the port
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;------------------------------------------------
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mov dx, SB_SIO_INDEX
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mov eax, 0x55550187 ; low byte first
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out dx, al
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shr eax, 8
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out dx, al
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shr eax, 8
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out dx, al
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shr eax, 8
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out dx, al
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ret
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;-----------------------------------------------------------------------
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; ATTENTION: the functions assume that RESET# signals use pins 84 and 34
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; of IT8712F SuperIO chip. These signals may be (and will be!) different
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; for every particular motherboard and SIO. Please refer to your m/board
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; documentation to define the correct pins and GPIO lines!
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;
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; Note this example DOES NOT PRETEND to be 100% correct implementation
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; of PCIe hotplug techniques !!
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;-----------------------------------------------------------------------
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align 4
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init_pcie_slot_control:
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;------------------------------------------------
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call enter_sio_cfg_mode
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mov ax, 0x0707 ; LDN = 07
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call write_sio_cfg
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mov al, 0x25
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call read_sio_cfg ; ah = reg25h (Multy-function pin selector)
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or ah, 3 ; set bits 0, 1 (GPIO)
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call write_sio_cfg
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mov al, 0x2A
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call read_sio_cfg ; ah = reg2Ah (Extended fn pin selector)
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or ah, 3 ; set bits 0, 1 (GPIO)
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call write_sio_cfg
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mov al, 0xB8
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call read_sio_cfg ; ah = regB8h (internal pull-up enable)
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or ah, 3 ; set bits 0, 1
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call write_sio_cfg
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mov al, 0xC0
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call read_sio_cfg ; ah = regC0h (simple IO enable)
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or ah, 3 ; set bits 0, 1
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call write_sio_cfg
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mov ax, 0x0202 ; Lock SIO config ports
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call write_sio_cfg
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ret
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align 4
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reset_pcie_slot:
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;------------------------------------------------
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call enter_sio_cfg_mode
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mov ax, 0x0707 ; LDN = 07
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call write_sio_cfg
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mov al, 0xB0
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call read_sio_cfg ; ah = regB0h (Pin polarity)
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and ah, 0xFC ; invert bits 0, 1
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call write_sio_cfg
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or ah, 3 ; restore bits 0, 1
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call write_sio_cfg
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mov ax, 0x0202 ; Lock SIO config ports
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call write_sio_cfg
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ret
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