forked from KolibriOS/kolibrios
Intel-2D: sna static stream initialization
git-svn-id: svn://kolibrios.org@3258 a494cfbc-eb01-0410-851d-a64ba20cac60
This commit is contained in:
parent
89bfe5f5d6
commit
1633df9e80
@ -397,7 +397,7 @@ gen6_choose_composite_kernel(int op, bool has_mask, bool is_ca, bool is_affine)
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/*
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if (is_ca) {
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if (gen6_blend_op[op].src_alpha)
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base = GEN6_WM_KERNEL_MASKCA_SRCALPHA;
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base = GEN6_WM_KERNEL_MASKSA;
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else
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base = GEN6_WM_KERNEL_MASKCA;
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} else
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@ -1647,7 +1647,7 @@ gen6_render_video(struct sna *sna,
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_kgem_set_mode(&sna->kgem, KGEM_RENDER);
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}
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gen6_emit_video_state(sna, &tmp, frame);
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gen6_emit_video_state(sna, &tmp);
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gen6_align_vertex(sna, &tmp);
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/* Set up the offset for translating from the given region (in screen
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@ -1815,10 +1815,10 @@ static void gen6_render_composite_done(struct sna *sna,
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gen6_magic_ca_pass(sna, op);
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}
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// if (op->mask.bo)
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// kgem_bo_destroy(&sna->kgem, op->mask.bo);
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// if (op->src.bo)
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// kgem_bo_destroy(&sna->kgem, op->src.bo);
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if (op->mask.bo)
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kgem_bo_destroy(&sna->kgem, op->mask.bo);
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if (op->src.bo)
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kgem_bo_destroy(&sna->kgem, op->src.bo);
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// sna_render_composite_redirect_done(sna, op);
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}
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@ -3223,7 +3223,7 @@ static void gen6_render_reset(struct sna *sna)
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static void gen6_render_fini(struct sna *sna)
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{
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// kgem_bo_destroy(&sna->kgem, sna->render_state.gen6.general_bo);
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kgem_bo_destroy(&sna->kgem, sna->render_state.gen6.general_bo);
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}
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static bool is_gt2(struct sna *sna)
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@ -3333,7 +3333,7 @@ bool gen6_render_init(struct sna *sna)
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// sna->render.fill_one = gen6_render_fill_one;
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// sna->render.clear = gen6_render_clear;
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// sna->render.flush = gen6_render_flush;
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sna->render.flush = gen6_render_flush;
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sna->render.reset = gen6_render_reset;
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sna->render.fini = gen6_render_fini;
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@ -3445,9 +3445,3 @@ int gen4_vertex_finish(struct sna *sna)
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return sna->render.vertex_size - sna->render.vertex_used;
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}
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void *kgem_bo_map(struct kgem *kgem, struct kgem_bo *bo)
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{
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return NULL;
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};
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@ -199,54 +199,54 @@ typedef struct _drm_i915_sarea {
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#define DRM_I915_GEM_GET_CACHEING 0x30
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#define DRM_I915_REG_READ 0x31
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#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
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#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
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#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
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#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
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#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
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#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
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#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
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#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
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#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
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#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
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#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
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#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
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#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
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#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
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#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
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#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
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#define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init)
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#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
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#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
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#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
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#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
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#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
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#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
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#define DRM_IOCTL_I915_GEM_SET_CACHEING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHEING, struct drm_i915_gem_cacheing)
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#define DRM_IOCTL_I915_GEM_GET_CACHEING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHEING, struct drm_i915_gem_cacheing)
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#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
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#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
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#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
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#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
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#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
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#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
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#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
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#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
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#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
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#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
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#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
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#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
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#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
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#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
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#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
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#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image)
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#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
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#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
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#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
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#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
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#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
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#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
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#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
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#define DRM_IOCTL_I915_INIT
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#define DRM_IOCTL_I915_FLUSH
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#define DRM_IOCTL_I915_FLIP
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#define DRM_IOCTL_I915_BATCHBUFFER
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#define DRM_IOCTL_I915_IRQ_EMIT
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#define DRM_IOCTL_I915_IRQ_WAIT
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#define DRM_IOCTL_I915_GETPARAM SRV_GET_PARAM
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#define DRM_IOCTL_I915_SETPARAM
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#define DRM_IOCTL_I915_ALLOC
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#define DRM_IOCTL_I915_FREE
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#define DRM_IOCTL_I915_INIT_HEAP
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#define DRM_IOCTL_I915_CMDBUFFER
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#define DRM_IOCTL_I915_DESTROY_HEAP
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#define DRM_IOCTL_I915_SET_VBLANK_PIPE
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#define DRM_IOCTL_I915_GET_VBLANK_PIPE
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#define DRM_IOCTL_I915_VBLANK_SWAP
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#define DRM_IOCTL_I915_HWS_ADDR
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#define DRM_IOCTL_I915_GEM_INIT
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#define DRM_IOCTL_I915_GEM_EXECBUFFER
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#define DRM_IOCTL_I915_GEM_EXECBUFFER2
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#define DRM_IOCTL_I915_GEM_PIN SRV_I915_GEM_PIN
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#define DRM_IOCTL_I915_GEM_UNPIN
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#define DRM_IOCTL_I915_GEM_BUSY SRV_I915_GEM_BUSY
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#define DRM_IOCTL_I915_GEM_SET_CACHEING SRV_I915_GEM_SET_CACHEING
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#define DRM_IOCTL_I915_GEM_GET_CACHEING
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#define DRM_IOCTL_I915_GEM_THROTTLE
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#define DRM_IOCTL_I915_GEM_ENTERVT
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#define DRM_IOCTL_I915_GEM_LEAVEVT
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#define DRM_IOCTL_I915_GEM_CREATE SRV_I915_GEM_CREATE
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#define DRM_IOCTL_I915_GEM_PREAD
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#define DRM_IOCTL_I915_GEM_PWRITE SRV_I915_GEM_PWRITE
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#define DRM_IOCTL_I915_GEM_MMAP SRV_I915_GEM_MMAP
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#define DRM_IOCTL_I915_GEM_MMAP_GTT SRV_I915_GEM_MMAP_GTT
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#define DRM_IOCTL_I915_GEM_SET_DOMAIN SRV_I915_GEM_SET_DOMAIN
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#define DRM_IOCTL_I915_GEM_SW_FINISH
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#define DRM_IOCTL_I915_GEM_SET_TILING
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#define DRM_IOCTL_I915_GEM_GET_TILING
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#define DRM_IOCTL_I915_GEM_GET_APERTURE SRV_I915_GEM_GET_APERTURE
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#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID
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#define DRM_IOCTL_I915_GEM_MADVISE
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#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE
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#define DRM_IOCTL_I915_OVERLAY_ATTRS
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#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY
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#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY
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#define DRM_IOCTL_I915_GEM_WAIT
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#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE
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#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY
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#define DRM_IOCTL_I915_REG_READ
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/* Allow drivers to submit batchbuffers directly to hardware, relying
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* on the security mechanisms provided by hardware.
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File diff suppressed because it is too large
Load Diff
@ -27,12 +27,12 @@
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#ifndef KGEM_H
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#define KGEM_H
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#define HAS_DEBUG_FULL 1
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#define HAS_DEBUG_FULL 1
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#include <stdint.h>
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#include <stdbool.h>
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#include <stdarg.h>
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#include <stdarg.h>
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#include <stdio.h>
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#include "i915_drm.h"
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@ -273,6 +273,11 @@ struct kgem_bo *kgem_create_2d(struct kgem *kgem,
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int bpp,
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int tiling,
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uint32_t flags);
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struct kgem_bo *kgem_create_cpu_2d(struct kgem *kgem,
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int width,
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int height,
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int bpp,
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uint32_t flags);
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uint32_t kgem_bo_get_binding(struct kgem_bo *bo, uint32_t format);
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void kgem_bo_set_binding(struct kgem_bo *bo, uint32_t format, uint16_t offset);
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@ -314,8 +319,6 @@ static inline bool kgem_flush(struct kgem *kgem, bool flush)
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return (kgem->flush ^ flush) && kgem_ring_is_idle(kgem, kgem->ring);
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}
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#if 0
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static inline void kgem_bo_submit(struct kgem *kgem, struct kgem_bo *bo)
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{
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if (bo->exec)
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@ -337,8 +340,6 @@ static inline void kgem_bo_flush(struct kgem *kgem, struct kgem_bo *bo)
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__kgem_flush(kgem, bo);
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}
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#endif
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static inline struct kgem_bo *kgem_bo_reference(struct kgem_bo *bo)
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{
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assert(bo->refcnt);
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@ -517,6 +518,15 @@ static inline bool __kgem_bo_is_mappable(struct kgem *kgem,
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return bo->presumed_offset + kgem_bo_size(bo) <= kgem->aperture_mappable;
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}
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static inline bool kgem_bo_is_mappable(struct kgem *kgem,
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struct kgem_bo *bo)
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{
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DBG(("%s: domain=%d, offset: %d size: %d\n",
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__FUNCTION__, bo->domain, bo->presumed_offset, kgem_bo_size(bo)));
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assert(bo->refcnt);
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return __kgem_bo_is_mappable(kgem, bo);
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}
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static inline bool kgem_bo_mapped(struct kgem *kgem, struct kgem_bo *bo)
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{
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DBG(("%s: map=%p, tiling=%d, domain=%d\n",
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@ -529,15 +539,42 @@ static inline bool kgem_bo_mapped(struct kgem *kgem, struct kgem_bo *bo)
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return IS_CPU_MAP(bo->map) == !bo->tiling;
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}
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static inline bool kgem_bo_can_map(struct kgem *kgem, struct kgem_bo *bo)
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{
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if (kgem_bo_mapped(kgem, bo))
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return true;
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if (!bo->tiling && kgem->has_llc)
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return true;
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if (kgem->gen == 021 && bo->tiling == I915_TILING_Y)
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return false;
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return kgem_bo_size(bo) <= kgem->aperture_mappable / 4;
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}
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static inline bool kgem_bo_is_snoop(struct kgem_bo *bo)
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{
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assert(bo->refcnt);
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while (bo->proxy)
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bo = bo->proxy;
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return bo->snoop;
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}
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bool __kgem_busy(struct kgem *kgem, int handle);
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static inline void kgem_bo_mark_busy(struct kgem_bo *bo, int ring)
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{
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bo->rq = (struct kgem_request *)((uintptr_t)bo->rq | ring);
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}
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inline static void __kgem_bo_clear_busy(struct kgem_bo *bo)
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{
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bo->needs_flush = false;
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list_del(&bo->request);
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bo->rq = NULL;
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bo->domain = DOMAIN_NONE;
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}
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static inline bool kgem_bo_is_busy(struct kgem_bo *bo)
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{
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@ -5,6 +5,28 @@
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#include "sna.h"
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typedef struct __attribute__((packed))
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{
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unsigned handle;
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unsigned io_code;
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void *input;
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int inp_size;
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void *output;
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int out_size;
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}ioctl_t;
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static int call_service(ioctl_t *io)
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{
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int retval;
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asm volatile("int $0x40"
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:"=a"(retval)
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:"a"(68),"b"(17),"c"(io)
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:"memory","cc");
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return retval;
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};
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const struct intel_device_info *
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intel_detect_chipset(struct pci_device *pci);
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@ -15,6 +37,11 @@ static bool sna_solid_cache_init(struct sna *sna);
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struct sna *sna_device;
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static void no_render_reset(struct sna *sna)
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{
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(void)sna;
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}
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void no_render_init(struct sna *sna)
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{
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struct sna_render *render = &sna->render;
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@ -36,14 +63,14 @@ void no_render_init(struct sna *sna)
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// render->fill_one = no_render_fill_one;
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// render->clear = no_render_clear;
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// render->reset = no_render_reset;
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// render->flush = no_render_flush;
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render->reset = no_render_reset;
|
||||
render->flush = no_render_flush;
|
||||
// render->fini = no_render_fini;
|
||||
|
||||
// sna->kgem.context_switch = no_render_context_switch;
|
||||
// sna->kgem.retire = no_render_retire;
|
||||
|
||||
// if (sna->kgem.gen >= 60)
|
||||
if (sna->kgem.gen >= 60)
|
||||
sna->kgem.ring = KGEM_RENDER;
|
||||
|
||||
sna_vertex_init(sna);
|
||||
@ -594,5 +621,19 @@ intel_detect_chipset(struct pci_device *pci)
|
||||
}
|
||||
|
||||
|
||||
int drmIoctl(int fd, unsigned long request, void *arg)
|
||||
{
|
||||
ioctl_t io;
|
||||
|
||||
io.handle = fd;
|
||||
io.io_code = request;
|
||||
io.input = arg;
|
||||
io.inp_size = 64;
|
||||
io.output = NULL;
|
||||
io.out_size = 0;
|
||||
|
||||
return call_service(&io);
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
@ -57,15 +57,8 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
#define assert(x)
|
||||
|
||||
|
||||
typedef struct
|
||||
{
|
||||
unsigned handle;
|
||||
unsigned io_code;
|
||||
void *input;
|
||||
int inp_size;
|
||||
void *output;
|
||||
int out_size;
|
||||
}ioctl_t;
|
||||
int drmIoctl(int fd, unsigned long request, void *arg);
|
||||
|
||||
|
||||
#define SRV_GET_PCI_INFO 20
|
||||
#define SRV_GET_PARAM 21
|
||||
@ -74,19 +67,16 @@ typedef struct
|
||||
#define SRV_I915_GEM_PIN 24
|
||||
#define SRV_I915_GEM_SET_CACHEING 25
|
||||
#define SRV_I915_GEM_GET_APERTURE 26
|
||||
#define SRV_I915_GEM_PWRITE 27
|
||||
#define SRV_I915_GEM_BUSY 28
|
||||
|
||||
static int call_service(ioctl_t *io)
|
||||
{
|
||||
int retval;
|
||||
#define SRV_I915_GEM_SET_DOMAIN 29
|
||||
#define SRV_I915_GEM_MMAP 30
|
||||
#define SRV_I915_GEM_MMAP_GTT 31
|
||||
|
||||
asm volatile("int $0x40"
|
||||
:"=a"(retval)
|
||||
:"a"(68),"b"(17),"c"(io)
|
||||
:"memory","cc");
|
||||
|
||||
return retval;
|
||||
};
|
||||
|
||||
#define DRM_IOCTL_GEM_CLOSE SRV_DRM_GEM_CLOSE
|
||||
|
||||
#define PIXMAN_FORMAT(bpp,type,a,r,g,b) (((bpp) << 24) | \
|
||||
((type) << 16) | \
|
||||
|
Loading…
Reference in New Issue
Block a user