forked from KolibriOS/kolibrios
radeon:fix compilation & minor updates
git-svn-id: svn://kolibrios.org@1630 a494cfbc-eb01-0410-851d-a64ba20cac60
This commit is contained in:
parent
92dc7c223f
commit
2d5920a514
@ -1,5 +1,4 @@
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CC = gcc
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FASM = e:/fasm/fasm.exe
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@ -772,7 +772,4 @@ typedef struct drm_scatter_gather drm_scatter_gather_t;
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typedef struct drm_set_version drm_set_version_t;
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#endif
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#define mutex_lock(x)
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#define mutex_unlock(x)
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#endif
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@ -57,7 +57,7 @@
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//#include <linux/dma-mapping.h>
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//#include <linux/mm.h>
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//#include <linux/cdev.h>
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//#include <linux/mutex.h>
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#include <linux/mutex.h>
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//#include <asm/io.h>
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//#include <asm/mman.h>
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//#include <asm/uaccess.h>
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@ -970,7 +970,7 @@ struct drm_device {
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/** \name Locks */
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/*@{ */
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spinlock_t count_lock; /**< For inuse, drm_device::open_count, drm_device::buf_use */
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// struct mutex struct_mutex; /**< For others */
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struct mutex struct_mutex; /**< For others */
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/*@} */
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/** \name Usage Counters */
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@ -1001,7 +1001,7 @@ struct drm_device {
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/*@{ */
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struct list_head ctxlist; /**< Linked list of context handles */
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int ctx_count; /**< Number of context handles */
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// struct mutex ctxlist_mutex; /**< For ctxlist */
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struct mutex ctxlist_mutex; /**< For ctxlist */
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// struct idr ctx_idr;
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@ -26,7 +26,7 @@
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#define __DRM_CRTC_H__
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#include <linux/i2c.h>
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//#include <linux/spinlock.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#include <linux/idr.h>
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@ -574,8 +574,8 @@ struct drm_mode_group {
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*
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*/
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struct drm_mode_config {
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// struct mutex mutex; /* protects configuration (mode lists etc.) */
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// struct mutex idr_mutex; /* for IDR management */
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struct mutex mutex; /* protects configuration (mode lists etc.) */
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struct mutex idr_mutex; /* for IDR management */
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struct idr crtc_idr; /* use this idr for all IDs, fb, crtc, connector, modes - just makes life easier */
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/* this is limited to one for now */
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int num_fb;
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@ -33,7 +33,7 @@
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#ifndef __DRM_CRTC_HELPER_H__
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#define __DRM_CRTC_HELPER_H__
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//#include <linux/spinlock.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#include <linux/idr.h>
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@ -34,11 +34,8 @@
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#include "drm_hashtab.h"
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#include <linux/kref.h>
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#include <linux/list.h>
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#include <linux/spinlock.h>
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//#include <linux/wait.h>
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//#include <linux/mutex.h>
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#include <linux/mutex.h>
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//#include <linux/mm.h>
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//#include <linux/rbtree.h>
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#include <linux/bitmap.h>
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@ -391,7 +391,7 @@ struct ttm_bo_global {
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struct ttm_mem_shrink shrink;
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size_t ttm_bo_extra_size;
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size_t ttm_bo_size;
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// struct mutex device_list_mutex;
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struct mutex device_list_mutex;
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spinlock_t lru_lock;
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/**
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@ -1,4 +1,6 @@
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#include <ddk.h>
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#ifndef __SYSCALL_H__
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#define __SYSCALL_H__
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@ -240,7 +242,8 @@ static inline u32_t __PciApi(int cmd)
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"movzxb %%al, %%eax"
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:"=a" (retval)
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:"a" (cmd)
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:"ebx","ecx","edx");
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:"cc");
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return retval;
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};
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@ -854,8 +854,8 @@ EXPORT_SYMBOL(drm_mode_create_dirty_info_property);
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*/
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void drm_mode_config_init(struct drm_device *dev)
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{
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// mutex_init(&dev->mode_config.mutex);
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// mutex_init(&dev->mode_config.idr_mutex);
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mutex_init(&dev->mode_config.mutex);
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mutex_init(&dev->mode_config.idr_mutex);
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INIT_LIST_HEAD(&dev->mode_config.fb_list);
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INIT_LIST_HEAD(&dev->mode_config.fb_kernel_list);
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INIT_LIST_HEAD(&dev->mode_config.crtc_list);
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@ -121,7 +121,7 @@ struct card_info {
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struct atom_context {
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struct card_info *card;
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// struct mutex mutex;
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struct mutex mutex;
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void *bios;
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uint32_t cmd_table, data_table;
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uint16_t *iio;
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@ -17,7 +17,7 @@ CFLAGS = -c -O2 $(INCLUDES) $(DEFINES) -march=i686 -fomit-frame-pointer -fno-b
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LIBPATH:= $(DRV_TOPDIR)/ddk
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LIBS:= -ldrv -lcore
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LIBS:= -lddk -lcore
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LDFLAGS = -nostdlib -shared -s -Map atikms.map --image-base 0\
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--file-alignment 512 --section-alignment 4096
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@ -1,7 +1,9 @@
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#include <ddk.h>
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#include <linux/kernel.h>
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#include <pci.h>
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#include <errno-base.h>
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#include <linux/mutex.h>
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#include <pci.h>
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#include <syscall.h>
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static LIST_HEAD(devices);
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@ -93,10 +95,10 @@ static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
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res = &dev->resource[pos];
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reg = PCI_BASE_ADDRESS_0 + (pos << 2);
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l = PciRead32(dev->bus, dev->devfn, reg);
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PciWrite32(dev->bus, dev->devfn, reg, ~0);
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sz = PciRead32(dev->bus, dev->devfn, reg);
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PciWrite32(dev->bus, dev->devfn, reg, l);
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l = PciRead32(dev->busnr, dev->devfn, reg);
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PciWrite32(dev->busnr, dev->devfn, reg, ~0);
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sz = PciRead32(dev->busnr, dev->devfn, reg);
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PciWrite32(dev->busnr, dev->devfn, reg, l);
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if (!sz || sz == 0xffffffff)
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continue;
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@ -132,10 +134,10 @@ static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
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{
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u32_t szhi, lhi;
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lhi = PciRead32(dev->bus, dev->devfn, reg+4);
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PciWrite32(dev->bus, dev->devfn, reg+4, ~0);
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szhi = PciRead32(dev->bus, dev->devfn, reg+4);
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PciWrite32(dev->bus, dev->devfn, reg+4, lhi);
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lhi = PciRead32(dev->busnr, dev->devfn, reg+4);
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PciWrite32(dev->busnr, dev->devfn, reg+4, ~0);
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szhi = PciRead32(dev->busnr, dev->devfn, reg+4);
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PciWrite32(dev->busnr, dev->devfn, reg+4, lhi);
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sz64 = ((u64_t)szhi << 32) | raw_sz;
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l64 = ((u64_t)lhi << 32) | l;
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sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK);
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@ -160,9 +162,9 @@ static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
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else if (lhi)
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{
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/* 64-bit wide address, treat as disabled */
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PciWrite32(dev->bus, dev->devfn, reg,
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PciWrite32(dev->busnr, dev->devfn, reg,
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l & ~(u32_t)PCI_BASE_ADDRESS_MEM_MASK);
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PciWrite32(dev->bus, dev->devfn, reg+4, 0);
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PciWrite32(dev->busnr, dev->devfn, reg+4, 0);
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res->start = 0;
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res->end = sz;
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}
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@ -175,10 +177,10 @@ static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
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dev->rom_base_reg = rom;
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res = &dev->resource[PCI_ROM_RESOURCE];
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l = PciRead32(dev->bus, dev->devfn, rom);
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PciWrite32(dev->bus, dev->devfn, rom, ~PCI_ROM_ADDRESS_ENABLE);
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sz = PciRead32(dev->bus, dev->devfn, rom);
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PciWrite32(dev->bus, dev->devfn, rom, l);
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l = PciRead32(dev->busnr, dev->devfn, rom);
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PciWrite32(dev->busnr, dev->devfn, rom, ~PCI_ROM_ADDRESS_ENABLE);
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sz = PciRead32(dev->busnr, dev->devfn, rom);
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PciWrite32(dev->busnr, dev->devfn, rom, l);
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if (l == 0xffffffff)
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l = 0;
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@ -203,10 +205,10 @@ static void pci_read_irq(struct pci_dev *dev)
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{
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u8_t irq;
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irq = PciRead8(dev->bus, dev->devfn, PCI_INTERRUPT_PIN);
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irq = PciRead8(dev->busnr, dev->devfn, PCI_INTERRUPT_PIN);
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dev->pin = irq;
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if (irq)
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PciRead8(dev->bus, dev->devfn, PCI_INTERRUPT_LINE);
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PciRead8(dev->busnr, dev->devfn, PCI_INTERRUPT_LINE);
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dev->irq = irq;
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};
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@ -215,7 +217,7 @@ static int pci_setup_device(struct pci_dev *dev)
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{
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u32_t class;
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class = PciRead32(dev->bus, dev->devfn, PCI_CLASS_REVISION);
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class = PciRead32(dev->busnr, dev->devfn, PCI_CLASS_REVISION);
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dev->revision = class & 0xff;
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class >>= 8; /* upper 3 bytes */
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dev->class = class;
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@ -234,8 +236,8 @@ static int pci_setup_device(struct pci_dev *dev)
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goto bad;
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pci_read_irq(dev);
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pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
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dev->subsystem_vendor = PciRead16(dev->bus, dev->devfn,PCI_SUBSYSTEM_VENDOR_ID);
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dev->subsystem_device = PciRead16(dev->bus, dev->devfn, PCI_SUBSYSTEM_ID);
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dev->subsystem_vendor = PciRead16(dev->busnr, dev->devfn,PCI_SUBSYSTEM_VENDOR_ID);
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dev->subsystem_device = PciRead16(dev->busnr, dev->devfn, PCI_SUBSYSTEM_ID);
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/*
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* Do the ugly legacy mode stuff here rather than broken chip
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@ -247,7 +249,7 @@ static int pci_setup_device(struct pci_dev *dev)
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{
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u8_t progif;
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progif = PciRead8(dev->bus, dev->devfn,PCI_CLASS_PROG);
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progif = PciRead8(dev->busnr, dev->devfn,PCI_CLASS_PROG);
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if ((progif & 1) == 0)
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{
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dev->resource[0].start = 0x1F0;
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@ -285,11 +287,11 @@ static int pci_setup_device(struct pci_dev *dev)
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goto bad;
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pci_read_irq(dev);
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pci_read_bases(dev, 1, 0);
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dev->subsystem_vendor = PciRead16(dev->bus,
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dev->subsystem_vendor = PciRead16(dev->busnr,
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dev->devfn,
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PCI_CB_SUBSYSTEM_VENDOR_ID);
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dev->subsystem_device = PciRead16(dev->bus,
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dev->subsystem_device = PciRead16(dev->busnr,
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dev->devfn,
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PCI_CB_SUBSYSTEM_ID);
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break;
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@ -352,7 +354,7 @@ static pci_dev_t* pci_scan_device(u32_t bus, int devfn)
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if(unlikely(dev == NULL))
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return NULL;
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dev->pci_dev.bus = bus;
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dev->pci_dev.busnr = bus;
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dev->pci_dev.devfn = devfn;
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dev->pci_dev.hdr_type = hdr & 0x7f;
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dev->pci_dev.multifunction = !!(hdr & 0x80);
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@ -503,140 +505,14 @@ int pci_find_capability(struct pci_dev *dev, int cap)
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{
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int pos;
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pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
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pos = __pci_bus_find_cap_start(dev->busnr, dev->devfn, dev->hdr_type);
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if (pos)
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pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
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pos = __pci_find_next_cap(dev->busnr, dev->devfn, pos, cap);
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return pos;
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}
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#if 0
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/**
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* pci_set_power_state - Set the power state of a PCI device
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* @dev: PCI device to be suspended
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* @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering
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*
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* Transition a device to a new power state, using the Power Management
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* Capabilities in the device's config space.
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*
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* RETURN VALUE:
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* -EINVAL if trying to enter a lower state than we're already in.
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* 0 if we're already in the requested state.
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* -EIO if device does not support PCI PM.
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* 0 if we can successfully change the power state.
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*/
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int
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pci_set_power_state(struct pci_dev *dev, pci_power_t state)
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{
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int pm, need_restore = 0;
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u16 pmcsr, pmc;
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/* bound the state we're entering */
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if (state > PCI_D3hot)
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state = PCI_D3hot;
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/*
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* If the device or the parent bridge can't support PCI PM, ignore
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* the request if we're doing anything besides putting it into D0
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* (which would only happen on boot).
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*/
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if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
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return 0;
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/* find PCI PM capability in list */
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pm = pci_find_capability(dev, PCI_CAP_ID_PM);
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/* abort if the device doesn't support PM capabilities */
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if (!pm)
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return -EIO;
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/* Validate current state:
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* Can enter D0 from any state, but if we can only go deeper
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* to sleep if we're already in a low power state
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*/
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if (state != PCI_D0 && dev->current_state > state) {
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printk(KERN_ERR "%s(): %s: state=%d, current state=%d\n",
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__FUNCTION__, pci_name(dev), state, dev->current_state);
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return -EINVAL;
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} else if (dev->current_state == state)
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return 0; /* we're already there */
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pci_read_config_word(dev,pm + PCI_PM_PMC,&pmc);
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if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
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printk(KERN_DEBUG
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"PCI: %s has unsupported PM cap regs version (%u)\n",
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pci_name(dev), pmc & PCI_PM_CAP_VER_MASK);
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return -EIO;
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}
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/* check if this device supports the desired state */
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if (state == PCI_D1 && !(pmc & PCI_PM_CAP_D1))
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return -EIO;
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else if (state == PCI_D2 && !(pmc & PCI_PM_CAP_D2))
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return -EIO;
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pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
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/* If we're (effectively) in D3, force entire word to 0.
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* This doesn't affect PME_Status, disables PME_En, and
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* sets PowerState to 0.
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*/
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switch (dev->current_state) {
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case PCI_D0:
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case PCI_D1:
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case PCI_D2:
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pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
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pmcsr |= state;
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break;
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case PCI_UNKNOWN: /* Boot-up */
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if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
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&& !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
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need_restore = 1;
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/* Fall-through: force to D0 */
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default:
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pmcsr = 0;
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break;
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}
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/* enter specified state */
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pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr);
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/* Mandatory power management transition delays */
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/* see PCI PM 1.1 5.6.1 table 18 */
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if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
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msleep(pci_pm_d3_delay);
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else if (state == PCI_D2 || dev->current_state == PCI_D2)
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udelay(200);
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/*
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* Give firmware a chance to be called, such as ACPI _PRx, _PSx
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* Firmware method after native method ?
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*/
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if (platform_pci_set_power_state)
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platform_pci_set_power_state(dev, state);
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dev->current_state = state;
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/* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
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* INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
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* from D3hot to D0 _may_ perform an internal reset, thereby
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* going to "D0 Uninitialized" rather than "D0 Initialized".
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* For example, at least some versions of the 3c905B and the
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* 3c556B exhibit this behaviour.
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*
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* At least some laptop BIOSen (e.g. the Thinkpad T21) leave
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* devices in a D3hot state at boot. Consequently, we need to
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* restore at least the BARs so that the device will be
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* accessible to its driver.
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*/
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if (need_restore)
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pci_restore_bars(dev);
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return 0;
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}
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#endif
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int pcibios_enable_resources(struct pci_dev *dev, int mask)
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{
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@ -644,7 +520,7 @@ int pcibios_enable_resources(struct pci_dev *dev, int mask)
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int idx;
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struct resource *r;
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|
||||
cmd = PciRead16(dev->bus, dev->devfn, PCI_COMMAND);
|
||||
cmd = PciRead16(dev->busnr, dev->devfn, PCI_COMMAND);
|
||||
old_cmd = cmd;
|
||||
for (idx = 0; idx < PCI_NUM_RESOURCES; idx++)
|
||||
{
|
||||
@ -672,7 +548,7 @@ int pcibios_enable_resources(struct pci_dev *dev, int mask)
|
||||
if (cmd != old_cmd) {
|
||||
printk("PCI: Enabling device %s (%04x -> %04x)\n",
|
||||
pci_name(dev), old_cmd, cmd);
|
||||
PciWrite16(dev->bus, dev->devfn, PCI_COMMAND, cmd);
|
||||
PciWrite16(dev->busnr, dev->devfn, PCI_COMMAND, cmd);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
@ -766,7 +642,6 @@ struct pci_device_id* find_pci_device(pci_dev_t* pdev, struct pci_device_id *idl
|
||||
}
|
||||
};
|
||||
}
|
||||
|
||||
return NULL;
|
||||
};
|
||||
|
||||
@ -793,53 +668,6 @@ void *pci_map_rom(struct pci_dev *pdev, size_t *size)
|
||||
void *rom;
|
||||
|
||||
#if 0
|
||||
/*
|
||||
* IORESOURCE_ROM_SHADOW set on x86, x86_64 and IA64 supports legacy
|
||||
* memory map if the VGA enable bit of the Bridge Control register is
|
||||
* set for embedded VGA.
|
||||
*/
|
||||
if (res->flags & IORESOURCE_ROM_SHADOW) {
|
||||
/* primary video rom always starts here */
|
||||
start = (u32_t)0xC0000;
|
||||
*size = 0x20000; /* cover C000:0 through E000:0 */
|
||||
} else {
|
||||
if (res->flags & (IORESOURCE_ROM_COPY | IORESOURCE_ROM_BIOS_COPY)) {
|
||||
*size = pci_resource_len(pdev, PCI_ROM_RESOURCE);
|
||||
return (void *)(unsigned long)
|
||||
pci_resource_start(pdev, PCI_ROM_RESOURCE);
|
||||
} else {
|
||||
/* assign the ROM an address if it doesn't have one */
|
||||
//if (res->parent == NULL &&
|
||||
// pci_assign_resource(pdev,PCI_ROM_RESOURCE))
|
||||
// return NULL;
|
||||
start = pci_resource_start(pdev, PCI_ROM_RESOURCE);
|
||||
*size = pci_resource_len(pdev, PCI_ROM_RESOURCE);
|
||||
if (*size == 0)
|
||||
return NULL;
|
||||
|
||||
/* Enable ROM space decodes */
|
||||
if (pci_enable_rom(pdev))
|
||||
return NULL;
|
||||
}
|
||||
}
|
||||
|
||||
rom = ioremap(start, *size);
|
||||
if (!rom) {
|
||||
/* restore enable if ioremap fails */
|
||||
if (!(res->flags & (IORESOURCE_ROM_ENABLE |
|
||||
IORESOURCE_ROM_SHADOW |
|
||||
IORESOURCE_ROM_COPY)))
|
||||
pci_disable_rom(pdev);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/*
|
||||
* Try to find the true size of the ROM since sometimes the PCI window
|
||||
* size is much larger than the actual size of the ROM.
|
||||
* True size is important if the ROM is going to be copied.
|
||||
*/
|
||||
*size = pci_get_rom_size(rom, *size);
|
||||
|
||||
#endif
|
||||
|
||||
unsigned char tmp[32];
|
||||
|
@ -60,6 +60,7 @@
|
||||
* are considered as fatal)
|
||||
*/
|
||||
|
||||
#include <ddk.h>
|
||||
#include <asm/atomic.h>
|
||||
|
||||
#include <linux/list.h>
|
||||
@ -331,6 +332,7 @@ struct radeon_bo_list {
|
||||
* GEM objects.
|
||||
*/
|
||||
struct radeon_gem {
|
||||
struct mutex mutex;
|
||||
struct list_head objects;
|
||||
};
|
||||
|
||||
@ -466,7 +468,7 @@ struct radeon_ib {
|
||||
* mutex protects scheduled_ibs, ready, alloc_bm
|
||||
*/
|
||||
struct radeon_ib_pool {
|
||||
// struct mutex mutex;
|
||||
struct mutex mutex;
|
||||
struct radeon_bo *robj;
|
||||
struct list_head bogus_ib;
|
||||
struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
|
||||
@ -486,7 +488,7 @@ struct radeon_cp {
|
||||
uint64_t gpu_addr;
|
||||
uint32_t align_mask;
|
||||
uint32_t ptr_mask;
|
||||
// struct mutex mutex;
|
||||
struct mutex mutex;
|
||||
bool ready;
|
||||
};
|
||||
|
||||
@ -507,6 +509,7 @@ struct r600_ih {
|
||||
};
|
||||
|
||||
struct r600_blit {
|
||||
struct mutex mutex;
|
||||
struct radeon_bo *shader_obj;
|
||||
u64 shader_gpu_addr;
|
||||
u32 vs_offset, ps_offset;
|
||||
@ -539,7 +542,7 @@ void radeon_ring_fini(struct radeon_device *rdev);
|
||||
struct radeon_cs_reloc {
|
||||
// struct drm_gem_object *gobj;
|
||||
struct radeon_bo *robj;
|
||||
// struct radeon_bo_list lobj;
|
||||
struct radeon_bo_list lobj;
|
||||
uint32_t handle;
|
||||
uint32_t flags;
|
||||
};
|
||||
@ -745,7 +748,7 @@ struct radeon_power_state {
|
||||
#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
|
||||
|
||||
struct radeon_pm {
|
||||
// struct mutex mutex;
|
||||
struct mutex mutex;
|
||||
// struct delayed_work idle_work;
|
||||
enum radeon_pm_state state;
|
||||
enum radeon_pm_action planned_action;
|
||||
@ -962,7 +965,7 @@ struct radeon_device {
|
||||
struct radeon_gem gem;
|
||||
struct radeon_pm pm;
|
||||
uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
|
||||
// struct mutex cs_mutex;
|
||||
struct mutex cs_mutex;
|
||||
struct radeon_wb wb;
|
||||
struct radeon_dummy_page dummy_page;
|
||||
bool gpu_lockup;
|
||||
@ -977,6 +980,7 @@ struct radeon_device {
|
||||
struct r600_blit r600_blit;
|
||||
int msi_enabled; /* msi enabled */
|
||||
int num_crtc; /* number of crtcs */
|
||||
struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
|
||||
|
||||
/* audio stuff */
|
||||
// struct timer_list audio_timer;
|
||||
|
@ -565,6 +565,7 @@ int radeon_atombios_init(struct radeon_device *rdev)
|
||||
atom_card_info->pll_write = cail_pll_write;
|
||||
|
||||
rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
|
||||
mutex_init(&rdev->mode_info.atom_context->mutex);
|
||||
radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
|
||||
atom_allocate_fb_scratch(rdev->mode_info.atom_context);
|
||||
return 0;
|
||||
@ -711,9 +712,12 @@ int radeon_device_init(struct radeon_device *rdev,
|
||||
rdev->accel_working = false;
|
||||
/* mutex initialization are all done here so we
|
||||
* can recall function without having locking issues */
|
||||
// mutex_init(&rdev->cs_mutex);
|
||||
// mutex_init(&rdev->ib_pool.mutex);
|
||||
// mutex_init(&rdev->cp.mutex);
|
||||
mutex_init(&rdev->cs_mutex);
|
||||
mutex_init(&rdev->ib_pool.mutex);
|
||||
mutex_init(&rdev->cp.mutex);
|
||||
mutex_init(&rdev->dc_hw_i2c_mutex);
|
||||
mutex_init(&rdev->gem.mutex);
|
||||
mutex_init(&rdev->pm.mutex);
|
||||
// rwlock_init(&rdev->fence_drv.lock);
|
||||
|
||||
/* Set asic functions */
|
||||
@ -759,14 +763,6 @@ int radeon_device_init(struct radeon_device *rdev,
|
||||
DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
|
||||
DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
|
||||
|
||||
/* if we have > 1 VGA cards, then disable the radeon VGA resources */
|
||||
/* this will fail for cards that aren't VGA class devices, just
|
||||
* ignore it */
|
||||
// r = vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
|
||||
// if (r) {
|
||||
// return -EINVAL;
|
||||
// }
|
||||
|
||||
r = radeon_init(rdev);
|
||||
if (r)
|
||||
return r;
|
||||
@ -872,6 +868,17 @@ int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent)
|
||||
dev->pci_device = pdev->device;
|
||||
dev->pci_vendor = pdev->vendor;
|
||||
|
||||
INIT_LIST_HEAD(&dev->filelist);
|
||||
INIT_LIST_HEAD(&dev->ctxlist);
|
||||
INIT_LIST_HEAD(&dev->vmalist);
|
||||
INIT_LIST_HEAD(&dev->maplist);
|
||||
|
||||
spin_lock_init(&dev->count_lock);
|
||||
spin_lock_init(&dev->drw_lock);
|
||||
mutex_init(&dev->struct_mutex);
|
||||
mutex_init(&dev->ctxlist_mutex);
|
||||
|
||||
|
||||
ret = radeon_driver_load_kms(dev, ent->driver_data );
|
||||
if (ret)
|
||||
goto err_g4;
|
||||
@ -1037,7 +1044,6 @@ u32_t drvEntry(int action, char *cmdline)
|
||||
dbgprintf("Radeon RC10 cmdline %s\n", cmdline);
|
||||
|
||||
enum_pci_devices();
|
||||
|
||||
ent = find_pci_device(&device, pciidlist);
|
||||
|
||||
if( unlikely(ent == NULL) )
|
||||
|
@ -810,12 +810,7 @@ static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
|
||||
if (fb->fbdev)
|
||||
radeonfb_remove(dev, fb);
|
||||
|
||||
// if (radeon_fb->obj) {
|
||||
// radeon_gem_object_unpin(radeon_fb->obj);
|
||||
// mutex_lock(&dev->struct_mutex);
|
||||
// drm_gem_object_unreference(radeon_fb->obj);
|
||||
// mutex_unlock(&dev->struct_mutex);
|
||||
// }
|
||||
|
||||
drm_framebuffer_cleanup(fb);
|
||||
kfree(radeon_fb);
|
||||
}
|
||||
|
@ -286,8 +286,6 @@ int radeonfb_create(struct drm_device *dev,
|
||||
DRM_INFO("fb depth is %d\n", fb->depth);
|
||||
DRM_INFO(" pitch is %d\n", fb->pitch);
|
||||
|
||||
dbgprintf("fb = %x\n", fb);
|
||||
|
||||
fb->fbdev = info;
|
||||
rfbdev->rfb = rfb;
|
||||
rfbdev->rdev = rdev;
|
||||
|
@ -90,6 +90,7 @@ static void radeon_i2c_do_lock(struct radeon_i2c_chan *i2c, int lock_state)
|
||||
WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
|
||||
R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3)));
|
||||
}
|
||||
mutex_unlock(&rdev->dc_hw_i2c_mutex);
|
||||
}
|
||||
}
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user