forked from KolibriOS/kolibrios
drm: 3.17-rc5
git-svn-id: svn://kolibrios.org@5128 a494cfbc-eb01-0410-851d-a64ba20cac60
This commit is contained in:
Sergey Semyonov (Serge)
parent
1415fa22e9
commit
347bbd1570
@ -1182,12 +1182,17 @@ static int i915_load_modeset_init(struct drm_device *dev)
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intel_power_domains_init_hw(dev_priv);
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/*
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* We enable some interrupt sources in our postinstall hooks, so mark
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* interrupts as enabled _before_ actually enabling them to avoid
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* special cases in our ordering checks.
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*/
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dev_priv->pm._irqs_disabled = false;
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ret = drm_irq_install(dev, dev->pdev->irq);
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if (ret)
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goto cleanup_gem_stolen;
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dev_priv->pm._irqs_disabled = false;
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/* Important: The output setup functions called by modeset_init need
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* working irqs for e.g. gmbus and dp aux transfers. */
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intel_modeset_init(dev);
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@ -195,6 +195,7 @@ enum hpd_pin {
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if ((1 << (domain)) & (mask))
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struct drm_i915_private;
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struct i915_mm_struct;
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struct i915_mmu_object;
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enum intel_dpll_id {
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@ -1511,9 +1512,8 @@ struct drm_i915_private {
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struct i915_gtt gtt; /* VM representing the global address space */
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struct i915_gem_mm mm;
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#if defined(CONFIG_MMU_NOTIFIER)
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DECLARE_HASHTABLE(mmu_notifiers, 7);
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#endif
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DECLARE_HASHTABLE(mm_structs, 7);
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struct mutex mm_lock;
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/* Kernel Modesetting */
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@ -1819,8 +1819,8 @@ struct drm_i915_gem_object {
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unsigned workers :4;
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#define I915_GEM_USERPTR_MAX_WORKERS 15
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struct mm_struct *mm;
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struct i915_mmu_object *mn;
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struct i915_mm_struct *mm;
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struct i915_mmu_object *mmu_object;
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struct work_struct *work;
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} userptr;
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};
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@ -334,16 +334,20 @@
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#define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
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#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
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#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
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#define COLOR_BLT_CMD (2<<29 | 0x40<<22 | (5-2))
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#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
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#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
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#define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
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#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
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#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
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#define BLT_WRITE_A (2<<20)
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#define BLT_WRITE_RGB (1<<20)
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#define BLT_WRITE_RGBA (BLT_WRITE_RGB | BLT_WRITE_A)
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#define BLT_DEPTH_8 (0<<24)
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#define BLT_DEPTH_16_565 (1<<24)
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#define BLT_DEPTH_16_1555 (2<<24)
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#define BLT_DEPTH_32 (3<<24)
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#define BLT_ROP_GXCOPY (0xcc<<16)
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#define BLT_ROP_SRC_COPY (0xcc<<16)
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#define BLT_ROP_COLOR_COPY (0xf0<<16)
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#define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */
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#define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */
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#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
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@ -675,6 +675,13 @@ static int init_render_ring(struct intel_engine_cs *ring)
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static void render_ring_cleanup(struct intel_engine_cs *ring)
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{
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struct drm_device *dev = ring->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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if (dev_priv->semaphore_obj) {
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i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
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drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
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dev_priv->semaphore_obj = NULL;
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}
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if (ring->scratch.obj == NULL)
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return;
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@ -1353,54 +1360,66 @@ i965_dispatch_execbuffer(struct intel_engine_cs *ring,
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/* Just userspace ABI convention to limit the wa batch bo to a resonable size */
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#define I830_BATCH_LIMIT (256*1024)
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#define I830_TLB_ENTRIES (2)
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#define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
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static int
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i830_dispatch_execbuffer(struct intel_engine_cs *ring,
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u64 offset, u32 len,
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unsigned flags)
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{
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u32 cs_offset = ring->scratch.gtt_offset;
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int ret;
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if (flags & I915_DISPATCH_PINNED) {
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ret = intel_ring_begin(ring, 4);
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ret = intel_ring_begin(ring, 6);
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if (ret)
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return ret;
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intel_ring_emit(ring, MI_BATCH_BUFFER);
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intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
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intel_ring_emit(ring, offset + len - 8);
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/* Evict the invalid PTE TLBs */
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intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
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intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
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intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
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intel_ring_emit(ring, cs_offset);
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intel_ring_emit(ring, 0xdeadbeef);
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intel_ring_emit(ring, MI_NOOP);
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intel_ring_advance(ring);
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} else {
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u32 cs_offset = ring->scratch.gtt_offset;
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if ((flags & I915_DISPATCH_PINNED) == 0) {
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if (len > I830_BATCH_LIMIT)
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return -ENOSPC;
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ret = intel_ring_begin(ring, 9+3);
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ret = intel_ring_begin(ring, 6 + 2);
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if (ret)
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return ret;
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/* Blit the batch (which has now all relocs applied) to the stable batch
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* scratch bo area (so that the CS never stumbles over its tlb
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* invalidation bug) ... */
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intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD |
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XY_SRC_COPY_BLT_WRITE_ALPHA |
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XY_SRC_COPY_BLT_WRITE_RGB);
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intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096);
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intel_ring_emit(ring, 0);
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intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024);
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/* Blit the batch (which has now all relocs applied) to the
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* stable batch scratch bo area (so that the CS never
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* stumbles over its tlb invalidation bug) ...
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*/
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intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
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intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
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intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 1024);
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intel_ring_emit(ring, cs_offset);
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intel_ring_emit(ring, 0);
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intel_ring_emit(ring, 4096);
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intel_ring_emit(ring, offset);
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intel_ring_emit(ring, MI_FLUSH);
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intel_ring_emit(ring, MI_NOOP);
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intel_ring_advance(ring);
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/* ... and execute it. */
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intel_ring_emit(ring, MI_BATCH_BUFFER);
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intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
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intel_ring_emit(ring, cs_offset + len - 8);
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intel_ring_advance(ring);
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offset = cs_offset;
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}
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ret = intel_ring_begin(ring, 4);
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if (ret)
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return ret;
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intel_ring_emit(ring, MI_BATCH_BUFFER);
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intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
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intel_ring_emit(ring, offset + len - 8);
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intel_ring_emit(ring, MI_NOOP);
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intel_ring_advance(ring);
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return 0;
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}
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@ -2179,7 +2198,7 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
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/* Workaround batchbuffer to combat CS tlb bug. */
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if (HAS_BROKEN_CS_TLB(dev)) {
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obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT);
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obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
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if (obj == NULL) {
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DRM_ERROR("Failed to allocate batch bo\n");
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return -ENOMEM;
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@ -186,7 +186,7 @@ u32_t __attribute__((externally_visible)) drvEntry(int action, char *cmdline)
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if( GetService("DISPLAY") != 0 )
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return 0;
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printf("\ni915 v3.17-rc3 build %s %s\nusage: i915 [options]\n"
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printf("\ni915 v3.17-rc5 build %s %s\nusage: i915 [options]\n"
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"-pm=<0,1> Enable powersavings, fbc, downclocking, etc. (default: 1 - true)\n",
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__DATE__, __TIME__);
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printf("-rc6=<-1,0-7> Enable power-saving render C-state 6.\n"
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@ -405,16 +405,13 @@ bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector)
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u8 msg[DP_DPCD_SIZE];
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int ret;
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char dpcd_hex_dump[DP_DPCD_SIZE * 3];
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ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_DPCD_REV, msg,
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DP_DPCD_SIZE);
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if (ret > 0) {
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memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);
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hex_dump_to_buffer(dig_connector->dpcd, sizeof(dig_connector->dpcd),
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32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
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DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
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DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd),
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dig_connector->dpcd);
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radeon_dp_probe_oui(radeon_connector);
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@ -134,7 +134,7 @@ u32_t __attribute__((externally_visible)) drvEntry(int action, char *cmdline)
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if( GetService("DISPLAY") != 0 )
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return 0;
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printf("Radeon v3.17-rc3 cmdline %s\n", cmdline);
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printf("Radeon v3.17-rc5 cmdline %s\n", cmdline);
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if( cmdline && *cmdline )
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parse_cmdline(cmdline, &usermode, log, &radeon_modeset);
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@ -2769,8 +2769,8 @@ bool r600_semaphore_ring_emit(struct radeon_device *rdev,
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radeon_ring_write(ring, lower_32_bits(addr));
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radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel);
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/* PFP_SYNC_ME packet only exists on 7xx+ */
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if (emit_wait && (rdev->family >= CHIP_RV770)) {
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/* PFP_SYNC_ME packet only exists on 7xx+, only enable it on eg+ */
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if (emit_wait && (rdev->family >= CHIP_CEDAR)) {
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/* Prevent the PFP from running ahead of the semaphore wait */
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radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
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radeon_ring_write(ring, 0x0);
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@ -447,6 +447,13 @@ static bool radeon_atom_apply_quirks(struct drm_device *dev,
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}
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}
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/* Fujitsu D3003-S2 board lists DVI-I as DVI-I and VGA */
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if ((dev->pdev->device == 0x9805) &&
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(dev->pdev->subsystem_vendor == 0x1734) &&
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(dev->pdev->subsystem_device == 0x11bd)) {
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if (*connector_type == DRM_MODE_CONNECTOR_VGA)
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return false;
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}
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return true;
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}
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@ -2281,19 +2288,31 @@ static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *r
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(controller->ucFanParameters &
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ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
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rdev->pm.int_thermal_type = THERMAL_TYPE_KV;
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} else if ((controller->ucType ==
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ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
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(controller->ucType ==
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ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) ||
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(controller->ucType ==
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ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL)) {
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DRM_INFO("Special thermal controller config\n");
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} else if (controller->ucType ==
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ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) {
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DRM_INFO("External GPIO thermal controller %s fan control\n",
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(controller->ucFanParameters &
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ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
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rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL_GPIO;
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} else if (controller->ucType ==
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ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) {
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DRM_INFO("ADT7473 with internal thermal controller %s fan control\n",
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(controller->ucFanParameters &
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ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
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rdev->pm.int_thermal_type = THERMAL_TYPE_ADT7473_WITH_INTERNAL;
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} else if (controller->ucType ==
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ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL) {
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DRM_INFO("EMC2103 with internal thermal controller %s fan control\n",
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(controller->ucFanParameters &
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ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
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rdev->pm.int_thermal_type = THERMAL_TYPE_EMC2103_WITH_INTERNAL;
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} else if (controller->ucType < ARRAY_SIZE(pp_lib_thermal_controller_names)) {
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DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
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pp_lib_thermal_controller_names[controller->ucType],
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controller->ucI2cAddress >> 1,
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(controller->ucFanParameters &
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ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
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rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL;
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i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
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rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
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if (rdev->pm.i2c_bus) {
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@ -34,7 +34,7 @@
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int radeon_semaphore_create(struct radeon_device *rdev,
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struct radeon_semaphore **semaphore)
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{
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uint32_t *cpu_addr;
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uint64_t *cpu_addr;
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int i, r;
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*semaphore = kmalloc(sizeof(struct radeon_semaphore), GFP_KERNEL);
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