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minor corrections

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git-svn-id: svn://kolibrios.org@3526 a494cfbc-eb01-0410-851d-a64ba20cac60
This commit is contained in:
Artem Jerdev (art_zh) 2013-05-21 20:28:08 +00:00
parent df1bbc6819
commit 3aef84d056
4 changed files with 39 additions and 84 deletions
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102
kernel/branches/Kolibri-A/trunk/bus/HT.inc
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@ -92,80 +92,16 @@ rs7xx_unlock_bar3:
;***************************************************************************
; Function
; rs7xx_pcie_init:
; fusion_pcie_init:
;
; Description
; PCIe extended (memory-mapped) config space detection
; PCIe extended config space detection and mapping
;
;***************************************************************************
align 4
rs7xx_pcie_init:
call rs7xx_unlock_bar3
mov al, 0x7C ; NB_IOC_CFG_CNTL
call rs7xx_nbconfig_read_pci
mov ebx, eax
; call rs7xx_nbconfig_flush_pci
test ebx, 0x20000000 ; BAR3 locked?
jz $
mov al, 0x84 ; NB_PCI_ARB
call rs7xx_nbconfig_read_pci
shr eax,16
and ax, 7 ; the Bus range lays here:
jnz @f
mov ax, 8 ; 1=2Mb, 2=4MB, 3=8MB, 4=16MB
@@:
mov word[PCIe_bus_range-OS_BASE], ax ; 5=32Mb, 6=64MB, 7=128Mb, 8=256Mb
mov cl, al
call rs7xx_nbconfig_flush_pci
dec cl ; <4M ?
jz @f
dec cl ; one PDE needed anyway
@@:
mov ebx, 1
shl ebx, cl
mov word[mmio_pcie_cfg_pdes-OS_BASE], bx ; 1..64 PDE(s) needed,
shl ebx, 22
mov dword[mmio_pcie_cfg_lim-OS_BASE], ebx ; or 4..256Mb space to map
dec dword[mmio_pcie_cfg_lim-OS_BASE]
mov al, 0x1C ; NB_BAR3_PCIEXP_MMCFG
call rs7xx_nbconfig_read_pci
mov ebx, eax
call rs7xx_nbconfig_flush_pci
mov eax, ebx
and eax, 0xFFE00000 ; valid bits [31..21]
jz $ ; invalid map!
.addr_found:
mov dword[mmio_pcie_cfg_addr-OS_BASE], eax ; physical address (lower 32 bits)
add dword[mmio_pcie_cfg_lim-OS_BASE], eax
; ---- common mapping procedure ----
; (eax = phys. address of PCIe conf.space)
;
map_pcie_pages:
or eax, (PG_NOCACHE + PG_SHARED + PG_LARGE + PG_UW) ; UW is unsafe!
mov ecx, PCIe_CONFIG_SPACE ; linear address
mov ebx, ecx
shr ebx, 20
add ebx, (sys_pgdir - OS_BASE) ; PgDir entry @
mov dl, byte[mmio_pcie_cfg_pdes-OS_BASE] ; 1 page = 4M in address space
cmp dl, 0x34 ; =(USER_DMA_BUFFER - PCIe_CONFIG_SPACE) / 4M
jb @f
mov dl, 0x33
mov byte[mmio_pcie_cfg_pdes-OS_BASE], dl
@@:
xor dx, dx ; PDEs counter
.write_pde:
mov dword[ebx], eax ; map 4 buses
add bx, 4 ; new PDE
add eax, 0x400000 ; +4M phys.
add ecx, 0x400000 ; +4M lin.
cmp dl, byte[mmio_pcie_cfg_pdes-OS_BASE]
jae pcie_cfg_mapped
inc dl
jmp .write_pde
; ---- stepping 10h CPUs and Fusion APUs: the configspace is stored in MSR_C001_0058 ----
align 4
@ -192,10 +128,35 @@ fusion_pcie_init:
add edx, eax ; the upper configspace limit
mov dword[mmio_pcie_cfg_lim-OS_BASE], edx
pcie_cfg_mapped:
; ---- large pages mapping ----
; (eax = phys. address of PCIe conf.space)
;
.map_pcie_pages:
or eax, (PG_NOCACHE + PG_SHARED + PG_LARGE + PG_UW) ; UW is unsafe!
mov ecx, PCIe_CONFIG_SPACE ; linear address
mov ebx, ecx
shr ebx, 20
add ebx, (sys_pgdir - OS_BASE) ; PgDir entry @
mov dl, byte[mmio_pcie_cfg_pdes-OS_BASE] ; 1 page = 4M in address space
cmp dl, 0x34 ; =(USER_DMA_BUFFER - PCIe_CONFIG_SPACE) / 4M
jb @f
mov dl, 0x33
mov byte[mmio_pcie_cfg_pdes-OS_BASE], dl
@@:
xor dx, dx ; PDEs counter
.write_pde:
mov dword[ebx], eax ; map 4 buses
add bx, 4 ; new PDE
add eax, 0x400000 ; +4M phys.
add ecx, 0x400000 ; +4M lin.
cmp dl, byte[mmio_pcie_cfg_pdes-OS_BASE]
jae .pcie_cfg_mapped
inc dl
jmp .write_pde
.pcie_cfg_mapped:
create_mmio_pte:
mov ecx, mmio_pte ; physical address
or ecx, (PG_NOCACHE + PG_SHARED)
mov ebx, FUSION_MMIO ; linear address
@ -203,11 +164,12 @@ create_mmio_pte:
add ebx, (sys_pgdir - OS_BASE) ; PgDir entry @
mov dword[ebx], ecx ; Fusion MMIO tables
map_apic_mmio:
; ---- short page mapping ----
.map_apic_mmio:
mov ecx, 0x01B ; APIC BAR
rdmsr
and eax, 0xFFFFF000 ; physical address
or eax, (PG_NOCACHE + PG_SHARED + PG_UW) ; UW is unsafe!
or eax, (PG_NOCACHE + PG_SHARED)
mov dword[mmio_pte + 0], eax
ret ; <<< OK >>>

8
kernel/branches/Kolibri-A/trunk/const.inc
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@ -370,18 +370,18 @@ PG_SHARED equ 0x200
;;;;;;;;;;;boot time variables
;BOOT_BPP equ 0x9000 ;byte bits per pixel
BOOT_SCANLINE equ 0x9001 ;word scanline length
BOOT_VESA_MODE equ 0x9008 ;word vesa video mode
;BOOT_SCANLINE equ 0x9001 ;word scanline length
;BOOT_VESA_MODE equ 0x9008 ;word vesa video mode
;;BOOT_X_RES equ 0x900A ;word X res
;;BOOT_Y_RES equ 0x900C ;word Y res
;;BOOT_MOUSE_PORT equ 0x9010 ;byte mouse port - not used
BOOT_BANK_SW equ 0x9014 ;dword Vesa 1.2 pm bank switch
;BOOT_BANK_SW equ 0x9014 ;dword Vesa 1.2 pm bank switch
BOOT_LFB equ 0x9018 ;dword Vesa 2.0 LFB address
BOOT_MTRR equ 0x901C ;byte 0 or 1 : enable MTRR graphics acceleration
BOOT_LOG equ 0x901D ;byte not used anymore (0 or 1 : enable system log display)
BOOT_DIRECT_LFB equ 0x901E ;byte 0 or 1 : enable direct lfb write, paging disabled
BOOT_PCI_DATA equ 0x9020 ;8bytes pci data
BOOT_VRR equ 0x9030 ;byte VRR start enabled 1, 2-no
;BOOT_VRR equ 0x9030 ;byte VRR start enabled 1, 2-no
BOOT_IDE_BASE_ADDR equ 0x9031 ;word IDEContrRegsBaseAddr
BOOT_MEM_AMOUNT equ 0x9034 ;dword memory amount

4
kernel/branches/Kolibri-A/trunk/init.inc
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@ -54,8 +54,8 @@ preinit_mem:
rep stosd
; clear <sys_pgdir> table
mov edi, sys_pgdir-OS_BASE
mov ecx, 4096/4
mov edi, mmio_pte
mov ecx, 2048 ; 8k (sys_pgdir included)
rep stosd
ret

9
kernel/branches/Kolibri-A/trunk/kernel.asm
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@ -216,15 +216,8 @@ diff16 "32-bit code start ",0,$
; PCIe extended config space access
display '** Platform chosen (const.inc): '
if PLATFORM>PLATFORM_RS780
call fusion_pcie_init ; (bus/HT.inc)
display 'RS880/Fusion '
else
call rs7xx_pcie_init ; (bus/HT.inc)
display 'RS780 '
end if
display 10,13
; MEMORY MODEL