diff --git a/programs/system/drivers/agp/agp.c b/programs/system/drivers/agp/agp.c new file mode 100644 index 0000000000..152b5e5942 --- /dev/null +++ b/programs/system/drivers/agp/agp.c @@ -0,0 +1,318 @@ + +#include "types.h" + +#include +#include +#include + +#include "pci.h" +#include "agp.h" + +#include "syscall.h" + + +agp_t agp_dev; + + +int __stdcall srv_agp(ioctl_t *io); + + +u32_t __stdcall drvEntry(int action) +{ + u32_t retval; + + int i; + + if(action != 1) + return 0; + + if(!dbg_open("/rd/1/drivers/agp.log")) + { + printf("Can't open /rd/1/drivers/agp.log\nExit\n"); + return 0; + } + + if( FindPciDevice() == 0) + { + dbgprintf("Device not found\n"); + return 0; + }; + + return 0; + +// retval = RegService("AGP", srv_2d); +// dbgprintf("reg service %s as: %x\n", "HDRAW", retval); + +// return retval; +}; + + +static void intel_8xx_tlbflush(void *mem) +{ + u32_t temp; + + temp = pciReadLong(agp_dev.PciTag, INTEL_AGPCTRL); + pciWriteLong(agp_dev.PciTag, INTEL_AGPCTRL, temp & ~(1 << 7)); + temp = pciReadLong(agp_dev.PciTag, INTEL_AGPCTRL); + pciWriteLong(agp_dev.PciTag, INTEL_AGPCTRL, temp | (1 << 7)); +} + + +static aper_size_t intel_8xx_sizes[7] = +{ + { 256, 65536, 64, 0 }, + { 128, 32768, 32, 32 }, + { 64, 16384, 16, 48 }, + { 32, 8192, 8, 56 }, + { 16, 4096, 4, 60 }, + { 8, 2048, 2, 62 }, + { 4, 1024, 1, 63 } +}; + +#if 0 +static int agp_backend_initialize(struct agp_bridge_data *bridge) +{ + int size_value, rc, got_gatt=0, got_keylist=0; + + bridge->max_memory_agp = agp_find_max(); + bridge->version = &agp_current_version; + + if (bridge->driver->needs_scratch_page) { + void *addr = bridge->driver->agp_alloc_page(bridge); + + if (!addr) { + printk(KERN_ERR PFX "unable to get memory for scratch page.\n"); + return -ENOMEM; + } + flush_agp_mappings(); + + bridge->scratch_page_real = virt_to_gart(addr); + bridge->scratch_page = + bridge->driver->mask_memory(bridge, bridge->scratch_page_real, 0); + } + + size_value = bridge->driver->fetch_size(); + if (size_value == 0) { + printk(KERN_ERR PFX "unable to determine aperture size.\n"); + rc = -EINVAL; + goto err_out; + } + if (bridge->driver->create_gatt_table(bridge)) { + printk(KERN_ERR PFX + "unable to get memory for graphics translation table.\n"); + rc = -ENOMEM; + goto err_out; + } + got_gatt = 1; + + bridge->key_list = vmalloc(PAGE_SIZE * 4); + if (bridge->key_list == NULL) { + printk(KERN_ERR PFX "error allocating memory for key lists.\n"); + rc = -ENOMEM; + goto err_out; + } + got_keylist = 1; + + /* FIXME vmalloc'd memory not guaranteed contiguous */ + memset(bridge->key_list, 0, PAGE_SIZE * 4); + + if (bridge->driver->configure()) { + printk(KERN_ERR PFX "error configuring host chipset.\n"); + rc = -EINVAL; + goto err_out; + } + + return 0; + +err_out: + if (bridge->driver->needs_scratch_page) { + bridge->driver->agp_destroy_page( + gart_to_virt(bridge->scratch_page_real)); + flush_agp_mappings(); + } + if (got_gatt) + bridge->driver->free_gatt_table(bridge); + if (got_keylist) { + vfree(bridge->key_list); + bridge->key_list = NULL; + } + return rc; +} + + +#endif + + +static int intel_845_configure(void *bridge) +{ + u32_t temp; + u8_t temp2; + aper_size_t *current_size; + + agp_t *agp = (agp_t*)bridge; + + current_size = agp->current_size; + + /* aperture size */ + pciWriteByte(agp->PciTag, INTEL_APSIZE, current_size->size_value); + + dbgprintf("INTEL_APSIZE %d\n", current_size->size_value ); + + if (agp->apbase_config != 0) + { + pciWriteLong(agp->PciTag, AGP_APBASE, agp->apbase_config); + } + else + { + /* address to map to */ + temp = pciReadLong(agp->PciTag, AGP_APBASE); + agp->gart_addr = (temp & PCI_MAP_MEMORY_ADDRESS_MASK); + agp->apbase_config = temp; + } + + dbgprintf("AGP_APBASE %x\n", temp ); + + /* attbase - aperture base */ + pciWriteLong(agp->PciTag, INTEL_ATTBASE, agp->gatt_dma); + + /* agpctrl */ + pciWriteLong(agp->PciTag, INTEL_AGPCTRL, 0x0000); + + /* agpm */ + temp2 = pciReadByte(agp->PciTag, INTEL_I845_AGPM); + pciWriteByte(agp->PciTag, INTEL_I845_AGPM, temp2 | (1 << 1)); + /* clear any possible error conditions */ + pciWriteWord(agp->PciTag, INTEL_I845_ERRSTS, 0x001c); + return 0; +} + + +int agp_generic_create_gatt_table(agp_t *bridge) +{ + count_t pages; + + pages = bridge->current_size->pages_count; + + bridge->gatt_dma = AllocPages(pages); + + bridge->gatt_table = (u32_t*)MapIoMem((void*)bridge->gatt_dma, + pages<<12, PG_SW+PG_NOCACHE); + + dbgprintf("gatt map %x at %x %d pages\n",bridge->gatt_dma , + bridge->gatt_table, pages); + + if (bridge->gatt_table == NULL) + return -30;//ENOMEM; + + /* AK: bogus, should encode addresses > 4GB */ +// for (i = 0; i < num_entries; i++) { +// writel(bridge->scratch_page, bridge->gatt_table+i); +// readl(bridge->gatt_table+i); /* PCI Posting. */ +// } + + return 0; +} + + + +static int __intel_8xx_fetch_size(u8_t temp) +{ + int i; + aper_size_t *values; + + // values = A_SIZE_8(agp_bridge->driver->aperture_sizes); + + values = intel_8xx_sizes; + + for (i = 0; i < 7; i++) + { + if (temp == values[i].size_value) + { + agp_dev.previous_size = + agp_dev.current_size = (void *) (values + i); + agp_dev.aperture_size_idx = i; + return values[i].size; + } + } + return 0; +} + +static int intel_8xx_fetch_size(void) +{ + u8_t temp; + + temp = pciReadByte(agp_dev.PciTag, INTEL_APSIZE); + return __intel_8xx_fetch_size(temp); +} + + +int agp_bind_memory(addr_t agp_addr, addr_t dma_addr, size_t size) +{ + int ret_val; + count_t count; + +// if (curr == NULL) +// return -EINVAL; + +// if (curr->is_bound == TRUE) { +// printk(KERN_INFO PFX "memory %p is already bound!\n", curr); +// return -EINVAL; +// } +// if (curr->is_flushed == FALSE) { +// curr->bridge->driver->cache_flush(); +// curr->is_flushed = TRUE; +// } +// ret_val = curr->bridge->driver->insert_memory(curr, pg_start, curr->type); + + u32_t volatile *table = &agp_dev.gatt_table[agp_addr>>12]; + + count = size >> 12; + + dma_addr |= 0x00000017; + + while(count--) + { + addr_t tmp; + + *table = dma_addr; + tmp = *table; /* PCI Posting. */ + table++; + dma_addr+=4096; + } + + agp_dev.tlb_flush(NULL); + +// if (ret_val != 0) +// return ret_val; + +// curr->is_bound = TRUE; +// curr->pg_start = pg_start; + return 0; +} + + +static agp_t intel_845_driver = +{ +// .aperture_sizes = intel_8xx_sizes, +// .size_type = U8_APER_SIZE, +// .num_aperture_sizes = 7, + .configure = intel_845_configure, + .fetch_size = intel_8xx_fetch_size, +// .cleanup = intel_8xx_cleanup, + .tlb_flush = intel_8xx_tlbflush, +// .mask_memory = agp_generic_mask_memory, +// .masks = intel_generic_masks, +// .agp_enable = agp_generic_enable, +// .cache_flush = global_cache_flush, +// .create_gatt_table = agp_generic_create_gatt_table, +// .free_gatt_table = agp_generic_free_gatt_table, +// .insert_memory = agp_generic_insert_memory, +// .remove_memory = agp_generic_remove_memory, +// .alloc_by_type = agp_generic_alloc_by_type, +// .free_by_type = agp_generic_free_by_type, +// .agp_alloc_page = agp_generic_alloc_page, +// .agp_destroy_page = agp_generic_destroy_page, +}; + + +#include "detect.inc" diff --git a/programs/system/drivers/agp/agp.h b/programs/system/drivers/agp/agp.h new file mode 100644 index 0000000000..b6e834ea50 --- /dev/null +++ b/programs/system/drivers/agp/agp.h @@ -0,0 +1,61 @@ + +/* Intel registers */ +#define INTEL_APSIZE 0xb4 +#define INTEL_ATTBASE 0xb8 +#define INTEL_AGPCTRL 0xb0 +#define INTEL_NBXCFG 0x50 +#define INTEL_ERRSTS 0x91 + +/* Intel i845 registers */ +#define INTEL_I845_AGPM 0x51 +#define INTEL_I845_ERRSTS 0xc8 + +/* Chipset independant registers (from AGP Spec) */ +#define AGP_APBASE 0x10 + +typedef struct +{ + size_t size; + count_t num_entries; + count_t pages_count; + u32_t size_value; +}aper_size_t; + +typedef struct +{ + PCITAG PciTag; + + aper_size_t *previous_size; + aper_size_t *current_size; + int aperture_size_idx; + + u32_t volatile *gatt_table; + addr_t gatt_dma; + + addr_t apbase_config; + addr_t gart_addr; + +// void *aperture_sizes; +// int num_aperture_sizes; +// enum aper_size_type size_type; +// int cant_use_aperture; +// int needs_scratch_page; +// struct gatt_mask *masks; + int (*fetch_size)(void *); + int (*configure)(void *); +// void (*agp_enable)(struct agp_bridge_data *, u32); +// void (*cleanup)(void); + void (*tlb_flush)(void *); +// u32_t (*mask_memory)(struct agp_bridge_data *,u32_t, int); +// void (*cache_flush)(void); +// int (*create_gatt_table)(struct agp_bridge_data *); +// int (*free_gatt_table)(struct agp_bridge_data *); +// int (*insert_memory)(struct agp_memory *, off_t, int); +// int (*remove_memory)(struct agp_memory *, off_t, int); +// struct agp_memory *(*alloc_by_type) (size_t, int); +// void (*free_by_type)(struct agp_memory *); +// void *(*agp_alloc_page)(struct agp_bridge_data *); +// void (*agp_destroy_page)(void *); +}agp_t; + + diff --git a/programs/system/drivers/agp/agp.lk b/programs/system/drivers/agp/agp.lk new file mode 100644 index 0000000000..f05f03a416 --- /dev/null +++ b/programs/system/drivers/agp/agp.lk @@ -0,0 +1,26 @@ +IMP + _KernelAlloc core.KernelAlloc, + _KernelFree core.KernelFree, + _UserAlloc core.UserAlloc, + _UserFree core.UserFree, + _CommitPages core.CommitPages, + _AllocPages core.AllocPages, + _UnmapPages core.UnmapPages, + _CreateObject core.CreateObject, + _DestroyObject core.DestroyObject, + _MapIoMem core.MapIoMem, + _GetPgAddr core.GetPgAddr, + _CreateRingBuffer core.CreateRingBuffer, + _PciApi core.PciApi, + _PciRead8 core.PciRead8, + _PciRead32 core.PciRead32, + _PciWrite8 core.PciWrite8, + _PciWrite16 core.PciWrite16, + _PciWrite32 core.PciWrite32, + _RegService core.RegService, + _SysMsgBoardStr core.SysMsgBoardStr + + +FIL agp.obj, + vsprintf.obj, + icompute.obj diff --git a/programs/system/drivers/agp/detect.inc b/programs/system/drivers/agp/detect.inc new file mode 100644 index 0000000000..ebcc90484e --- /dev/null +++ b/programs/system/drivers/agp/detect.inc @@ -0,0 +1,117 @@ + +#define PCI_CLASS_BRIDGE_HOST 0x06 + +#define INTEL_82443LX_0 (0x7180<<16)|0x8086 +#define INTEL_82443BX_0 (0x7190<<16)|0x8086 +#define INTEL_82443GX_0 (0x71a0<<16)|0x8086 +#define INTEL_82810_MC1 (0x7120<<16)|0x8086 +#define INTEL_82810_MC3 (0x7122<<16)|0x8086 +#define INTEL_82810E_MC (0x7124<<16)|0x8086 +#define INTEL_82815_MC (0x1130<<16)|0x8086 +#define INTEL_82820_HB (0x2500<<16)|0x8086 +#define INTEL_82820_UP_HB (0x2501<<16)|0x8086 +#define INTEL_82830_HB (0x3575<<16)|0x8086 +#define INTEL_82840_HB (0x1a21<<16)|0x8086 +#define INTEL_82845_HB (0x1a30<<16)|0x8086 +#define INTEL_82845G_HB (0x2560<<16)|0x8086 +#define INTEL_82850_HB (0x2530<<16)|0x8086 +#define INTEL_82855PM_HB (0x3340<<16)|0x8086 +#define INTEL_82855GM_HB (0x3580<<16)|0x8086 +#define INTEL_82860_HB (0x2531<<16)|0x8086 +#define INTEL_82865_HB (0x2570<<16)|0x8086 +#define INTEL_82875_HB (0x2578<<16)|0x8086 +#define INTEL_7505_0 (0x2550<<16)|0x8086 +#define INTEL_7205_0 (0x255d<<16)|0x8086 +#define INTEL_82915G_HB (0x2580<<16)|0x8086 +#define INTEL_82915GM_HB (0x2590<<16)|0x8086 +#define INTEL_82945G_HB (0x2770<<16)|0x8086 +#define INTEL_82945GM_HB (0x27A0<<16)|0x8086 + + +typedef struct +{ + int id; + int driver; +}pci_device_t; + + +static pci_device_t agp_dev_table[] = { + +// { INTEL_82443LX_0, 0 }, +// { INTEL_82443BX_0, 0 }, +// { INTEL_82443GX_0, 0 }, +// { INTEL_82810_MC1, 0 }, +// { INTEL_82810_MC3, 0 }, +// { INTEL_82810E_MC, 0 }, +// { INTEL_82815_MC, 0 }, +// { INTEL_82820_HB, 0 }, +// { INTEL_82820_UP_HB,0 }, +// { INTEL_82830_HB, 0 }, +// { INTEL_82840_HB, 0 }, +// { INTEL_82845_HB, 0 }, +// { INTEL_82845G_HB, 0 }, +// { INTEL_82850_HB, 0 }, +// { INTEL_82855PM_HB, 0 }, +// { INTEL_82855GM_HB, 0 }, +// { INTEL_82860_HB, 0 }, + { INTEL_82865_HB, 0 }, +// { INTEL_82875_HB, 0 }, +// { INTEL_7505_0, 0 }, +// { INTEL_7205_0, 0 }, +// { INTEL_82915G_HB, 0 }, +// { INTEL_82915GM_HB, 0 }, +// { INTEL_82945G_HB, 0 }, +// { INTEL_82945GM_HB, 0 }, + { 0, 0 } +}; + +pci_device_t* agp_dev_match(u32_t dev, pci_device_t *list) +{ + while(list->id) + { + if(dev == list->id) + return list; + list++; + } + return NULL; +} + +int FindPciDevice() +{ + u32_t bus, last_bus; + PCITAG tag; + + if( (last_bus = PciApi(1))==-1) + return 0; + + for(bus=0;bus<=last_bus;bus++) + { + u32_t devfn; + + for(devfn=0;devfn<256;devfn++) + { + u32_t pciId; + u8_t devclass; + pci_device_t *dev; + + pciId = PciRead32(bus,devfn, 0); + devclass = PciRead8(bus,devfn, 0x0B); + + if( devclass != PCI_CLASS_BRIDGE_HOST) + continue; + + if( (dev = agp_dev_match(pciId, agp_dev_table))!=NULL) + { + dbgprintf("detect agp host %x\n",dev->id); + agp_dev.PciTag = pciTag(bus,(devfn>>3)&0x1F,devfn&0x7); + dbgprintf("fetch size = %x\n", intel_8xx_fetch_size()); + agp_generic_create_gatt_table(&agp_dev); + intel_845_configure(&agp_dev); + return 1; + }; + + + }; + }; + return 0; +}; diff --git a/programs/system/drivers/agp/makefile b/programs/system/drivers/agp/makefile new file mode 100644 index 0000000000..709ba2003b --- /dev/null +++ b/programs/system/drivers/agp/makefile @@ -0,0 +1,27 @@ + +CC = gcc +FASM = e:/fasm/fasm.exe +CFLAGS = -c -O2 -fomit-frame-pointer -fno-builtin-printf +LDRHD = -shared -T ld.x -s --file-alignment 32 + +HFILES:= syscall.h \ + pci.h \ + +SRC_DEP:= detect.inc + +AGP_SRC:= agp.c + + +AGP = agp.dll + +all: $(AGP) + +$(AGP): agp.obj $(SRC_DEP) $(HFILES) Makefile + wlink name agp.dll SYS nt_dll lib libdrv op offset=0 op nod op maxe=25 op el op STUB=stub.exe op START=_drvEntry @agp.lk + kpack.exe agp.dll agp.drv + +agp.obj : agp.c $(SRC_DEP) $(HFILES) Makefile + $(CC) $(CFLAGS) -o agp.obj agp.c + + + diff --git a/programs/system/drivers/agp/pci.h b/programs/system/drivers/agp/pci.h new file mode 100644 index 0000000000..ef2556470c --- /dev/null +++ b/programs/system/drivers/agp/pci.h @@ -0,0 +1,79 @@ + + +#pragma pack(push, 1) +typedef struct +{ + u16_t device; + u16_t ChipSet; +}PciChipset_t; +#pragma pack(pop) + +#define VENDOR_ATI 0x1002 + + +#define PCI_MAP_REG_START 0x10 +#define PCI_MAP_REG_END 0x28 +#define PCI_MAP_ROM_REG 0x30 + +#define PCI_MAP_MEMORY 0x00000000 +#define PCI_MAP_IO 0x00000001 + +#define PCI_MAP_MEMORY_TYPE 0x00000007 +#define PCI_MAP_IO_TYPE 0x00000003 + +#define PCI_MAP_MEMORY_TYPE_32BIT 0x00000000 +#define PCI_MAP_MEMORY_TYPE_32BIT_1M 0x00000002 +#define PCI_MAP_MEMORY_TYPE_64BIT 0x00000004 +#define PCI_MAP_MEMORY_TYPE_MASK 0x00000006 +#define PCI_MAP_MEMORY_CACHABLE 0x00000008 +#define PCI_MAP_MEMORY_ATTR_MASK 0x0000000e +#define PCI_MAP_MEMORY_ADDRESS_MASK 0xfffffff0 + +#define PCI_MAP_IO_ATTR_MASK 0x00000003 + +#define PCI_MAP_IS_IO(b) ((b) & PCI_MAP_IO) +#define PCI_MAP_IS_MEM(b) (!PCI_MAP_IS_IO(b)) + +#define PCI_MAP_IS64BITMEM(b) \ + (((b) & PCI_MAP_MEMORY_TYPE_MASK) == PCI_MAP_MEMORY_TYPE_64BIT) + +#define PCIGETMEMORY(b) ((b) & PCI_MAP_MEMORY_ADDRESS_MASK) +#define PCIGETMEMORY64HIGH(b) (*((CARD32*)&b + 1)) +#define PCIGETMEMORY64(b) \ + (PCIGETMEMORY(b) | ((CARD64)PCIGETMEMORY64HIGH(b) << 32)) + +#define PCI_MAP_IO_ADDRESS_MASK 0xfffffffc + +#define PCIGETIO(b) ((b) & PCI_MAP_IO_ADDRESS_MASK) + +#define PCI_MAP_ROM_DECODE_ENABLE 0x00000001 +#define PCI_MAP_ROM_ADDRESS_MASK 0xfffff800 + +#define PCIGETROM(b) ((b) & PCI_MAP_ROM_ADDRESS_MASK) + + +#ifndef PCI_DOM_MASK +# define PCI_DOM_MASK 0x0ffu +#endif +#define PCI_DOMBUS_MASK (((PCI_DOM_MASK) << 8) | 0x0ffu) + +#define PCI_MAKE_TAG(b,d,f) ((((b) & (PCI_DOMBUS_MASK)) << 16) | \ + (((d) & 0x00001fu) << 11) | \ + (((f) & 0x000007u) << 8)) + +#define PCI_BUS_FROM_TAG(tag) (((tag) >> 16) & (PCI_DOMBUS_MASK)) +#define PCI_DEV_FROM_TAG(tag) (((tag) & 0x0000f800u) >> 11) +#define PCI_FUNC_FROM_TAG(tag) (((tag) & 0x00000700u) >> 8) +#define PCI_DFN_FROM_TAG(tag) (((tag) & 0x0000ff00u) >> 8) + + +typedef unsigned int PCITAG; + +extern inline PCITAG +pciTag(int busnum, int devnum, int funcnum) +{ + return(PCI_MAKE_TAG(busnum,devnum,funcnum)); +} + +const PciChipset_t *PciDevMatch(u16_t dev,const PciChipset_t *list); +u32_t pciGetBaseSize(int bus, int devfn, int index, Bool destructive, Bool *min); diff --git a/programs/system/drivers/agp/syscall.h b/programs/system/drivers/agp/syscall.h new file mode 100644 index 0000000000..a389666966 --- /dev/null +++ b/programs/system/drivers/agp/syscall.h @@ -0,0 +1,254 @@ + +#define OS_BASE 0x80000000 + +typedef struct +{ + u32_t handle; + u32_t io_code; + void *input; + int inp_size; + void *output; + int out_size; +}ioctl_t; + +typedef int (__stdcall *srv_proc_t)(ioctl_t *); + +#define ERR_OK 0 +#define ERR_PARAM -1 + + +u32_t __stdcall drvEntry(int)__asm__("_drvEntry"); + +/////////////////////////////////////////////////////////////////////////////// + +#define STDCALL __attribute__ ((stdcall)) __attribute__ ((dllimport)) +#define IMPORT __attribute__ ((dllimport)) + +/////////////////////////////////////////////////////////////////////////////// + +#define SysMsgBoardStr __SysMsgBoardStr +#define PciApi __PciApi +//#define RegService __RegService +#define CreateObject __CreateObject +#define DestroyObject __DestroyObject + +/////////////////////////////////////////////////////////////////////////////// + +#define PG_SW 0x003 +#define PG_NOCACHE 0x018 + +void* STDCALL AllocKernelSpace(size_t size)__asm__("AllocKernelSpace"); +void* STDCALL KernelAlloc(size_t size)__asm__("KernelAlloc"); +void* STDCALL KernelFree(void *mem)__asm__("KernelFree"); +void* STDCALL UserAlloc(size_t size)__asm__("UserAlloc"); +int STDCALL UserFree(void *mem)__asm__("UserFree"); + +addr_t STDCALL AllocPages(count_t count)__asm__("AllocPages"); + +void* STDCALL CreateRingBuffer(size_t size, u32_t map)__asm__("CreateRingBuffer"); + +u32_t STDCALL RegService(char *name, srv_proc_t proc)__asm__("RegService"); + +//void *CreateObject(u32 pid, size_t size); +//void *DestroyObject(void *obj); + +addr_t STDCALL MapIoMem(void* base,size_t size,u32_t flags)__asm__("MapIoMem"); + +/////////////////////////////////////////////////////////////////////////////// + + +static u32_t PciApi(int cmd); + +u8_t STDCALL PciRead8 (u32_t bus, u32_t devfn, u32_t reg)__asm__("PciRead8"); +u16_t STDCALL PciRead16(u32_t bus, u32_t devfn, u32_t reg)__asm__("PciRead16"); +u32_t STDCALL PciRead32(u32_t bus, u32_t devfn, u32_t reg)__asm__("PciRead32"); + +#define pciReadLong(tag, reg) \ + PciRead32(PCI_BUS_FROM_TAG(tag),PCI_DFN_FROM_TAG(tag),(reg)) + +#define pciReadByte(tag, reg) \ + PciRead8(PCI_BUS_FROM_TAG(tag),PCI_DFN_FROM_TAG(tag),(reg)) + +u32_t STDCALL PciWrite8 (u32_t bus, u32_t devfn, u32_t reg,u8_t val) __asm__("PciWrite8"); +u32_t STDCALL PciWrite16(u32_t bus, u32_t devfn, u32_t reg,u16_t val)__asm__("PciWrite16"); +u32_t STDCALL PciWrite32(u32_t bus, u32_t devfn, u32_t reg,u32_t val)__asm__("PciWrite32"); + +#define pciWriteByte(tag, reg, val) \ + PciWrite8(PCI_BUS_FROM_TAG(tag),PCI_DFN_FROM_TAG(tag),(reg),(val)) + +#define pciWriteWord(tag, reg, val) \ + PciWrite16(PCI_BUS_FROM_TAG(tag),PCI_DFN_FROM_TAG(tag),(reg),(val)) + +#define pciWriteLong(tag, reg, val) \ + PciWrite32(PCI_BUS_FROM_TAG(tag),PCI_DFN_FROM_TAG(tag),(reg),(val)) + + +/////////////////////////////////////////////////////////////////////////////// + +int dbg_open(char *path); +int dbgprintf(const char* format, ...); + +/////////////////////////////////////////////////////////////////////////////// + +extern inline int GetScreenSize() +{ + int retval; + + asm("int $0x40" + :"=a"(retval) + :"a"(61), "b"(1)); + return retval; +} + +extern inline int GetScreenBpp() +{ + int retval; + + asm("int $0x40" + :"=a"(retval) + :"a"(61), "b"(2)); + return retval; +} + +extern inline int GetScreenPitch() +{ + int retval; + + asm("int $0x40" + :"=a"(retval) + :"a"(61), "b"(3)); + return retval; +} + +extern inline u32_t GetPgAddr(void *mem) +{ + u32_t retval; + + __asm__ __volatile__ ( + "call *__imp__GetPgAddr \n\t" + :"=eax" (retval) + :"a" (mem) ); + return retval; +}; + +extern inline void CommitPages(void *mem, u32_t page, u32_t size) +{ + size = (size+4095) & ~4095; + __asm__ __volatile__ ( + "call *__imp__CommitPages" + ::"a" (page), "b"(mem),"c"(size>>12) + :"edx" ); + __asm__ __volatile__ ("":::"eax","ebx","ecx"); +}; + +extern inline void UnmapPages(void *mem, size_t size) +{ + size = (size+4095) & ~4095; + __asm__ __volatile__ ( + "call *__imp__UnmapPages" + ::"a" (mem), "c"(size>>12) + :"edx"); + __asm__ __volatile__ ("":::"eax","ecx"); +}; + +extern inline void usleep(u32_t delay) +{ + if( !delay ) + delay++; + delay*=2000; + + __asm__ __volatile__ ( + "1:\n\t" + "xorl %%eax, %%eax \n\t" + "cpuid \n\t" + "decl %%edi \n\t" + "jnz 1b" + : + :"D"(delay) + :"eax","ebx","ecx","edx"); +}; + +extern inline u32_t __PciApi(int cmd) +{ + u32_t retval; + + __asm__ __volatile__ ( + "call *__imp__PciApi" + :"=a" (retval) + :"a" (cmd) + :"memory"); + return retval; +}; + +extern inline void* __CreateObject(u32_t pid, size_t size) +{ + void *retval; + + __asm__ __volatile__ ( + "call *__imp__CreateObject \n\t" + :"=a" (retval) + :"a" (size),"b"(pid) + :"esi","edi", "memory"); + return retval; +} + +extern inline void *__DestroyObject(void *obj) +{ + __asm__ __volatile__ ( + "call *__imp__DestroyObject" + : + :"a" (obj) + :"ebx","edx","esi","edi", "memory"); +} + + +/* +u32 __RegService(char *name, srv_proc_t proc) +{ + u32 retval; + + asm __volatile__ + ( + "pushl %%eax \n\t" + "pushl %%ebx \n\t" + "call *__imp__RegService \n\t" + :"=eax" (retval) + :"a" (proc), "b" (name) + :"memory" + ); + return retval; +}; +*/ + +extern inline u32_t safe_cli(void) +{ + u32_t ifl; + __asm__ __volatile__ ( + "pushf\n\t" + "popl %0\n\t" + "cli\n" + : "=r" (ifl)); + return ifl; +} + +extern inline void safe_sti(u32_t ifl) +{ + __asm__ __volatile__ ( + "pushl %0\n\t" + "popf\n" + : : "r" (ifl) + ); +} + +extern inline void __clear (void * dst, unsigned len) +{ + u32_t tmp; + __asm__ __volatile__ ( +// "xorl %%eax, %%eax \n\t" + "cld \n\t" + "rep stosb \n" + :"=c"(tmp),"=D"(tmp) + :"a"(0),"c"(len),"D"(dst)); + __asm__ __volatile__ ("":::"ecx","edi"); +}; + diff --git a/programs/system/drivers/agp/types.h b/programs/system/drivers/agp/types.h new file mode 100644 index 0000000000..cef0bba8a3 --- /dev/null +++ b/programs/system/drivers/agp/types.h @@ -0,0 +1,21 @@ + +#define NULL (void*)0 + + +typedef unsigned char u8_t; +typedef unsigned short int u16_t; +typedef unsigned int u32_t; +typedef unsigned long long u64_t; + +typedef unsigned int addr_t; + +typedef unsigned int size_t; +typedef unsigned int count_t; +typedef unsigned int eflags_t; + +typedef unsigned int Bool; + +#define TRUE (Bool)1 +#define FALSE (Bool)0 + +