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blit from system memory in PIO mode

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git-svn-id: svn://kolibrios.org@1002 a494cfbc-eb01-0410-851d-a64ba20cac60
This commit is contained in:
Sergey Semyonov (Serge) 2009-01-27 00:31:09 +00:00
parent 76bc83bd66
commit 80c71dc52a
18 changed files with 986 additions and 706 deletions
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4
programs/develop/libraries/pixlib/clip.inc
View File

@ -170,11 +170,11 @@ int blit_clip(clip_t *dst_clip,int *dst_x,int *dst_y,
*src_y += dy0 - *dst_y;
*dst_x = dx0;
*dst_y = dx0;
*dst_y = dy0;
return 0;
};
};
}
return 1;
};

117
programs/develop/libraries/pixlib/draw.inc
View File

@ -564,14 +564,13 @@ int Blit(pixmap_t *dst_pixmap, int dst_x, int dst_y,
return ERR_PARAM;
/* if "hardware acceleration present" and
"destinastion is primary screen or local videomemory" and
"source is primary screen or local videomemory"
"destinastion is primary screen or local videomemory"
*/
if( (srv_hw2d != 0) &&
( (dst_pixmap == (void*)-1) ||
( (dst_pixmap->flags & PX_MEM_MASK)==PX_MEM_LOCAL) ) &&
( (dst_pixmap->flags & PX_MEM_MASK)==PX_MEM_LOCAL) ) /* &&
( (src_pixmap == (void*)-1) ||
( (src_pixmap->flags & PX_MEM_MASK)==PX_MEM_LOCAL) ) )
( (src_pixmap->flags & PX_MEM_MASK)==PX_MEM_LOCAL) ) */ )
{
ioctl_t io;
pxblit_t *blit = (pxblit_t*)&dst_pixmap;
@ -579,7 +578,8 @@ int Blit(pixmap_t *dst_pixmap, int dst_x, int dst_y,
if((int)dst_pixmap != -1)
blit->dst_pixmap = (pixmap_t*)dst_pixmap->handle;
if((int)src_pixmap != -1)
if( (int)src_pixmap != -1 &&
(src_pixmap->flags & PX_MEM_MASK) != PX_MEM_SYSTEM)
blit->src_pixmap = (pixmap_t*)src_pixmap->handle;
io.handle = srv_hw2d;
@ -705,6 +705,9 @@ int TransparentBlit(pixmap_t *dst_pixmap, int dst_x, int dst_y,
return call_service(&io);
};
dst_pixmap = (dst_pixmap == (void*)-1) ? &scrn_pixmap : dst_pixmap ;
src_pixmap = (src_pixmap == (void*)-1) ? &scrn_pixmap : src_pixmap ;
src_clip.xmin = 0;
src_clip.ymin = 0;
src_clip.xmax = src_pixmap->width-1;
@ -722,8 +725,6 @@ int TransparentBlit(pixmap_t *dst_pixmap, int dst_x, int dst_y,
{
__m64 clr_key;
dst_pixmap = (dst_pixmap == (void*)-1) ? &scrn_pixmap : dst_pixmap ;
src_pixmap = (src_pixmap == (void*)-1) ? &scrn_pixmap : src_pixmap ;
color_t *src_addr = &((color_t*)(src_pixmap->mapped))[src_pixmap->pitch*src_y/4+src_x];
color_t *dst_addr = &((color_t*)(dst_pixmap->mapped))[dst_pixmap->pitch*dst_y/4+dst_x];
@ -766,4 +767,106 @@ int TransparentBlit(pixmap_t *dst_pixmap, int dst_x, int dst_y,
return ERR_OK;
}
unsigned long long m_0080 = 0x0080008000800080ULL;
int BlitAlpha(pixmap_t *dst_pixmap, int dst_x, int dst_y,
pixmap_t *src_pixmap, int src_x, int src_y,
int width, int height, u32_t alpha)
{
clip_t src_clip, dst_clip;
if( (srv_hw2d != 0) &&
( (dst_pixmap == (void*)-1) ||
( (dst_pixmap->flags & PX_MEM_MASK)==PX_MEM_LOCAL) ) &&
( (src_pixmap == (void*)-1) ||
( (src_pixmap->flags & PX_MEM_MASK)==PX_MEM_LOCAL) ) )
{
ioctl_t io;
pxblit_t *blit = (pxblit_t*)&dst_pixmap;
if((int)dst_pixmap != -1)
blit->dst_pixmap = (pixmap_t*)dst_pixmap->handle;
if((int)src_pixmap != -1)
blit->src_pixmap = (pixmap_t*)src_pixmap->handle;
io.handle = srv_hw2d;
io.io_code = PX_BLIT_ALPHA;
io.input = blit;
io.inp_size = 9;
io.output = NULL;
io.out_size = 0;
return call_service(&io);
};
dst_pixmap = (dst_pixmap == (void*)-1) ? &scrn_pixmap : dst_pixmap ;
src_pixmap = (src_pixmap == (void*)-1) ? &scrn_pixmap : src_pixmap ;
src_clip.xmin = 0;
src_clip.ymin = 0;
src_clip.xmax = src_pixmap->width-1;
src_clip.ymax = src_pixmap->height-1;
dst_clip.xmin = 0;
dst_clip.ymin = 0;
dst_clip.xmax = dst_pixmap->width-1;
dst_clip.ymax = dst_pixmap->height-1;
if( !blit_clip(&dst_clip, &dst_x, &dst_y,
&src_clip, &src_x, &src_y,
&width, &height) )
{
__m64 m_alpha;
__m64 m_one_alpha;
color_t *src_addr = &((color_t*)(src_pixmap->mapped))[src_pixmap->pitch*src_y/4+src_x];
color_t *dst_addr = &((color_t*)(dst_pixmap->mapped))[dst_pixmap->pitch*dst_y/4+dst_x];
m_alpha = _mm_cvtsi32_si64((alpha << 16) | alpha);
m_alpha = _mm_unpacklo_pi32(m_alpha, m_alpha);
m_one_alpha = _mm_subs_pu16((__m64)0x00FF00FF00FF00FFULL, m_alpha);
while( height-- )
{
int w = width;
color_t *tmp_src = src_addr;
color_t *tmp_dst = dst_addr;
src_addr += src_pixmap->pitch/4;
dst_addr += dst_pixmap->pitch/4;
while( w-- )
{
__asm__ __volatile__ (
"movd (%0), %%mm0 \n\t"
"pxor %%mm1, %%mm1 \n\t"
"punpcklbw %%mm1, %%mm0 \n\t"
"pmullw %[clr_key], %%mm0 \n\t"
// "paddw %[m_0080], %%mm0 \n\t"
"movd (%1), %%mm2 \n\t"
"punpcklbw %%mm1, %%mm2 \n\t"
"pmullw %[m_one_alpha], %%mm2 \n\t"
// "paddw %[m_0080], %%mm2 \n\t"
"paddw %%mm2, %%mm0 \n\t"
"psrlw $8, %%mm0 \n\t"
"packuswb %%mm0, %%mm0 \n\t"
"movd %%mm0, (%1)"
:: "r" (tmp_src),
"r" (tmp_dst),
[clr_key] "y" (m_alpha),
[m_one_alpha] "y" (m_one_alpha)
:"memory","mm0", "mm1", "mm2");
tmp_src++;
tmp_dst++;
};
// if( w && (*tmp_src != alpha) )
// *tmp_dst = *tmp_src;
};
};
return ERR_OK;
}

8
programs/develop/libraries/pixlib/pixlib.c
View File

@ -1,4 +1,6 @@
//#define KOLIBRI_PE
#include "types.h"
#include "system.h"
@ -64,9 +66,9 @@ int __stdcall start(int state)
scrn_pixmap.width = scrnsize >> 16;
scrn_pixmap.height = scrnsize & 0xFFFF;
scrn_pixmap.format = PICT_a8r8g8b8;
scrn_pixmap.flags = 0;
scrn_pixmap.flags = PX_MEM_LOCAL;
scrn_pixmap.pitch = scrnpitch;
scrn_pixmap.mapped = (void*)0xFE000000;
scrn_pixmap.mapped = (void*)LFB_BASE;
br_slab.available = 256;
br_slab.start = brushes;
@ -129,6 +131,7 @@ char szDrawRect[] = "DrawRect";
char szFillRect[] = "FillRect";
char szBlit[] = "Blit";
char szTransparentBlit[] = "TransparentBlit";
char szBlitAlpha[] = "BlitAlpha";
export_t EXPORTS[] __asm__("EXPORTS") =
@ -155,6 +158,7 @@ export_t EXPORTS[] __asm__("EXPORTS") =
{ szFillRect, FillRect },
{ szBlit, Blit },
{ szTransparentBlit, TransparentBlit },
{ szBlitAlpha, BlitAlpha },
{ NULL, NULL },
};

1
programs/develop/libraries/pixlib/pixlib.h
View File

@ -151,6 +151,7 @@ typedef struct
int src_y;
int w;
int h;
color_t key;
}pxblit_t;
#define PX_CREATE 1

65
programs/develop/libraries/pixlib/pixlib.inc
View File

@ -126,6 +126,21 @@ macro Blit dstpix, dstx, dsty, srcpix, srcx, srcy, w, h
add esp, 8*4
}
macro BlitAlpha dstpix, dstx, dsty, srcpix, srcx, srcy, w, h, alpha
{
pushd alpha
pushd h
pushd w
pushd srcy
pushd srcx
pushd srcpix
pushd dsty
pushd dstx
pushd dstpix
call [imp_BlitAlpha]
add esp, 9*4
}
macro TransparentBlit dstpix, dstx, dsty, srcpix, srcx, srcy, w, h, key
{
pushd key
@ -141,6 +156,25 @@ macro TransparentBlit dstpix, dstx, dsty, srcpix, srcx, srcy, w, h, key
add esp, 9*4
}
macro fix_cwd path
{
pushd path
push '/'
push path
call _strrchr
mov byte [eax], 0
mov eax, 30
mov ebx, 1
mov ecx, [esp+8]
int 0x40
add esp, 12
}
szPxlib db '/rd/1/lib/pixlib.obj',0
szStart db 'START',0
@ -162,6 +196,7 @@ szDrawRect db 'DrawRect',0
szFillRect db 'FillRect',0
szBlit db 'Blit',0
szTransparentBlit db 'TransparentBlit',0
szBlitAlpha db 'BlitAlpha',0
align 4
@ -186,6 +221,7 @@ imp_DrawRect dd szDrawRect
imp_FillRect dd szFillRect
imp_Blit dd szBlit
imp_TransparentBlit dd szTransparentBlit
imp_BlitAlpha dd szBlitAlpha
dd 0
@ -257,4 +293,31 @@ load_pxlib:
xor eax, eax
ret
align 4
_strrchr:
push ebp
mov ebp, esp
push edi
mov edi, [8+ebp]
mov ecx, -1
xor al, al
cld
repne
scasb
not ecx
dec edi
mov al, [12+ebp]
std
repne
scasb
cld
jne .failure
lea eax, [edi+1]
pop edi
pop ebp
ret
.failure:
xor eax, eax
pop edi
pop ebp
ret

6
programs/develop/libraries/pixlib/pixmap.inc
View File

@ -55,8 +55,7 @@ pixmap_t* CreatePixmap(unsigned width, unsigned height, u32_t format, u32_t flag
if (call_service(&io)==ERR_OK)
return pixmap;
else
{
else{
free_pixmap(pixmap) ;
return NULL;
}
@ -71,8 +70,7 @@ pixmap_t* CreatePixmap(unsigned width, unsigned height, u32_t format, u32_t flag
pitch = ((width+8)&~8)*4;
raw = UserAlloc(pitch * height);
if (! raw)
{
if ( !raw ){
free_pixmap(pixmap);
return NULL;
};

6
programs/develop/libraries/pixlib/system.h
View File

@ -18,6 +18,12 @@ typedef struct
///////////////////////////////////////////////////////////////////////////////
#ifdef KOLIBRI_PE
#define LFB_BASE 0xDF000000
#else
#define LFB_BASE 0xFE000000
#endif
void usleep(u32_t delay);

6
programs/system/drivers/ati2d/accel_2d.h
View File

@ -64,6 +64,12 @@ typedef struct
void *local;
}local_pixmap_t;
#define PX_MEM_SYSTEM 0
#define PX_MEM_LOCAL 1
#define PX_MEM_GART 2
#define PX_MEM_MASK 3
#define PX_LOCK 1

97
programs/system/drivers/ati2d/accel_2d.inc
View File

@ -567,6 +567,95 @@ int FillRect(io_fill_t *fill)
};
#define ADDRREG(addr) ((volatile u32_t *)(rhd.MMIOBase + (addr)))
static int blit_host(u32_t dstpitch, int dstx, int dsty,
u32_t src, int srcx, int srcy,
int w, int h, int srcpitch)
{
u32_t ifl;
color_t *src_addr;
ifl = safe_cli();
#if R300_PIO
R5xxFIFOWait(5);
OUTREG(R5XX_DP_GUI_MASTER_CNTL,
RADEON_GMC_DST_PITCH_OFFSET_CNTL |
// RADEON_GMC_DST_CLIPPING |
RADEON_GMC_BRUSH_NONE |
RADEON_GMC_DST_32BPP |
RADEON_GMC_SRC_DATATYPE_COLOR |
RADEON_DP_SRC_SOURCE_HOST_DATA |
// RADEON_GMC_BYTE_MSB_TO_LSB |
R5XX_GMC_CLR_CMP_CNTL_DIS |
R5XX_GMC_WR_MSK_DIS |
R5XX_ROP3_S
);
OUTREG(R5XX_DP_CNTL, R5XX_DST_X_LEFT_TO_RIGHT |
R5XX_DST_Y_TOP_TO_BOTTOM);
OUTREG(R5XX_DST_PITCH_OFFSET, dstpitch);
// OUTREG(RADEON_SC_TOP_LEFT, (y << 16) | ((x+skipleft) & 0xffff));
// OUTREG(RADEON_SC_BOTTOM_RIGHT, ((y+h) << 16) | ((x+w) & 0xffff));
OUTREG(RADEON_DST_Y_X, (dsty << 16) | (dstx & 0xffff));
OUTREG(RADEON_DST_HEIGHT_WIDTH, (h << 16) | w);
src_addr = &((color_t*)src)[srcpitch*srcy/4+srcx];
while ( h-- )
{
color_t *tmp_src = src_addr;
src_addr += srcpitch/4;
int left = w;
while( left )
{
volatile u32_t *d;
if( left > 8 )
{
int i;
R5xxFIFOWait(8);
d = ADDRREG(RADEON_HOST_DATA0);
/* Unrolling doesn't improve performance */
for ( i = 0; i < 8; i++)
*d++ = *tmp_src++;
left -= 8;
}
else
{
R5xxFIFOWait(left);
if( h )
d = ADDRREG(RADEON_HOST_DATA7) - (left - 1);
else
d = ADDRREG(RADEON_HOST_DATA_LAST) - (left - 1);
for ( ; left; --left)
*d++ = *tmp_src++;
left = 0;
};
};
};
#endif
safe_sti(ifl);
return ERR_OK;
}
int Blit(io_blit_t *blit)
{
@ -604,6 +693,14 @@ int Blit(io_blit_t *blit)
u32_t *ring, write;
u32_t ifl;
if( (srcpixmap->flags & PX_MEM_MASK)==PX_MEM_SYSTEM)
return blit_host(dstpixmap->pitch_offset,
blit->dst_x, blit->dst_y,
srcpixmap->mapped,
blit->src_x, blit->src_y,
blit->w, blit->h,
srcpixmap->pitch);
ifl = safe_cli();
#if R300_PIO

15
programs/system/drivers/ati2d/ati2d.c
View File

@ -1,6 +1,11 @@
#define R300_PIO 0 /* now we have cp */
#define R300_PIO 1
#define API_VERSION 0x01000100
#define SRV_GETVERSION 0
#include "types.h"
@ -72,8 +77,11 @@ u32_t __stdcall drvEntry(int action)
R5xx2DInit();
#if !R300_PIO
Init3DEngine(&rhd);
#endif
retval = RegService("HDRAW", srv_2d);
dbgprintf("reg service %s as: %x\n", "HDRAW", retval);
@ -82,11 +90,6 @@ u32_t __stdcall drvEntry(int action)
};
#define API_VERSION 0x01000100
#define SRV_GETVERSION 0
int __stdcall srv_2d(ioctl_t *io)
{
u32_t *inp;

4
programs/system/drivers/ati2d/ati_mem.c
View File

@ -39,7 +39,8 @@
* already mapped into each client's address space.
*/
struct mem_block {
struct mem_block
{
struct mem_block *next;
struct mem_block *prev;
u32_t start;
@ -114,7 +115,6 @@ static struct mem_block *alloc_block(struct mem_block *heap, int size)
list_for_each(p, heap)
{
if ( !(p->start & USED_BLOCK) && size <= p->size)
return split_block(p, size);
}

118
programs/system/drivers/ati2d/init.c
View File

@ -448,7 +448,6 @@ static void RADEONUpdateMemMapRegisters(RHDPtr info)
#endif
static void RADEONInitMemoryMap(RHDPtr info)
{
u32_t mem_size;
@ -484,7 +483,8 @@ static void RADEONInitMemoryMap(RHDPtr info)
if ( (info->ChipFamily != CHIP_FAMILY_RS600) &&
(info->ChipFamily != CHIP_FAMILY_RS690) &&
(info->ChipFamily != CHIP_FAMILY_RS740)) {
(info->ChipFamily != CHIP_FAMILY_RS740))
{
if (info->IsIGP)
info->mc_fb_location = INREG(RADEON_NB_TOM);
else
@ -995,12 +995,124 @@ Bool RHDPreInit()
info = &rhd;
return TRUE;
error1:
return FALSE;
};
static void RADEONPllErrataAfterIndex()
{
if (!(rhd.ChipErrata & CHIP_ERRATA_PLL_DUMMYREADS))
return;
/* This workaround is necessary on rv200 and RS200 or PLL
* reads may return garbage (among others...)
*/
(void)INREG(RADEON_CLOCK_CNTL_DATA);
(void)INREG(RADEON_CRTC_GEN_CNTL);
}
static void RADEONPllErrataAfterData()
{
/* This function is required to workaround a hardware bug in some (all?)
* revisions of the R300. This workaround should be called after every
* CLOCK_CNTL_INDEX register access. If not, register reads afterward
* may not be correct.
*/
if (rhd.ChipFamily <= CHIP_FAMILY_RV380)
{
u32_t save, tmp;
save = INREG(RADEON_CLOCK_CNTL_INDEX);
tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
OUTREG(RADEON_CLOCK_CNTL_INDEX, tmp);
tmp = INREG(RADEON_CLOCK_CNTL_DATA);
OUTREG(RADEON_CLOCK_CNTL_INDEX, save);
}
}
/* Read PLL register */
static u32_t RADEONINPLL(int addr)
{
u32_t data;
OUTREG8(RADEON_CLOCK_CNTL_INDEX, addr & 0x3f);
RADEONPllErrataAfterIndex();
data = INREG(RADEON_CLOCK_CNTL_DATA);
RADEONPllErrataAfterData();
return data;
};
/* Write PLL information */
static void RADEONOUTPLL(int addr, u32_t data)
{
OUTREG8(RADEON_CLOCK_CNTL_INDEX, (((addr) & 0x3f) |
RADEON_PLL_WR_EN));
RADEONPllErrataAfterIndex();
OUTREG(RADEON_CLOCK_CNTL_DATA, data);
RADEONPllErrataAfterData();
}
static void init_pipes(RHDPtr info)
{
u32_t gb_tile_config = 0;
if ( (info->ChipFamily == CHIP_FAMILY_RV410) ||
(info->ChipFamily == CHIP_FAMILY_R420) ||
(info->ChipFamily == CHIP_FAMILY_RS600) ||
(info->ChipFamily == CHIP_FAMILY_RS690) ||
(info->ChipFamily == CHIP_FAMILY_RS740) ||
(info->ChipFamily == CHIP_FAMILY_RS400) ||
(info->ChipFamily == CHIP_FAMILY_RS480) || IS_R500_3D)
{
u32_t gb_pipe_sel = INREG(R400_GB_PIPE_SELECT);
info->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
if (IS_R500_3D)
OUTPLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
}
else
{
if ((info->ChipFamily == CHIP_FAMILY_R300) ||
(info->ChipFamily == CHIP_FAMILY_R350))
{
/* R3xx chips */
info->num_gb_pipes = 2;
}
else {
/* RV3xx chips */
info->num_gb_pipes = 1;
}
}
if (IS_R300_3D || IS_R500_3D)
{
dbgprintf("num quad-pipes is %d\n", info->num_gb_pipes);
switch(info->num_gb_pipes) {
case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
default:
case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
}
OUTREG(R300_GB_TILE_CONFIG, gb_tile_config);
OUTREG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
OUTREG(R300_DST_PIPE_CONFIG, INREG(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
OUTREG(R300_RB2D_DSTCACHE_MODE, (INREG(R300_RB2D_DSTCACHE_MODE) |
R300_DC_AUTOFLUSH_ENABLE |
R300_DC_DC_DISABLE_IGNORE_PE));
}
else
OUTREG(RADEON_RB3D_CNTL, 0);
};

1
programs/system/drivers/ati2d/init_3d.inc
View File

@ -635,7 +635,6 @@ int Init3DEngine(RHDPtr info)
FINISH_ACCEL();
}
safe_sti(ifl);
}

114
programs/system/drivers/ati2d/init_cp.c
View File

@ -20,65 +20,9 @@
#define RADEON_IDLE_RETRY 16 /* Fall out of idle loops after this count */
#define RADEON_TIMEOUT 2000000 /* Fall out of wait loops after this count */
#define RADEON_TIMEOUT 4000000 /* Fall out of wait loops after this count */
void RADEONPllErrataAfterIndex()
{
if (!(rhd.ChipErrata & CHIP_ERRATA_PLL_DUMMYREADS))
return;
/* This workaround is necessary on rv200 and RS200 or PLL
* reads may return garbage (among others...)
*/
(void)INREG(RADEON_CLOCK_CNTL_DATA);
(void)INREG(RADEON_CRTC_GEN_CNTL);
}
void RADEONPllErrataAfterData()
{
/* This function is required to workaround a hardware bug in some (all?)
* revisions of the R300. This workaround should be called after every
* CLOCK_CNTL_INDEX register access. If not, register reads afterward
* may not be correct.
*/
if (rhd.ChipFamily <= CHIP_FAMILY_RV380)
{
u32_t save, tmp;
save = INREG(RADEON_CLOCK_CNTL_INDEX);
tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
OUTREG(RADEON_CLOCK_CNTL_INDEX, tmp);
tmp = INREG(RADEON_CLOCK_CNTL_DATA);
OUTREG(RADEON_CLOCK_CNTL_INDEX, save);
}
}
/* Read PLL register */
u32_t RADEONINPLL(int addr)
{
u32_t data;
OUTREG8(RADEON_CLOCK_CNTL_INDEX, addr & 0x3f);
RADEONPllErrataAfterIndex();
data = INREG(RADEON_CLOCK_CNTL_DATA);
RADEONPllErrataAfterData();
return data;
};
/* Write PLL information */
void RADEONOUTPLL(int addr, u32_t data)
{
OUTREG8(RADEON_CLOCK_CNTL_INDEX, (((addr) & 0x3f) |
RADEON_PLL_WR_EN));
RADEONPllErrataAfterIndex();
OUTREG(RADEON_CLOCK_CNTL_DATA, data);
RADEONPllErrataAfterData();
}
void RADEONEngineFlush(RHDPtr info)
{
@ -148,61 +92,6 @@ static int radeon_do_wait_for_idle()
}
static void init_pipes(RHDPtr info)
{
u32_t gb_tile_config = 0;
if ( (info->ChipFamily == CHIP_FAMILY_RV410) ||
(info->ChipFamily == CHIP_FAMILY_R420) ||
(info->ChipFamily == CHIP_FAMILY_RS600) ||
(info->ChipFamily == CHIP_FAMILY_RS690) ||
(info->ChipFamily == CHIP_FAMILY_RS740) ||
(info->ChipFamily == CHIP_FAMILY_RS400) ||
(info->ChipFamily == CHIP_FAMILY_RS480) || IS_R500_3D)
{
u32_t gb_pipe_sel = INREG(R400_GB_PIPE_SELECT);
info->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
if (IS_R500_3D)
OUTPLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
}
else
{
if ((info->ChipFamily == CHIP_FAMILY_R300) ||
(info->ChipFamily == CHIP_FAMILY_R350))
{
/* R3xx chips */
info->num_gb_pipes = 2;
}
else {
/* RV3xx chips */
info->num_gb_pipes = 1;
}
}
if (IS_R300_3D || IS_R500_3D)
{
dbgprintf("num quad-pipes is %d\n", info->num_gb_pipes);
switch(info->num_gb_pipes) {
case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
default:
case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
}
OUTREG(R300_GB_TILE_CONFIG, gb_tile_config);
OUTREG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
OUTREG(R300_DST_PIPE_CONFIG, INREG(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
OUTREG(R300_RB2D_DSTCACHE_MODE, (INREG(R300_RB2D_DSTCACHE_MODE) |
R300_DC_AUTOFLUSH_ENABLE |
R300_DC_DC_DISABLE_IGNORE_PE));
}
else
OUTREG(RADEON_RB3D_CNTL, 0);
};
/* ================================================================
* CP control, initialization
@ -501,6 +390,7 @@ Bool init_cp(RHDPtr info)
radeon_cp_start(&rhd);
return TRUE;
};

3
programs/system/drivers/ati2d/makefile
View File

@ -22,8 +22,7 @@ SRC_DEP:= init.c \
blend.inc \
r500.inc \
pixmap.inc \
accel_2d.inc \
accel_3d.inc
accel_2d.inc
ATI_SRC:= ati2d.c

14
programs/system/drivers/ati2d/pci.c
View File

@ -60,12 +60,12 @@ RHDPtr FindPciDevice()
int i;
rhd.chipset = (char*)xf86TokenToString(RADEONChipsets, rhd.PciDeviceID);
if (!rhd.chipset)
{
if (!rhd.chipset){
dbgprintf("ChipID 0x%04x is not recognized\n", rhd.PciDeviceID);
return FALSE;
}
dbgprintf("Chipset: \"%s\" (ChipID = 0x%04x)\n",rhd.chipset,rhd.PciDeviceID);
dbgprintf("Chipset: \"%s\" (ChipID = 0x%04x)\n",
rhd.chipset,rhd.PciDeviceID);
rhd.bus = bus;
rhd.devfn = devfn;
@ -93,13 +93,11 @@ RHDPtr FindPciDevice()
base = PciRead32(bus,devfn, PCI_MAP_REG_START + (i << 2));
if(base)
{
if (base & PCI_MAP_IO)
{
if (base & PCI_MAP_IO){
rhd.ioBase[i] = (u32_t)PCIGETIO(base);
rhd.memtype[i] = base & PCI_MAP_IO_ATTR_MASK;
}
else
{
else{
rhd.memBase[i] = (u32_t)PCIGETMEMORY(base);
rhd.memtype[i] = base & PCI_MAP_MEMORY_ATTR_MASK;
}
@ -108,7 +106,7 @@ RHDPtr FindPciDevice()
}
return &rhd;
}
};
}
};
return NULL;
}

2
programs/system/drivers/ati2d/pixmap.inc
View File

@ -50,7 +50,7 @@ int CreatePixmap(pixmap_t *io)
pixmap->width = io->width;
pixmap->height = io->height;
pixmap->format = PICT_a8r8g8b8;
pixmap->flags = io->flags;
pixmap->flags = PX_MEM_LOCAL; //io->flags;
pixmap->pitch = pitch;
pixmap->mapped = mapped;
pixmap->pitch_offset = ((pitch/64)<<22)| (((u32_t)local+rhd.fbLocation)>>10);

7
programs/system/drivers/ati2d/r500.inc
View File

@ -71,7 +71,6 @@ R5xx2DIdleLocal() //R100-R500
}
dbgprintf("%s: Idle Timeout 0x%08X.\n", __func__,INREG(R5XX_RBBM_STATUS));
return FALSE;
}
@ -174,6 +173,7 @@ void R5xx2DInit()
scr_pixmap.width = rhd.displayWidth;
scr_pixmap.height = rhd.displayHeight;
scr_pixmap.format = PICT_a8r8g8b8;
scr_pixmap.flags = PX_MEM_LOCAL;
scr_pixmap.pitch = rhd.displayWidth * 4 ;//screenpitch;
scr_pixmap.local = (void*)rhd.fbLocation;
scr_pixmap.pitch_offset = rhd.dst_pitch_offset;
@ -188,9 +188,10 @@ void R5xx2DInit()
OUTREG(R5XX_SURFACE_CNTL, rhd.surface_cntl);
#if R300_PIO
#else
#if !R300_PIO
init_cp(&rhd);
#endif
R5xx2DSetup();