added pci.inc for drivers, removed redundant code from netdrv.inc

git-svn-id: svn://kolibrios.org@2886 a494cfbc-eb01-0410-851d-a64ba20cac60
This commit is contained in:
hidnplayr 2012-07-22 19:47:29 +00:00
parent 2a2f8aee7f
commit 8a10e28dfe
2 changed files with 199 additions and 152 deletions

View File

@ -0,0 +1,124 @@
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; ;;
;; Copyright (C) KolibriOS team 2004-2012. All rights reserved. ;;
;; Distributed under terms of the GNU General Public License ;;
;; ;;
;; GNU GENERAL PUBLIC LICENSE ;;
;; Version 2, June 1991 ;;
;; ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; PCI Bus defines
PCI_HEADER_TYPE = 0x0e ; 8 bit
PCI_BASE_ADDRESS_0 = 0x10 ; 32 bit
PCI_BASE_ADDRESS_5 = 0x24 ; 32 bits
PCI_BASE_ADDRESS_SPACE_IO = 0x01
PCI_VENDOR_ID = 0x00 ; 16 bit
PCI_BASE_ADDRESS_IO_MASK = 0xFFFFFFFC
; PCI programming
PCI_REG_COMMAND = 0x4 ; command register
PCI_REG_STATUS = 0x6 ; status register
PCI_REG_LATENCY = 0xd ; latency timer register
PCI_REG_CAP_PTR = 0x34 ; capabilities pointer
PCI_REG_CAPABILITY_ID = 0x0 ; capapility ID in pm register block
PCI_REG_PM_STATUS = 0x4 ; power management status register
PCI_REG_PM_CTRL = 0x4 ; power management control register
PCI_BIT_PIO = 1 ; bit0: io space control
PCI_BIT_MMIO = 2 ; bit1: memory space control
PCI_BIT_MASTER = 4 ; bit2: device acts as a PCI master
macro find_io bus, dev, io {
local .check, .inc, .got
xor eax, eax
mov esi, PCI_BASE_ADDRESS_0
movzx ecx, bus
movzx edx, dev
.check:
stdcall PciRead32, ecx ,edx ,esi
test eax, PCI_BASE_ADDRESS_IO_MASK
jz .inc
test eax, PCI_BASE_ADDRESS_SPACE_IO
jz .inc
and eax, PCI_BASE_ADDRESS_IO_MASK
mov io , eax
jmp .got
.inc:
add esi, 4
cmp esi, PCI_BASE_ADDRESS_5
jle .check
.got:
}
macro find_mmio32 bus, dev, mmio32 {
local .check, .got
xor eax, eax
mov esi, PCI_BASE_ADDRESS_0
movzx ecx, bus
movzx edx, dev
.check:
stdcall PciRead32, ecx ,edx ,esi
test eax, not PCI_BASE_ADDRESS_IO_MASK
jz .got
add esi, 4
cmp esi, PCI_BASE_ADDRESS_5
jle .check
xor eax, eax
.got:
mov mmio32, eax
}
macro find_irq bus, dev, irq {
push eax edx ecx
movzx ecx, bus
movzx edx, dev
stdcall PciRead8, ecx ,edx ,0x3c ; 0x3c is the offset where irq can be found
mov irq, al
pop ecx edx eax
}
macro find_rev bus, dev, rev {
push eax edx ecx
movzx ecx, bus
movzx edx, dev
stdcall PciRead8, ecx ,edx ,0x8
mov rev, al
pop ecx edx eax
}
macro make_bus_master bus, dev {
movzx ecx, bus
movzx edx, dev
stdcall PciRead32, ecx ,edx, PCI_REG_COMMAND
or al, PCI_BIT_MASTER ;or PCI_BIT_PIO
; and al, not PCI_BIT_MMIO
stdcall PciWrite32, ecx, edx, PCI_REG_COMMAND, eax
;; TODO: try to switch to PIO, and check if PIO works or not..
}

View File

@ -1,24 +1,14 @@
; PCI Bus defines ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
PCI_HEADER_TYPE equ 0x0e ;8 bit ;; ;;
PCI_BASE_ADDRESS_0 equ 0x10 ;32 bit ;; Copyright (C) KolibriOS team 2004-2012. All rights reserved. ;;
PCI_BASE_ADDRESS_5 equ 0x24 ;32 bits ;; Distributed under terms of the GNU General Public License ;;
PCI_BASE_ADDRESS_SPACE_IO equ 0x01 ;; ;;
PCI_VENDOR_ID equ 0x00 ;16 bit ;; GNU GENERAL PUBLIC LICENSE ;;
PCI_BASE_ADDRESS_IO_MASK equ 0xFFFFFFFC ;; Version 2, June 1991 ;;
;; ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; PCI programming
PCI_REG_COMMAND equ 0x4 ; command register
PCI_REG_STATUS equ 0x6 ; status register
PCI_REG_LATENCY equ 0xd ; latency timer register
PCI_REG_CAP_PTR equ 0x34 ; capabilities pointer
PCI_REG_CAPABILITY_ID equ 0x0 ; capapility ID in pm register block
PCI_REG_PM_STATUS equ 0x4 ; power management status register
PCI_REG_PM_CTRL equ 0x4 ; power management control register
PCI_BIT_PIO equ 1 ; bit0: io space control
PCI_BIT_MMIO equ 2 ; bit1: memory space control
PCI_BIT_MASTER equ 4 ; bit2: device acts as a PCI master
include 'bus/pci.inc'
; Kernel variables ; Kernel variables
@ -32,7 +22,6 @@
NET_TYPE_SLIP equ 2 NET_TYPE_SLIP equ 2
LAST_IO = 0 LAST_IO = 0
macro set_io addr { macro set_io addr {
@ -79,72 +68,6 @@ macro allocate_and_clear dest, size, err {
} }
macro find_io bus, dev, io {
local .check, .inc, .got
xor eax, eax
mov esi, PCI_BASE_ADDRESS_0
movzx ecx, bus
movzx edx, dev
.check:
stdcall PciRead32, ecx ,edx ,esi
test eax, PCI_BASE_ADDRESS_IO_MASK
jz .inc
test eax, PCI_BASE_ADDRESS_SPACE_IO
jz .inc
and eax, PCI_BASE_ADDRESS_IO_MASK
mov io , eax
jmp .got
.inc:
add esi, 4
cmp esi, PCI_BASE_ADDRESS_5
jle .check
.got:
}
macro find_irq bus, dev, irq {
push eax edx ecx
movzx ecx, bus
movzx edx, dev
stdcall PciRead8, ecx ,edx ,0x3c ; 0x3c is the offset where irq can be found
mov irq, al
pop ecx edx eax
}
macro find_rev bus, dev, rev {
push eax edx ecx
movzx ecx, bus
movzx edx, dev
stdcall PciRead8, ecx ,edx ,0x8
mov rev, al
pop ecx edx eax
}
macro make_bus_master bus, dev {
movzx ecx, bus
movzx edx, dev
stdcall PciRead32, ecx ,edx, PCI_REG_COMMAND
or al, PCI_BIT_MASTER ;or PCI_BIT_PIO
; and al, not PCI_BIT_MMIO
stdcall PciWrite32, ecx, edx, PCI_REG_COMMAND, eax
;; TODO: try to switch to PIO, and check if PIO works or not..
}
struc IOCTL { struc IOCTL {
.handle dd ? .handle dd ?
.io_code dd ? .io_code dd ?