forked from KolibriOS/kolibrios
3c59x: enable RX/TX after enabling interrupts, not before.
git-svn-id: svn://kolibrios.org@3349 a494cfbc-eb01-0410-851d-a64ba20cac60
This commit is contained in:
hidnplayr
parent
2c13dbe1c3
commit
e4513c6c12
@ -82,16 +82,16 @@
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format MS COFF
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format MS COFF
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API_VERSION = 0x01000100
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API_VERSION = 0x01000100
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DRIVER_VERSION = 5
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DRIVER_VERSION = 5
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MAX_DEVICES = 16
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MAX_DEVICES = 16
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FORCE_FD = 0 ; forcing full duplex mode makes sense at some cards and link types
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FORCE_FD = 0 ; forcing full duplex mode makes sense at some cards and link types
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PROMISCIOUS = 0 ; enables promiscous mode
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PROMISCIOUS = 0 ; enables promiscous mode
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DEBUG = 1
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DEBUG = 1
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__DEBUG__ = 1
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__DEBUG__ = 1
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__DEBUG_LEVEL__ = 1
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__DEBUG_LEVEL__ = 1
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include 'proc32.inc'
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include 'proc32.inc'
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include 'imports.inc'
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include 'imports.inc'
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@ -104,12 +104,12 @@ public version
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struc DPD { ; Download Packet Descriptor
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struc DPD { ; Download Packet Descriptor
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.next_ptr dd ?
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.next_ptr dd ?
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.frame_start_hdr dd ?
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.frame_start_hdr dd ?
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.frag_addr dd ? ; for packet data
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.frag_addr dd ? ; for packet data
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.frag_len dd ? ; for packet data
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.frag_len dd ? ; for packet data
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.realaddr dd ?
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.realaddr dd ?
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.size = 32
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.size = 32
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}
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}
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virtual at 0
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virtual at 0
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@ -119,11 +119,11 @@ end virtual
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struc UPD { ; Upload Packet Descriptor
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struc UPD { ; Upload Packet Descriptor
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.next_ptr dd ?
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.next_ptr dd ?
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.pkt_status dd ?
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.pkt_status dd ?
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.frag_addr dd ?
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.frag_addr dd ?
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.frag_len dd ? ; for packet data
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.frag_len dd ? ; for packet data
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.realaddr dd ?
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.realaddr dd ?
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.size = 32
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.size = 32
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}
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}
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@ -133,202 +133,202 @@ virtual at 0
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end virtual
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end virtual
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; Registers
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; Registers
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REG_POWER_MGMT_CTRL = 0x7c
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REG_POWER_MGMT_CTRL = 0x7c
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REG_UP_LIST_PTR = 0x38
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REG_UP_LIST_PTR = 0x38
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REG_UP_PKT_STATUS = 0x30
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REG_UP_PKT_STATUS = 0x30
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REG_TX_FREE_THRESH = 0x2f
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REG_TX_FREE_THRESH = 0x2f
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REG_DN_LIST_PTR = 0x24
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REG_DN_LIST_PTR = 0x24
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REG_DMA_CTRL = 0x20
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REG_DMA_CTRL = 0x20
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REG_TX_STATUS = 0x1b
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REG_TX_STATUS = 0x1b
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REG_RX_STATUS = 0x18
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REG_RX_STATUS = 0x18
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REG_TX_DATA = 0x10
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REG_TX_DATA = 0x10
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; Common window registers
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; Common window registers
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REG_INT_STATUS = 0xe
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REG_INT_STATUS = 0xe
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REG_COMMAND = 0xe
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REG_COMMAND = 0xe
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; Register window 7
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; Register window 7
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REG_MASTER_STATUS = 0xc
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REG_MASTER_STATUS = 0xc
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REG_POWER_MGMT_EVENT = 0xc
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REG_POWER_MGMT_EVENT = 0xc
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REG_MASTER_LEN = 0x6
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REG_MASTER_LEN = 0x6
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REG_VLAN_ETHER_TYPE = 0x4
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REG_VLAN_ETHER_TYPE = 0x4
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REG_VLAN_MASK = 0x0
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REG_VLAN_MASK = 0x0
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REG_MASTER_ADDRESS = 0x0
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REG_MASTER_ADDRESS = 0x0
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; Register window 6
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; Register window 6
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REG_BYTES_XMITTED_OK = 0xc
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REG_BYTES_XMITTED_OK = 0xc
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REG_BYTES_RCVD_OK = 0xa
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REG_BYTES_RCVD_OK = 0xa
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REG_UPPER_FRAMES_OK = 0x9
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REG_UPPER_FRAMES_OK = 0x9
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REG_FRAMES_DEFERRED = 0x8
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REG_FRAMES_DEFERRED = 0x8
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REG_FRAMES_RCVD_OK = 0x7
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REG_FRAMES_RCVD_OK = 0x7
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REG_FRAMES_XMITTED_OK = 0x6
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REG_FRAMES_XMITTED_OK = 0x6
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REG_RX_OVERRUNS = 0x5
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REG_RX_OVERRUNS = 0x5
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REG_LATE_COLLISIONS = 0x4
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REG_LATE_COLLISIONS = 0x4
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REG_SINGLE_COLLISIONS = 0x3
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REG_SINGLE_COLLISIONS = 0x3
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REG_MULTIPLE_COLLISIONS = 0x2
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REG_MULTIPLE_COLLISIONS = 0x2
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REG_SQE_ERRORS = 0x1
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REG_SQE_ERRORS = 0x1
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REG_CARRIER_LOST = 0x0
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REG_CARRIER_LOST = 0x0
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; Register window 5
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; Register window 5
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REG_INDICATION_ENABLE = 0xc
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REG_INDICATION_ENABLE = 0xc
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REG_INTERRUPT_ENABLE = 0xa
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REG_INTERRUPT_ENABLE = 0xa
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REG_TX_RECLAIM_THRESH = 0x9
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REG_TX_RECLAIM_THRESH = 0x9
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REG_RX_FILTER = 0x8
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REG_RX_FILTER = 0x8
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REG_RX_EARLY_THRESH = 0x6
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REG_RX_EARLY_THRESH = 0x6
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REG_TX_START_THRESH = 0x0
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REG_TX_START_THRESH = 0x0
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; Register window 4
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; Register window 4
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REG_UPPER_BYTES_OK = 0xe
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REG_UPPER_BYTES_OK = 0xe
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REG_BAD_SSD = 0xc
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REG_BAD_SSD = 0xc
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REG_MEDIA_STATUS = 0xa
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REG_MEDIA_STATUS = 0xa
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REG_PHYSICAL_MGMT = 0x8
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REG_PHYSICAL_MGMT = 0x8
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REG_NETWORK_DIAGNOSTIC = 0x6
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REG_NETWORK_DIAGNOSTIC = 0x6
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REG_FIFO_DIAGNOSTIC = 0x4
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REG_FIFO_DIAGNOSTIC = 0x4
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REG_VCO_DIAGNOSTIC = 0x2 ; may not supported
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REG_VCO_DIAGNOSTIC = 0x2 ; may not supported
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; Bits in register window 4
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; Bits in register window 4
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BIT_AUTOSELECT = 24
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BIT_AUTOSELECT = 24
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; Register window 3
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; Register window 3
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REG_TX_FREE = 0xc
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REG_TX_FREE = 0xc
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REG_RX_FREE = 0xa
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REG_RX_FREE = 0xa
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REG_MEDIA_OPTIONS = 0x8
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REG_MEDIA_OPTIONS = 0x8
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REG_MAC_CONTROL = 0x6
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REG_MAC_CONTROL = 0x6
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REG_MAX_PKT_SIZE = 0x4
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REG_MAX_PKT_SIZE = 0x4
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REG_INTERNAL_CONFIG = 0x0
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REG_INTERNAL_CONFIG = 0x0
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; Register window 2
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; Register window 2
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REG_RESET_OPTIONS = 0xc
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REG_RESET_OPTIONS = 0xc
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REG_STATION_MASK_HI = 0xa
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REG_STATION_MASK_HI = 0xa
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REG_STATION_MASK_MID = 0x8
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REG_STATION_MASK_MID = 0x8
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REG_STATION_MASK_LO = 0x6
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REG_STATION_MASK_LO = 0x6
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REG_STATION_ADDRESS_HI = 0x4
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REG_STATION_ADDRESS_HI = 0x4
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REG_STATION_ADDRESS_MID = 0x2
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REG_STATION_ADDRESS_MID = 0x2
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REG_STATION_ADDRESS_LO = 0x0
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REG_STATION_ADDRESS_LO = 0x0
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; Register window 1
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; Register window 1
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REG_TRIGGER_BITS = 0xc
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REG_TRIGGER_BITS = 0xc
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REG_SOS_BITS = 0xa
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REG_SOS_BITS = 0xa
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REG_WAKE_ON_TIMER = 0x8
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REG_WAKE_ON_TIMER = 0x8
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REG_SMB_RXBYTES = 0x7
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REG_SMB_RXBYTES = 0x7
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REG_SMB_DIAG = 0x5
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REG_SMB_DIAG = 0x5
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REG_SMB_ARB = 0x4
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REG_SMB_ARB = 0x4
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REG_SMB_STATUS = 0x2
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REG_SMB_STATUS = 0x2
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REG_SMB_ADDRESS = 0x1
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REG_SMB_ADDRESS = 0x1
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REG_SMB_FIFO_DATA = 0x0
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REG_SMB_FIFO_DATA = 0x0
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; Register window 0
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; Register window 0
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REG_EEPROM_DATA = 0xc
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REG_EEPROM_DATA = 0xc
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REG_EEPROM_COMMAND = 0xa
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REG_EEPROM_COMMAND = 0xa
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REG_BIOS_ROM_DATA = 0x8
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REG_BIOS_ROM_DATA = 0x8
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REG_BIOS_ROM_ADDR = 0x4
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REG_BIOS_ROM_ADDR = 0x4
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; Physical management bits
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; Physical management bits
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BIT_MGMT_DIR = 2 ; drive with the data written in mgmtData
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BIT_MGMT_DIR = 2 ; drive with the data written in mgmtData
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BIT_MGMT_DATA = 1 ; MII management data bit
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BIT_MGMT_DATA = 1 ; MII management data bit
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BIT_MGMT_CLK = 0 ; MII management clock
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BIT_MGMT_CLK = 0 ; MII management clock
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; MII commands
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; MII commands
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MII_CMD_MASK = (1111b shl 10)
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MII_CMD_MASK = (1111b shl 10)
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MII_CMD_READ = (0110b shl 10)
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MII_CMD_READ = (0110b shl 10)
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MII_CMD_WRITE = (0101b shl 10)
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MII_CMD_WRITE = (0101b shl 10)
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; MII registers
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; MII registers
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REG_MII_BMCR = 0 ; basic mode control register
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REG_MII_BMCR = 0 ; basic mode control register
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REG_MII_BMSR = 1 ; basic mode status register
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REG_MII_BMSR = 1 ; basic mode status register
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REG_MII_ANAR = 4 ; auto negotiation advertisement register
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REG_MII_ANAR = 4 ; auto negotiation advertisement register
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REG_MII_ANLPAR = 5 ; auto negotiation link partner ability register
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REG_MII_ANLPAR = 5 ; auto negotiation link partner ability register
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REG_MII_ANER = 6 ; auto negotiation expansion register
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REG_MII_ANER = 6 ; auto negotiation expansion register
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; MII bits
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; MII bits
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BIT_MII_AUTONEG_COMPLETE = 5 ; auto-negotiation complete
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BIT_MII_AUTONEG_COMPLETE = 5 ; auto-negotiation complete
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BIT_MII_PREAMBLE_SUPPRESSION = 6
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BIT_MII_PREAMBLE_SUPPRESSION = 6
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; eeprom bits and commands
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; eeprom bits and commands
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EEPROM_CMD_READ = 0x80
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EEPROM_CMD_READ = 0x80
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EEPROM_BIT_BUSY = 15
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EEPROM_BIT_BUSY = 15
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; eeprom registers
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; eeprom registers
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EEPROM_REG_OEM_NODE_ADDR = 0xa
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EEPROM_REG_OEM_NODE_ADDR= 0xa
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EEPROM_REG_CAPABILITIES = 0x10
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EEPROM_REG_CAPABILITIES = 0x10
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; Commands for command register
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; Commands for command register
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SELECT_REGISTER_WINDOW = (1 shl 11)
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SELECT_REGISTER_WINDOW = (1 shl 11)
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IS_VORTEX = 0x1
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IS_VORTEX = 0x1
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IS_BOOMERANG = 0x2
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IS_BOOMERANG = 0x2
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IS_CYCLONE = 0x4
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IS_CYCLONE = 0x4
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IS_TORNADO = 0x8
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IS_TORNADO = 0x8
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EEPROM_8BIT = 0x10
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EEPROM_8BIT = 0x10
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HAS_PWR_CTRL = 0x20
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HAS_PWR_CTRL = 0x20
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HAS_MII = 0x40
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HAS_MII = 0x40
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HAS_NWAY = 0x80
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HAS_NWAY = 0x80
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HAS_CB_FNS = 0x100
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HAS_CB_FNS = 0x100
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INVERT_MII_PWR = 0x200
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INVERT_MII_PWR = 0x200
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INVERT_LED_PWR = 0x400
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INVERT_LED_PWR = 0x400
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MAX_COLLISION_RESET = 0x800
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MAX_COLLISION_RESET = 0x800
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EEPROM_OFFSET = 0x1000
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EEPROM_OFFSET = 0x1000
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HAS_HWCKSM = 0x2000
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HAS_HWCKSM = 0x2000
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EXTRA_PREAMBLE = 0x4000
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EXTRA_PREAMBLE = 0x4000
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; Status
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; Status
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IntLatch = 0x0001
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IntLatch = 0x0001
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HostError = 0x0002
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HostError = 0x0002
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TxComplete = 0x0004
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TxComplete = 0x0004
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TxAvailable = 0x0008
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TxAvailable = 0x0008
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RxComplete = 0x0010
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RxComplete = 0x0010
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RxEarly = 0x0020
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RxEarly = 0x0020
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IntReq = 0x0040
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IntReq = 0x0040
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StatsFull = 0x0080
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StatsFull = 0x0080
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DMADone = 0x0100
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DMADone = 0x0100
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DownComplete = 0x0200
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DownComplete = 0x0200
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UpComplete = 0x0400
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UpComplete = 0x0400
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DMAInProgress = 0x0800 ; 1 shl 11 (DMA controller is still busy)
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DMAInProgress = 0x0800 ; 1 shl 11 (DMA controller is still busy)
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CmdInProgress = 0x1000 ; 1 shl 12 (EL3_CMD is still busy)
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CmdInProgress = 0x1000 ; 1 shl 12 (EL3_CMD is still busy)
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S_5_INTS = HostError + RxEarly + UpComplete + DownComplete ;+ TxComplete + RxComplete + TxAvailable
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S_5_INTS = HostError + RxEarly + UpComplete + DownComplete ;+ TxComplete + RxComplete + TxAvailable
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; Commands
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; Commands
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TotalReset = 0 shl 11
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TotalReset = 0 shl 11
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SelectWindow = 1 shl 11
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SelectWindow = 1 shl 11
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StartCoax = 2 shl 11
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StartCoax = 2 shl 11
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RxDisable = 3 shl 11
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RxDisable = 3 shl 11
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RxEnable = 4 shl 11
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RxEnable = 4 shl 11
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RxReset = 5 shl 11
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RxReset = 5 shl 11
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UpStall = 6 shl 11
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UpStall = 6 shl 11
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UpUnstall = (6 shl 11)+1
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UpUnstall = (6 shl 11)+1
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DownStall = (6 shl 11)+2
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DownStall = (6 shl 11)+2
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DownUnstall = (6 shl 11)+3
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DownUnstall = (6 shl 11)+3
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RxDiscard = 8 shl 11
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RxDiscard = 8 shl 11
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TxEnable = 9 shl 11
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TxEnable = 9 shl 11
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TxDisable = 10 shl 11
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TxDisable = 10 shl 11
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TxReset = 11 shl 11
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TxReset = 11 shl 11
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FakeIntr = 12 shl 11
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FakeIntr = 12 shl 11
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AckIntr = 13 shl 11
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AckIntr = 13 shl 11
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SetIntrEnb = 14 shl 11
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SetIntrEnb = 14 shl 11
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SetStatusEnb = 15 shl 11
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SetStatusEnb = 15 shl 11
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SetRxFilter = 16 shl 11
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SetRxFilter = 16 shl 11
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SetRxThreshold = 17 shl 11
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SetRxThreshold = 17 shl 11
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SetTxThreshold = 18 shl 11
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SetTxThreshold = 18 shl 11
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SetTxStart = 19 shl 11
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SetTxStart = 19 shl 11
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StartDMAUp = 20 shl 11
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StartDMAUp = 20 shl 11
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StartDMADown = (20 shl 11)+1
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StartDMADown = (20 shl 11)+1
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StatsEnable = 21 shl 11
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StatsEnable = 21 shl 11
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StatsDisable = 22 shl 11
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StatsDisable = 22 shl 11
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StopCoax = 23 shl 11
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StopCoax = 23 shl 11
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SetFilterBit = 25 shl 11
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SetFilterBit = 25 shl 11
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; Rx mode bits
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; Rx mode bits
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RxStation = 1
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RxStation = 1
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RxMulticast = 2
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RxMulticast = 2
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RxBroadcast = 4
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RxBroadcast = 4
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RxProm = 8
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RxProm = 8
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; RX/TX buffers sizes
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; RX/TX buffers sizes
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MAX_ETH_PKT_SIZE = 1536 ; max packet size
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MAX_ETH_PKT_SIZE = 1536 ; max packet size
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NUM_RX_DESC = 4 ; a power of 2 number
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NUM_RX_DESC = 4 ; a power of 2 number
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NUM_TX_DESC = 4 ; a power of 2 number
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NUM_TX_DESC = 4 ; a power of 2 number
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MAX_ETH_FRAME_SIZE = 1520 ; size of ethernet frame + bytes alignment
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MAX_ETH_FRAME_SIZE = 1520 ; size of ethernet frame + bytes alignment
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virtual at ebx
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virtual at ebx
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@ -739,7 +739,7 @@ reset:
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in al, dx
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in al, dx
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loop .loop
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loop .loop
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; Get rid of stary ints
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; Get rid of stray ints
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set_io REG_COMMAND
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set_io REG_COMMAND
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mov ax, AckIntr + 0xff
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mov ax, AckIntr + 0xff
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out dx, ax
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out dx, ax
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@ -761,24 +761,6 @@ reset:
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;>>>>>>>>>>>>>>>>>>
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;>>>>>>>>>>>>>>>>>>
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set_io 0
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set_io REG_COMMAND
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mov ax, RxEnable
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out dx, ax
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mov ax, TxEnable
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out dx, ax
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set_io REG_COMMAND
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mov ax, SetRxThreshold + 208
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out dx, ax
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mov ax, SetTxThreshold + 60 ;16 ; recommended by the manual :)
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out dx, ax
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mov ax, SELECT_REGISTER_WINDOW + 1
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out dx, ax
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xor eax, eax
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xor eax, eax
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; clear packet/byte counters
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; clear packet/byte counters
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@ -850,6 +832,26 @@ start_device:
|
|||||||
mov ax, SetIntrEnb + S_5_INTS
|
mov ax, SetIntrEnb + S_5_INTS
|
||||||
out dx, ax
|
out dx, ax
|
||||||
|
|
||||||
|
; Start RX/TX
|
||||||
|
|
||||||
|
set_io 0
|
||||||
|
set_io REG_COMMAND
|
||||||
|
mov ax, RxEnable
|
||||||
|
out dx, ax
|
||||||
|
|
||||||
|
mov ax, TxEnable
|
||||||
|
out dx, ax
|
||||||
|
|
||||||
|
set_io REG_COMMAND
|
||||||
|
mov ax, SetRxThreshold + 208
|
||||||
|
out dx, ax
|
||||||
|
|
||||||
|
mov ax, SetTxThreshold + 60 ;16 ; recommended by the manual :)
|
||||||
|
out dx, ax
|
||||||
|
|
||||||
|
mov ax, SELECT_REGISTER_WINDOW + 1
|
||||||
|
out dx, ax
|
||||||
|
|
||||||
ret
|
ret
|
||||||
|
|
||||||
|
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user