forked from KolibriOS/kolibrios
325 lines
7.6 KiB
NASM
325 lines
7.6 KiB
NASM
;; rs780 PCIe Core indirect regs test
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;; (C) art_zh 2010
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;; <kolibri@jerdev.co.uk>
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use32 ;
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org 0x0 ;
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db 'MENUET01' ;
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dd 0x01 ;
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dd START ;
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dd I_END ;
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dd 0x1000 ;
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dd 0x1000 ;
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dd 0x0 ;
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dd 0x0 ;
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include 'MACROS.INC' ;
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PCIE_SPACE equ 0xF0000000
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PCIEIND_INDEX equ 0xF00000E0
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PCIEIND_DATA equ 0xF00000E4
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BOX_COLOR equ 0xE0D8D0
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START:
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red:
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call draw_window
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still:
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mcall 10 ; event waiting
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cmp eax,1 ; redraw window
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je red ;
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cmp eax,2 ; key pressed?
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je key ;
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cmp eax,3 ; button hit?
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je button ;
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jmp still ; none of that
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;---------------------------------------------------------------------
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key: ; key pressed
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jmp red
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;---------------------------------------------------------------------
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button:
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mcall 17 ; get the button ID
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cmp ah, 1
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jne .bt2
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mcall -1
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.bt2:
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cmp ah, 2
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jne .bt3
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dec [Reg] ; Rg# decrement
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jmp red
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.bt3:
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cmp ah, 3
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jne .bt4
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inc [Reg] ; Rg# increment
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jmp red
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.bt4:
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cmp ah, 4
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jne .bt5
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add [Reg],16 ; PgDn
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jmp red
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.bt5:
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cmp ah, 5
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jne .bt6
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mov edx, [Reg]
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cmp edx, 16
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jb @f
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sub edx, 16
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mov [Reg],edx ; PgUp
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jmp red
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@@:
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xor edx, edx
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mov [Reg], edx
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jmp red
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.bt6:
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cmp ah, 6
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jne still
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mcall 37, 1 ; get the mouse pointer
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shr eax, 16 ; only X needed
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sub eax, 124 ; check the left border
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jb red
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xor edx, edx
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mov ebx, 12
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div ebx
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cmp eax, 32 ; check the right border
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jnb red
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mov ecx, 31
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sub ecx, eax ; reverse the bit order
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mov ebx, [Rct]
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btc ebx, ecx ; invert the bit
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mov eax, [Reg]
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mov [Rct], ebx
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call write_pcieind
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jmp red
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;------------------------------------------------
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print_config_reg:
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;------------------------------------------------
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mov eax, [Reg]
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; and eax, 0x0FF
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mov ebx, 3*65536+256 ; 3 hex digits
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mov ecx, eax
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mov dx,[stX]
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shl edx,16 ; = X*65536
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mov dx,[stY] ; = edx + Y
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mov esi,0
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mcall 47 ; print reg#
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mov ecx, edx
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call read_pcieind
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mov edx, ecx
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mov ecx, eax
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add edx, 36*65536 ; right column
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mov ebx, 8*65536+256 ; 8 hex digits
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mcall 47 ; print config data
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ret
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;------------------------------------------------
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read_pcieind:
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; in: [Reg] = reg# | out: eax = [Rct] = data
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;------------------------------------------------
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mov edx, PCIEIND_INDEX
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xor eax, eax
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mov al, byte [Reg]
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; or eax, 0x00020000 ; 2=translate to GPP; 1 = to SB; 0 = GFX (default)
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mov [edx], eax
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add dl, 4
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mov eax, [edx]
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mov [Rct], eax
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ret
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;------------------------------------------------
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write_pcieind:
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; in: [Reg] = reg#; [Rct] = data
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;------------------------------------------------
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mov edx, PCIEIND_INDEX
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xor eax, eax
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mov al, byte [Reg]
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; set bits [18:16] as shown above^ to access GPP os SB bridges ^
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mov [edx], eax
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add dl, 4
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mov eax, [Rct]
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mov [edx], eax
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sub dl, 4
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xor eax, eax ; reg#1 = SCRATCH
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inc al
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mov [edx], eax ; safely switch the index
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ret
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;------------------------------------------------
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draw_window:
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;------------------------------------------------
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mcall 12, 1
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mcall 0, 600*65536+530, 410*65536+290, 0x1494A0B0,,title
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; -----------------------------------------------------------------
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; BUTTONS: Xleft Xwid, Ytop Yheig
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mcall 8, 370*65536+ 40, 26*65536+ 18, 2, 0x94A0B0 ; <<
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mcall , , 51*65536+ 18, 3, ; >>
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mcall , 425*65536+ 90, 26*65536+ 18, 4, ; Next Page
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mcall , , 51*65536+ 18, 5, ; Prev Page
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mcall , 117*65536+400, 97*65536+ 40, 6, ; Bits
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call read_pcieind
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mov ebx, bitstr2
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inc ebx
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mov edx, [Rct]
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mov ecx, 0x80000000
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xor eax, eax
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.stringtest:
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test edx, ecx
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jz @f
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mov byte [ebx+eax*2],'I' ; bit dump
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jmp .nextbit
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@@:
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mov byte [ebx+eax*2],'0'
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.nextbit:
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inc eax
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shr ecx, 1
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jnz .stringtest
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; button txt: X *65536+ Y
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mcall 4, 378*65536+32 ,0x10000000, butstr2,3
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mcall , 378*65536+57 , , butstr3,
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mcall , 436*65536+32 , , butstr4,9
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mcall , 436*65536+57 , , butstr5,
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mcall 4, 122*65536+101,0 , bitstr0,65
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mcall , 122*65536+110,0 , bitstr1,65
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mcall , 122*65536+117,0 , bitstr2,65
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mcall , 122*65536+126,0 , bitstr3,65
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; -----------------------------------------------------------------
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; draw the reg-value box
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mov ebx, 10*65536+100 ; Xleft | Xwidth
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mov ecx, 26*65536+250 ; Ytop | Yheight
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mov edx, BOX_COLOR
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mcall 13
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; draw the reg-address box
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mov ebx, 206*65536+146 ; Xleft | Xwidth
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mov cx, 44 ; Yheight only
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mcall 13
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; fill the data box
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mov bx, 40 ; upper position
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mov [stY],bx
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mov eax, [Reg]
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mov [reg], eax ; store original#
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.print_reg_names:
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call print_config_reg
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add [stY],14
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inc [Reg]
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mov edx,[reg]
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mov eax, 16
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add eax, edx
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cmp eax,[Reg]
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ja .print_reg_names
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mov [Reg], edx ; restore original#
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; fill the status box
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mcall 4, 210*65536+30,0,str1,12
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mcall , 210*65536+44, ,str2,
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mcall , 210*65536+56, ,str3,
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call read_pcieind
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mov ecx, PCIEIND_DATA
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mov edx, 300*65536+30
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mov ebx, 8*65536+256
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mcall 47
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add dx, 14
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mov ecx,[Reg]
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mov esi, 0
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mcall 47
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add dx,14
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mov ecx, [Rct]
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mcall 47
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; print extra info
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mov ebx, 120*65536+170
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xor ecx, ecx
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mov edx, info1
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@@:
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mcall 4,,,,66
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add edx, 66
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add ebx, 14
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cmp edx, info_end
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jb @b
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mcall 12, 2
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ret
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align 4
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;-------------------------------------------------
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pix dd 0x55AACC33
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pxX dd 200
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pxY dd 160
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stX dw 18
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stY dw 0
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reg dd 0
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Rct dd 0 ; reg content
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Reg dd 0x00 ; reg number
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title db ' RS780 PCIe Core indirect registers ',0
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;------------------------------------------------------------------------------------
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reg_str db 'Reg#| hex.Value '
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;------------------------------------------------------------------------------------
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str1 db 'bdf address:'
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str2 db 'Reg. number:'
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str3 db 'Reg.content:'
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butstr2 db ' << '
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butstr3 db ' >> '
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butstr4 db 'Next Page'
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butstr5 db 'Prev Page'
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bitstr0 db '31',209,205,209,205,209,205,209,205,209,205,209,205,'24',\
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209,205,209,205,209,205,209,205,209,205,209,205,209,205,'16',\
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209,'15',205,209,205,209,205,209,205,209,205,209,205,209,'8',\
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205,'7',209,205,209,205,209,205,209,205,209,205,209,205,209,'0',184
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bitstr1 db 179,' | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ',179
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bitstr2 db 179,'1 0 9 8',179,'7 6 5 4',179,'3 2 1 0',179,'9 8 7 6',\
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179,'5 4 3 2',179,'1 0 9 8',179,'7 6 5 4',179,'3 2 1 0',179
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bitstr3 db 212,205,207,205,207,205,207,205,207,205,207,205,207,205,207,205,207,\
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205,207,205,207,205,207,205,207,205,207,205,207,205,207,205,207,205,207,\
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205,207,205,207,205,207,205,207,205,207,205,207,205,207,205,207,205,207,\
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205,207,205,207,205,207,205,207,205,207,205,190
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info1 db '------------- PCIe Core indirect registers shortlist -------------'
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db '| |'
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info2 db '| reg 13 - timeout status; 28,29 - line control |'
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db '| reg 41 - buffer status; 42 - decoder errors |'
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db '| reg 46 - symbol control; 60-62 impedance/strength control |'
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db '| reg 71-78 latency control; 82-8F ??? |'
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db '| reg EF - ERROR RESET; F0-FF error counters |'
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db '------------------------------------------------------------------'
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info_end:
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I_END: ; end of program
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rd 256
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align 256
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st_0:
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