forked from KolibriOS/kolibrios
711 lines
24 KiB
C
711 lines
24 KiB
C
/*
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* Copyright 2007-8 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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*/
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#include <drmP.h>
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#include <drm_crtc_helper.h>
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#include "radeon_drm.h"
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#include "radeon_fixed.h"
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#include "radeon.h"
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#include "atom.h"
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#include "atom-bits.h"
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static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
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{
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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struct drm_device *dev = crtc->dev;
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struct radeon_device *rdev = dev->dev_private;
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int index =
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GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
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ENABLE_CRTC_PS_ALLOCATION args;
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memset(&args, 0, sizeof(args));
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args.ucCRTC = radeon_crtc->crtc_id;
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args.ucEnable = lock;
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atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
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}
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static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
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{
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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struct drm_device *dev = crtc->dev;
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struct radeon_device *rdev = dev->dev_private;
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int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
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ENABLE_CRTC_PS_ALLOCATION args;
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memset(&args, 0, sizeof(args));
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args.ucCRTC = radeon_crtc->crtc_id;
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args.ucEnable = state;
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atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
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}
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static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
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{
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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struct drm_device *dev = crtc->dev;
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struct radeon_device *rdev = dev->dev_private;
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int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
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ENABLE_CRTC_PS_ALLOCATION args;
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memset(&args, 0, sizeof(args));
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args.ucCRTC = radeon_crtc->crtc_id;
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args.ucEnable = state;
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atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
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}
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static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
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{
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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struct drm_device *dev = crtc->dev;
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struct radeon_device *rdev = dev->dev_private;
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int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
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BLANK_CRTC_PS_ALLOCATION args;
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memset(&args, 0, sizeof(args));
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args.ucCRTC = radeon_crtc->crtc_id;
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args.ucBlanking = state;
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atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
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}
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void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
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{
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struct drm_device *dev = crtc->dev;
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struct radeon_device *rdev = dev->dev_private;
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switch (mode) {
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case DRM_MODE_DPMS_ON:
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if (ASIC_IS_DCE3(rdev))
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atombios_enable_crtc_memreq(crtc, 1);
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atombios_enable_crtc(crtc, 1);
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atombios_blank_crtc(crtc, 0);
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break;
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case DRM_MODE_DPMS_STANDBY:
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case DRM_MODE_DPMS_SUSPEND:
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case DRM_MODE_DPMS_OFF:
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atombios_blank_crtc(crtc, 1);
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atombios_enable_crtc(crtc, 0);
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if (ASIC_IS_DCE3(rdev))
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atombios_enable_crtc_memreq(crtc, 0);
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break;
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}
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if (mode != DRM_MODE_DPMS_OFF) {
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radeon_crtc_load_lut(crtc);
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}
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}
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static void
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atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
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SET_CRTC_USING_DTD_TIMING_PARAMETERS * crtc_param)
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{
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struct drm_device *dev = crtc->dev;
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struct radeon_device *rdev = dev->dev_private;
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SET_CRTC_USING_DTD_TIMING_PARAMETERS conv_param;
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int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
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conv_param.usH_Size = cpu_to_le16(crtc_param->usH_Size);
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conv_param.usH_Blanking_Time =
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cpu_to_le16(crtc_param->usH_Blanking_Time);
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conv_param.usV_Size = cpu_to_le16(crtc_param->usV_Size);
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conv_param.usV_Blanking_Time =
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cpu_to_le16(crtc_param->usV_Blanking_Time);
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conv_param.usH_SyncOffset = cpu_to_le16(crtc_param->usH_SyncOffset);
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conv_param.usH_SyncWidth = cpu_to_le16(crtc_param->usH_SyncWidth);
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conv_param.usV_SyncOffset = cpu_to_le16(crtc_param->usV_SyncOffset);
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conv_param.usV_SyncWidth = cpu_to_le16(crtc_param->usV_SyncWidth);
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conv_param.susModeMiscInfo.usAccess =
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cpu_to_le16(crtc_param->susModeMiscInfo.usAccess);
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conv_param.ucCRTC = crtc_param->ucCRTC;
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printk("executing set crtc dtd timing\n");
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atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&conv_param);
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}
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void atombios_crtc_set_timing(struct drm_crtc *crtc,
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SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION *
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crtc_param)
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{
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struct drm_device *dev = crtc->dev;
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struct radeon_device *rdev = dev->dev_private;
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SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION conv_param;
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int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
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conv_param.usH_Total = cpu_to_le16(crtc_param->usH_Total);
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conv_param.usH_Disp = cpu_to_le16(crtc_param->usH_Disp);
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conv_param.usH_SyncStart = cpu_to_le16(crtc_param->usH_SyncStart);
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conv_param.usH_SyncWidth = cpu_to_le16(crtc_param->usH_SyncWidth);
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conv_param.usV_Total = cpu_to_le16(crtc_param->usV_Total);
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conv_param.usV_Disp = cpu_to_le16(crtc_param->usV_Disp);
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conv_param.usV_SyncStart = cpu_to_le16(crtc_param->usV_SyncStart);
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conv_param.usV_SyncWidth = cpu_to_le16(crtc_param->usV_SyncWidth);
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conv_param.susModeMiscInfo.usAccess =
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cpu_to_le16(crtc_param->susModeMiscInfo.usAccess);
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conv_param.ucCRTC = crtc_param->ucCRTC;
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conv_param.ucOverscanRight = crtc_param->ucOverscanRight;
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conv_param.ucOverscanLeft = crtc_param->ucOverscanLeft;
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conv_param.ucOverscanBottom = crtc_param->ucOverscanBottom;
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conv_param.ucOverscanTop = crtc_param->ucOverscanTop;
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conv_param.ucReserved = crtc_param->ucReserved;
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printk("executing set crtc timing\n");
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atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&conv_param);
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}
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void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
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{
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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struct drm_device *dev = crtc->dev;
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struct radeon_device *rdev = dev->dev_private;
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struct drm_encoder *encoder = NULL;
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struct radeon_encoder *radeon_encoder = NULL;
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uint8_t frev, crev;
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int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
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SET_PIXEL_CLOCK_PS_ALLOCATION args;
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PIXEL_CLOCK_PARAMETERS *spc1_ptr;
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PIXEL_CLOCK_PARAMETERS_V2 *spc2_ptr;
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PIXEL_CLOCK_PARAMETERS_V3 *spc3_ptr;
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uint32_t sclock = mode->clock;
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uint32_t ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
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struct radeon_pll *pll;
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int pll_flags = 0;
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memset(&args, 0, sizeof(args));
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if (ASIC_IS_AVIVO(rdev)) {
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uint32_t ss_cntl;
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if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */
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pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
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else
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pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
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/* disable spread spectrum clocking for now -- thanks Hedy Lamarr */
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if (radeon_crtc->crtc_id == 0) {
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ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
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WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl & ~1);
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} else {
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ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
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WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl & ~1);
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}
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} else {
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pll_flags |= RADEON_PLL_LEGACY;
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if (mode->clock > 200000) /* range limits??? */
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pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
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else
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pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
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}
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list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
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if (encoder->crtc == crtc) {
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if (!ASIC_IS_AVIVO(rdev)) {
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if (encoder->encoder_type !=
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DRM_MODE_ENCODER_DAC)
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pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
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if (!ASIC_IS_AVIVO(rdev)
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&& (encoder->encoder_type ==
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DRM_MODE_ENCODER_LVDS))
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pll_flags |= RADEON_PLL_USE_REF_DIV;
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}
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radeon_encoder = to_radeon_encoder(encoder);
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}
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}
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if (radeon_crtc->crtc_id == 0)
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pll = &rdev->clock.p1pll;
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else
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pll = &rdev->clock.p2pll;
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radeon_compute_pll(pll, mode->clock, &sclock, &fb_div, &frac_fb_div,
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&ref_div, &post_div, pll_flags);
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atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
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&crev);
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switch (frev) {
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case 1:
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switch (crev) {
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case 1:
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spc1_ptr = (PIXEL_CLOCK_PARAMETERS *) & args.sPCLKInput;
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spc1_ptr->usPixelClock = cpu_to_le16(sclock);
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spc1_ptr->usRefDiv = cpu_to_le16(ref_div);
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spc1_ptr->usFbDiv = cpu_to_le16(fb_div);
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spc1_ptr->ucFracFbDiv = frac_fb_div;
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spc1_ptr->ucPostDiv = post_div;
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spc1_ptr->ucPpll =
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radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
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spc1_ptr->ucCRTC = radeon_crtc->crtc_id;
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spc1_ptr->ucRefDivSrc = 1;
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break;
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case 2:
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spc2_ptr =
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(PIXEL_CLOCK_PARAMETERS_V2 *) & args.sPCLKInput;
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spc2_ptr->usPixelClock = cpu_to_le16(sclock);
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spc2_ptr->usRefDiv = cpu_to_le16(ref_div);
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spc2_ptr->usFbDiv = cpu_to_le16(fb_div);
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spc2_ptr->ucFracFbDiv = frac_fb_div;
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spc2_ptr->ucPostDiv = post_div;
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spc2_ptr->ucPpll =
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radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
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spc2_ptr->ucCRTC = radeon_crtc->crtc_id;
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spc2_ptr->ucRefDivSrc = 1;
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break;
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case 3:
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if (!encoder)
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return;
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spc3_ptr =
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(PIXEL_CLOCK_PARAMETERS_V3 *) & args.sPCLKInput;
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spc3_ptr->usPixelClock = cpu_to_le16(sclock);
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spc3_ptr->usRefDiv = cpu_to_le16(ref_div);
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spc3_ptr->usFbDiv = cpu_to_le16(fb_div);
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spc3_ptr->ucFracFbDiv = frac_fb_div;
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spc3_ptr->ucPostDiv = post_div;
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spc3_ptr->ucPpll =
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radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
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spc3_ptr->ucMiscInfo = (radeon_crtc->crtc_id << 2);
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spc3_ptr->ucTransmitterId = radeon_encoder->encoder_id;
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spc3_ptr->ucEncoderMode =
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atombios_get_encoder_mode(encoder);
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break;
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default:
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DRM_ERROR("Unknown table version %d %d\n", frev, crev);
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return;
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}
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break;
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default:
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DRM_ERROR("Unknown table version %d %d\n", frev, crev);
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return;
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}
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printk("executing set pll\n");
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atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
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}
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int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
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struct drm_framebuffer *old_fb)
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{
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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struct drm_device *dev = crtc->dev;
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struct radeon_device *rdev = dev->dev_private;
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struct radeon_framebuffer *radeon_fb;
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struct drm_gem_object *obj;
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struct drm_radeon_gem_object *obj_priv;
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uint64_t fb_location;
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uint32_t fb_format, fb_pitch_pixels;
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ENTRY();
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if (!crtc->fb)
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return -EINVAL;
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radeon_fb = to_radeon_framebuffer(crtc->fb);
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obj = radeon_fb->obj;
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obj_priv = obj->driver_private;
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//if (radeon_gem_object_pin(obj, RADEON_GEM_DOMAIN_VRAM, &fb_location)) {
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// return -EINVAL;
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//}
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fb_location = rdev->mc.vram_location;
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dbgprintf("fb_location %x\n", fb_location);
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dbgprintf("bpp %x\n", crtc->fb->bits_per_pixel);
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switch (crtc->fb->bits_per_pixel) {
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case 15:
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fb_format =
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AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
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AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
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break;
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case 16:
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fb_format =
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AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
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AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
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break;
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case 24:
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case 32:
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fb_format =
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AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
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AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
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break;
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default:
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DRM_ERROR("Unsupported screen depth %d\n",
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crtc->fb->bits_per_pixel);
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return -EINVAL;
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}
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/* TODO tiling */
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if (radeon_crtc->crtc_id == 0)
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WREG32(AVIVO_D1VGA_CONTROL, 0);
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else
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WREG32(AVIVO_D2VGA_CONTROL, 0);
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WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
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(u32) fb_location);
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WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
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radeon_crtc->crtc_offset, (u32) fb_location);
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WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
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WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
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WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
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WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
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WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
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WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, crtc->fb->width);
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WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, crtc->fb->height);
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fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
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WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
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WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
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WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
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crtc->mode.vdisplay);
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x &= ~3;
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y &= ~1;
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WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
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(x << 16) | y);
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WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
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(crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
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if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
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WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
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AVIVO_D1MODE_INTERLEAVE_EN);
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else
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WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
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if (old_fb && old_fb != crtc->fb) {
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radeon_fb = to_radeon_framebuffer(old_fb);
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// radeon_gem_object_unpin(radeon_fb->obj);
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}
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|
LEAVE();
|
|
return 0;
|
|
}
|
|
|
|
int atombios_crtc_mode_set(struct drm_crtc *crtc,
|
|
struct drm_display_mode *mode,
|
|
struct drm_display_mode *adjusted_mode,
|
|
int x, int y, struct drm_framebuffer *old_fb)
|
|
{
|
|
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
|
|
struct drm_device *dev = crtc->dev;
|
|
struct radeon_device *rdev = dev->dev_private;
|
|
struct drm_encoder *encoder;
|
|
SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION crtc_timing;
|
|
|
|
ENTRY();
|
|
|
|
/* TODO color tiling */
|
|
memset(&crtc_timing, 0, sizeof(crtc_timing));
|
|
|
|
/* TODO tv */
|
|
list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
|
|
|
|
}
|
|
|
|
crtc_timing.ucCRTC = radeon_crtc->crtc_id;
|
|
crtc_timing.usH_Total = adjusted_mode->crtc_htotal;
|
|
crtc_timing.usH_Disp = adjusted_mode->crtc_hdisplay;
|
|
crtc_timing.usH_SyncStart = adjusted_mode->crtc_hsync_start;
|
|
crtc_timing.usH_SyncWidth =
|
|
adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
|
|
|
|
crtc_timing.usV_Total = adjusted_mode->crtc_vtotal;
|
|
crtc_timing.usV_Disp = adjusted_mode->crtc_vdisplay;
|
|
crtc_timing.usV_SyncStart = adjusted_mode->crtc_vsync_start;
|
|
crtc_timing.usV_SyncWidth =
|
|
adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
|
|
|
|
if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
|
|
crtc_timing.susModeMiscInfo.usAccess |= ATOM_VSYNC_POLARITY;
|
|
|
|
if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
|
|
crtc_timing.susModeMiscInfo.usAccess |= ATOM_HSYNC_POLARITY;
|
|
|
|
if (adjusted_mode->flags & DRM_MODE_FLAG_CSYNC)
|
|
crtc_timing.susModeMiscInfo.usAccess |= ATOM_COMPOSITESYNC;
|
|
|
|
if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
|
|
crtc_timing.susModeMiscInfo.usAccess |= ATOM_INTERLACE;
|
|
|
|
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
|
|
crtc_timing.susModeMiscInfo.usAccess |= ATOM_DOUBLE_CLOCK_MODE;
|
|
|
|
atombios_crtc_set_pll(crtc, adjusted_mode);
|
|
atombios_crtc_set_timing(crtc, &crtc_timing);
|
|
|
|
if (ASIC_IS_AVIVO(rdev))
|
|
atombios_crtc_set_base(crtc, x, y, old_fb);
|
|
else {
|
|
if (radeon_crtc->crtc_id == 0) {
|
|
SET_CRTC_USING_DTD_TIMING_PARAMETERS crtc_dtd_timing;
|
|
memset(&crtc_dtd_timing, 0, sizeof(crtc_dtd_timing));
|
|
|
|
/* setup FP shadow regs on R4xx */
|
|
crtc_dtd_timing.ucCRTC = radeon_crtc->crtc_id;
|
|
crtc_dtd_timing.usH_Size = adjusted_mode->crtc_hdisplay;
|
|
crtc_dtd_timing.usV_Size = adjusted_mode->crtc_vdisplay;
|
|
crtc_dtd_timing.usH_Blanking_Time =
|
|
adjusted_mode->crtc_hblank_end -
|
|
adjusted_mode->crtc_hdisplay;
|
|
crtc_dtd_timing.usV_Blanking_Time =
|
|
adjusted_mode->crtc_vblank_end -
|
|
adjusted_mode->crtc_vdisplay;
|
|
crtc_dtd_timing.usH_SyncOffset =
|
|
adjusted_mode->crtc_hsync_start -
|
|
adjusted_mode->crtc_hdisplay;
|
|
crtc_dtd_timing.usV_SyncOffset =
|
|
adjusted_mode->crtc_vsync_start -
|
|
adjusted_mode->crtc_vdisplay;
|
|
crtc_dtd_timing.usH_SyncWidth =
|
|
adjusted_mode->crtc_hsync_end -
|
|
adjusted_mode->crtc_hsync_start;
|
|
crtc_dtd_timing.usV_SyncWidth =
|
|
adjusted_mode->crtc_vsync_end -
|
|
adjusted_mode->crtc_vsync_start;
|
|
/* crtc_dtd_timing.ucH_Border = adjusted_mode->crtc_hborder; */
|
|
/* crtc_dtd_timing.ucV_Border = adjusted_mode->crtc_vborder; */
|
|
|
|
if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
|
|
crtc_dtd_timing.susModeMiscInfo.usAccess |=
|
|
ATOM_VSYNC_POLARITY;
|
|
|
|
if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
|
|
crtc_dtd_timing.susModeMiscInfo.usAccess |=
|
|
ATOM_HSYNC_POLARITY;
|
|
|
|
if (adjusted_mode->flags & DRM_MODE_FLAG_CSYNC)
|
|
crtc_dtd_timing.susModeMiscInfo.usAccess |=
|
|
ATOM_COMPOSITESYNC;
|
|
|
|
if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
|
|
crtc_dtd_timing.susModeMiscInfo.usAccess |=
|
|
ATOM_INTERLACE;
|
|
|
|
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
|
|
crtc_dtd_timing.susModeMiscInfo.usAccess |=
|
|
ATOM_DOUBLE_CLOCK_MODE;
|
|
|
|
atombios_set_crtc_dtd_timing(crtc, &crtc_dtd_timing);
|
|
}
|
|
radeon_crtc_set_base(crtc, x, y, old_fb);
|
|
radeon_legacy_atom_set_surface(crtc);
|
|
}
|
|
LEAVE();
|
|
|
|
return 0;
|
|
}
|
|
|
|
static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
|
|
struct drm_display_mode *mode,
|
|
struct drm_display_mode *adjusted_mode)
|
|
{
|
|
return true;
|
|
}
|
|
|
|
static void atombios_crtc_prepare(struct drm_crtc *crtc)
|
|
{
|
|
atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
|
|
atombios_lock_crtc(crtc, 1);
|
|
}
|
|
|
|
static void atombios_crtc_commit(struct drm_crtc *crtc)
|
|
{
|
|
atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
|
|
atombios_lock_crtc(crtc, 0);
|
|
}
|
|
|
|
static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
|
|
.dpms = atombios_crtc_dpms,
|
|
.mode_fixup = atombios_crtc_mode_fixup,
|
|
.mode_set = atombios_crtc_mode_set,
|
|
.mode_set_base = atombios_crtc_set_base,
|
|
.prepare = atombios_crtc_prepare,
|
|
.commit = atombios_crtc_commit,
|
|
};
|
|
|
|
void radeon_atombios_init_crtc(struct drm_device *dev,
|
|
struct radeon_crtc *radeon_crtc)
|
|
{
|
|
if (radeon_crtc->crtc_id == 1)
|
|
radeon_crtc->crtc_offset =
|
|
AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
|
|
drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
|
|
|
|
dbgprintf("done %s\n",__FUNCTION__);
|
|
|
|
}
|
|
|
|
void radeon_init_disp_bw_avivo(struct drm_device *dev,
|
|
struct drm_display_mode *mode1,
|
|
uint32_t pixel_bytes1,
|
|
struct drm_display_mode *mode2,
|
|
uint32_t pixel_bytes2)
|
|
{
|
|
struct radeon_device *rdev = dev->dev_private;
|
|
fixed20_12 min_mem_eff;
|
|
fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff;
|
|
fixed20_12 sclk_ff, mclk_ff;
|
|
uint32_t dc_lb_memory_split, temp;
|
|
|
|
min_mem_eff.full = rfixed_const_8(0);
|
|
if (rdev->disp_priority == 2) {
|
|
uint32_t mc_init_misc_lat_timer = 0;
|
|
if (rdev->family == CHIP_RV515)
|
|
mc_init_misc_lat_timer =
|
|
RREG32_MC(RV515_MC_INIT_MISC_LAT_TIMER);
|
|
else if (rdev->family == CHIP_RS690)
|
|
mc_init_misc_lat_timer =
|
|
RREG32_MC(RS690_MC_INIT_MISC_LAT_TIMER);
|
|
|
|
mc_init_misc_lat_timer &=
|
|
~(R300_MC_DISP1R_INIT_LAT_MASK <<
|
|
R300_MC_DISP1R_INIT_LAT_SHIFT);
|
|
mc_init_misc_lat_timer &=
|
|
~(R300_MC_DISP0R_INIT_LAT_MASK <<
|
|
R300_MC_DISP0R_INIT_LAT_SHIFT);
|
|
|
|
if (mode2)
|
|
mc_init_misc_lat_timer |=
|
|
(1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
|
|
if (mode1)
|
|
mc_init_misc_lat_timer |=
|
|
(1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
|
|
|
|
if (rdev->family == CHIP_RV515)
|
|
WREG32_MC(RV515_MC_INIT_MISC_LAT_TIMER,
|
|
mc_init_misc_lat_timer);
|
|
else if (rdev->family == CHIP_RS690)
|
|
WREG32_MC(RS690_MC_INIT_MISC_LAT_TIMER,
|
|
mc_init_misc_lat_timer);
|
|
}
|
|
|
|
/*
|
|
* determine is there is enough bw for current mode
|
|
*/
|
|
temp_ff.full = rfixed_const(100);
|
|
mclk_ff.full = rfixed_const(rdev->clock.default_mclk);
|
|
mclk_ff.full = rfixed_div(mclk_ff, temp_ff);
|
|
sclk_ff.full = rfixed_const(rdev->clock.default_sclk);
|
|
sclk_ff.full = rfixed_div(sclk_ff, temp_ff);
|
|
|
|
temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
|
|
temp_ff.full = rfixed_const(temp);
|
|
mem_bw.full = rfixed_mul(mclk_ff, temp_ff);
|
|
mem_bw.full = rfixed_mul(mem_bw, min_mem_eff);
|
|
|
|
pix_clk.full = 0;
|
|
pix_clk2.full = 0;
|
|
peak_disp_bw.full = 0;
|
|
if (mode1) {
|
|
temp_ff.full = rfixed_const(1000);
|
|
pix_clk.full = rfixed_const(mode1->clock); /* convert to fixed point */
|
|
pix_clk.full = rfixed_div(pix_clk, temp_ff);
|
|
temp_ff.full = rfixed_const(pixel_bytes1);
|
|
peak_disp_bw.full += rfixed_mul(pix_clk, temp_ff);
|
|
}
|
|
if (mode2) {
|
|
temp_ff.full = rfixed_const(1000);
|
|
pix_clk2.full = rfixed_const(mode2->clock); /* convert to fixed point */
|
|
pix_clk2.full = rfixed_div(pix_clk2, temp_ff);
|
|
temp_ff.full = rfixed_const(pixel_bytes2);
|
|
peak_disp_bw.full += rfixed_mul(pix_clk2, temp_ff);
|
|
}
|
|
|
|
if (peak_disp_bw.full >= mem_bw.full) {
|
|
DRM_ERROR
|
|
("You may not have enough display bandwidth for current mode\n"
|
|
"If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
|
|
printk("peak disp bw %d, mem_bw %d\n",
|
|
rfixed_trunc(peak_disp_bw), rfixed_trunc(mem_bw));
|
|
}
|
|
|
|
/*
|
|
* Line Buffer Setup
|
|
* There is a single line buffer shared by both display controllers.
|
|
* DC_LB_MEMORY_SPLIT controls how that line buffer is shared between the display
|
|
* controllers. The paritioning can either be done manually or via one of four
|
|
* preset allocations specified in bits 1:0:
|
|
* 0 - line buffer is divided in half and shared between each display controller
|
|
* 1 - D1 gets 3/4 of the line buffer, D2 gets 1/4
|
|
* 2 - D1 gets the whole buffer
|
|
* 3 - D1 gets 1/4 of the line buffer, D2 gets 3/4
|
|
* Setting bit 2 of DC_LB_MEMORY_SPLIT controls switches to manual allocation mode.
|
|
* In manual allocation mode, D1 always starts at 0, D1 end/2 is specified in bits
|
|
* 14:4; D2 allocation follows D1.
|
|
*/
|
|
|
|
/* is auto or manual better ? */
|
|
dc_lb_memory_split =
|
|
RREG32(AVIVO_DC_LB_MEMORY_SPLIT) & ~AVIVO_DC_LB_MEMORY_SPLIT_MASK;
|
|
dc_lb_memory_split &= ~AVIVO_DC_LB_MEMORY_SPLIT_SHIFT_MODE;
|
|
#if 1
|
|
/* auto */
|
|
if (mode1 && mode2) {
|
|
if (mode1->hdisplay > mode2->hdisplay) {
|
|
if (mode1->hdisplay > 2560)
|
|
dc_lb_memory_split |=
|
|
AVIVO_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q;
|
|
else
|
|
dc_lb_memory_split |=
|
|
AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
|
|
} else if (mode2->hdisplay > mode1->hdisplay) {
|
|
if (mode2->hdisplay > 2560)
|
|
dc_lb_memory_split |=
|
|
AVIVO_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
|
|
else
|
|
dc_lb_memory_split |=
|
|
AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
|
|
} else
|
|
dc_lb_memory_split |=
|
|
AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
|
|
} else if (mode1) {
|
|
dc_lb_memory_split |= AVIVO_DC_LB_MEMORY_SPLIT_D1_ONLY;
|
|
} else if (mode2) {
|
|
dc_lb_memory_split |= AVIVO_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
|
|
}
|
|
#else
|
|
/* manual */
|
|
dc_lb_memory_split |= AVIVO_DC_LB_MEMORY_SPLIT_SHIFT_MODE;
|
|
dc_lb_memory_split &=
|
|
~(AVIVO_DC_LB_DISP1_END_ADR_MASK <<
|
|
AVIVO_DC_LB_DISP1_END_ADR_SHIFT);
|
|
if (mode1) {
|
|
dc_lb_memory_split |=
|
|
((((mode1->hdisplay / 2) + 64) & AVIVO_DC_LB_DISP1_END_ADR_MASK)
|
|
<< AVIVO_DC_LB_DISP1_END_ADR_SHIFT);
|
|
} else if (mode2) {
|
|
dc_lb_memory_split |= (0 << AVIVO_DC_LB_DISP1_END_ADR_SHIFT);
|
|
}
|
|
#endif
|
|
WREG32(AVIVO_DC_LB_MEMORY_SPLIT, dc_lb_memory_split);
|
|
}
|