diff --git a/kernel/trunk/bus/pci/PCIe.inc b/kernel/trunk/bus/pci/PCIe.inc
index cd2cc9083b..4284b18c49 100644
--- a/kernel/trunk/bus/pci/PCIe.inc
+++ b/kernel/trunk/bus/pci/PCIe.inc
@@ -8,7 +8,6 @@
 ;;                                                              ;;
 ;;  Extended PCI express services                               ;;
 ;;                                                              ;;
-;;  Author:                                                     ;;
 ;;  	            art_zh  <artem@jerdev.co.uk>                ;;
 ;;                                                              ;;
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
@@ -30,15 +29,27 @@ $Revision: 1463 $
 ;***************************************************************************
 
 PCIe_CONFIG_SPACE	equ	0xF0000000	; to be moved to const.inc
-mmio_pcie_cfg_addr	dd  	0x0		; not defined by default
-mmio_pcie_cfg_lim	dd	0x0		; each bus needs 1Mb 
+mmio_pcie_cfg_addr	dd  	0x0	; intel pcie space may be defined here
+mmio_pcie_cfg_lim	dd	0x0		; upper pcie space address 
 
 
 align 4
 
 pci_ext_config:
 
-	push	ebx
+	mov	ebx, [mmio_pcie_cfg_addr]
+	or	ebx,ebx
+	jz	@f
+	or	ebx, 0x7FFFFFFF		; required by PCI-SIG standards 
+	jnz	.pcie_failed
+	add	ebx, 0x0FFFFC
+	cmp	ebx, [mmio_pcie_cfg_lim]; is the space limit correct?
+	ja	.pcie_failed
+	jmp	.pcie_cfg_mapped
+@@:
+	mov	ebx, [cpu_vendor]
+	cmp	ebx, dword [AMD_str]
+	jne	.pcie_failed
 	mov	bx, 0xC184		; dev = 24, fn = 01, reg = 84h
 
 .check_HT_mmio:
@@ -48,7 +59,7 @@ pci_ext_config:
 	mov	bx, cx
 	sub	bl, 4
 	and 	al, 0x80		; check the NP bit
-	jz	.not_pcie_cfg
+	jz	.no_pcie_cfg
 	shl	eax, 8			; bus:[27..20], dev:[19:15] 
 	or	eax, 0x00007FFC		; fun:[14..12], reg:[11:2] 
 	mov	[mmio_pcie_cfg_lim], eax
@@ -57,17 +68,17 @@ pci_ext_config:
 	call 	pci_read_reg
 	mov	bx, cx
 	test	al, 0x03		; MMIO Base RW enabled?
-	jz	.not_pcie_cfg
+	jz	.no_pcie_cfg
 	test	al, 0x0C		; MMIO Base locked?
-	jnz	.not_pcie_cfg
+	jnz	.no_pcie_cfg
 	xor	al, al
 	shl	eax, 8
-;	test	eax, 0x000F0000		; MMIO Base must be bus0-aligned
-;	jnz	.not_pcie_cfg
+	test	eax, 0x000F0000		; MMIO Base must be bus0-aligned
+	jnz	.no_pcie_cfg
 	mov	[mmio_pcie_cfg_addr], eax
 	add	eax, 0x000FFFFC
 	sub	eax,[mmio_pcie_cfg_lim]	; MMIO must cover at least one bus
-	ja	.not_pcie_cfg
+	ja	.no_pcie_cfg
 
 ;	-- it looks like a true PCIe config space; 
 	mov 	eax,[mmio_pcie_cfg_addr]	; physical address
@@ -89,12 +100,11 @@ pci_ext_config:
 .pcie_cfg_mapped:
 	
 ;	-- glad to have the extended PCIe config field found
-	mov	esi, boot_pcie_ok
-	pop	ebx
-	call	boot_log
+;	mov	esi, boot_pcie_ok
+;	call	boot_log
 	ret	; <<<<<<<<<<< OK >>>>>>>>>>>
 	
-.not_pcie_cfg:
+.no_pcie_cfg:
 
 	xor	eax, eax
 	mov	[mmio_pcie_cfg_addr], eax
@@ -102,8 +112,8 @@ pci_ext_config:
 	add	bl, 12
 	cmp	bl, 0xC0		; MMIO regs lay below this offset
 	jb	.check_HT_mmio
-	mov	esi, boot_pcie_fail
-	pop	ebx
-	call	boot_log
+.pcie_failed:
+;	mov	esi, boot_pcie_fail
+;	call	boot_log
 	ret	; <<<<<<<<< FAILURE >>>>>>>>>
 
diff --git a/kernel/trunk/memmap.inc b/kernel/trunk/memmap.inc
index 73bb649519..78656f4798 100644
--- a/kernel/trunk/memmap.inc
+++ b/kernel/trunk/memmap.inc
@@ -242,16 +242,20 @@
 ;         0C   dword  draw limit - y end
 ; 0x80339000 -> 3BFFF3   free (12k)
 ; 0x8033BFF4 -> 33BFFF   background info 
-; 0x8033C000 -> 3??FFF   page map: 1bit per page; size = mem_size>>15 (max: 128k)
-; 0x003??000 -> 3??FFF	 phys. location of system PTE head (12kb min); 
-; =====================================
-; 0x805FFF80 -> 5FFFFF   TSS  (128)
-; 0x80600000 -> 7FFFFF   extra kernel data structutes(2M max)
-; =====================================
+; 0x8033C000    	 page map     (length b = memsize shr 15)
+; 0x8033C000 + b         start of static pagetables
+
+; 0x803FFFFF <- no direct address translation beyond this point
+; ============================================================= 
+
+; 0x805FF000 -> 5FFF80   TSS  
+; 0x80600000 -> 601FFF   i/o maps
+
 ; 0x80800000 ->       kernel heap
 ; 0x80FFFFFF          heap min limit
 ; 0xFDBFFFFF          heap max limit
 
+; 0xF0000000 -> 0xF1FFFFFF  PCI-express extended config space
 ; 0xFDC00000 -> 0xFDFFFFFF  page tables 4Mb
 ; 0xFE000000 -> 0xFFFFFFFF  LFB 32Mb
 ; 0xFE000000 -> 0xFE7FFFFF  application available LFB 8Mb