forked from KolibriOS/kolibrios
r300_pio blit & transparent blit
git-svn-id: svn://kolibrios.org@868 a494cfbc-eb01-0410-851d-a64ba20cac60
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2860a7433c
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@ -1,13 +1,16 @@
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#define FILL_RECT 1
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#define DRAW_RECT 2
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#define LINE_2P 3
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#define BLIT 4
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#define COMPIZ 5
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#define PIXMAP 6
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#define PIXBLIT 7
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#define PIXLOCK 8
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#define PIXUNLOCK 9
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#define FILL_RECT 1
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#define DRAW_RECT 2
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#define LINE_2P 3
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#define BLIT 4
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#define COMPIZ 5
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#define PIXMAP 6
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#define PIXBLIT 7
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#define PIXLOCK 8
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#define PIXUNLOCK 9
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#define PIXDESTROY 10
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#define TRANSBLIT 11
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typedef unsigned int color_t;
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@ -95,10 +98,12 @@ int Blit(blit_t *blit);
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int RadeonComposite( blit_t *blit);
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int CreatePixmap(userpixmap_t *io);
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int DestroyPixmap(userpixmap_t *io);
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int LockPixmap(userpixmap_t *io);
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int UnlockPixmap(userpixmap_t *io);
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int PixBlit(pixblit_t* blit);
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int LockPixmap(userpixmap_t *io);
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# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
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# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
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@ -123,6 +128,8 @@ int LockPixmap(userpixmap_t *io);
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# define RADEON_CNTL_PAINT 0x00009100
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# define RADEON_CNTL_BITBLT 0x00009200
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# define RADEON_CNTL_TRANBLT 0x00009C00
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# define RADEON_CNTL_PAINT_POLYLINE 0x00009500
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# define RADEON_CNTL_PAINT_MULTI 0x00009A00
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@ -196,16 +196,20 @@ int Line2P(line2p_t *draw)
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#if R300_PIO
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R5xxFIFOWait(7);
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R5xxFIFOWait(6);
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OUTREG(R5XX_DP_GUI_MASTER_CNTL, rhd.gui_control | R5XX_ROP3_P |
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R5XX_GMC_BRUSH_SOLID_COLOR |
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R5XX_GMC_SRC_DATATYPE_COLOR);
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OUTREG(R5XX_DP_GUI_MASTER_CNTL,
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rhd.gui_control |
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R5XX_GMC_BRUSH_SOLID_COLOR |
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R5XX_GMC_SRC_DATATYPE_COLOR |
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R5XX_GMC_CLR_CMP_CNTL_DIS |
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R5XX_GMC_WR_MSK_DIS |
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R5XX_ROP3_P
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);
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OUTREG(R5XX_DST_LINE_PATCOUNT, 0x55 << R5XX_BRES_CNTL_SHIFT);
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OUTREG(R5XX_DP_BRUSH_FRGD_CLR, draw->color);
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OUTREG(R5XX_DP_WRITE_MASK, 0xFFFFFFFF);
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OUTREG(R5XX_DST_PITCH_OFFSET, rhd.dst_pitch_offset);
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OUTREG(R5XX_DST_LINE_START,(y0<<16)|x0);
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@ -219,7 +223,9 @@ int Line2P(line2p_t *draw)
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RADEON_GMC_BRUSH_SOLID_COLOR |
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RADEON_GMC_DST_32BPP |
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RADEON_GMC_SRC_DATATYPE_COLOR |
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(1 << 28)+(1 << 30) | R5XX_ROP3_P);
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R5XX_GMC_CLR_CMP_CNTL_DIS |
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R5XX_GMC_WR_MSK_DIS |
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R5XX_ROP3_P);
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OUT_RING(rhd.dst_pitch_offset);
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OUT_RING(draw->color);
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@ -365,6 +371,14 @@ int UnlockPixmap(userpixmap_t *io)
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if( (pixmap->flags & 1) != PX_LOCK )
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return ERR_PARAM;
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/* Sanity checks */
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if( (pixmap->usermap == 0)||
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((u32_t)pixmap->usermap >= 0x80000000) ||
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((u32_t)pixmap->usermap & 4095)
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)
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return ERR_PARAM;
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size = (pixmap->pitch*pixmap->width+4095) & ~ 4095;
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UnmapPages(pixmap->usermap, size);
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@ -403,6 +417,32 @@ int PixBlit(pixblit_t *blit)
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ifl = safe_cli();
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#if R300_PIO
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R5xxFIFOWait(7);
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OUTREG(R5XX_DP_GUI_MASTER_CNTL,
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RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
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RADEON_GMC_DST_PITCH_OFFSET_CNTL |
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RADEON_GMC_BRUSH_NONE |
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RADEON_GMC_DST_32BPP |
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RADEON_GMC_SRC_DATATYPE_COLOR |
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RADEON_DP_SRC_SOURCE_MEMORY |
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R5XX_GMC_CLR_CMP_CNTL_DIS |
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R5XX_GMC_WR_MSK_DIS |
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R5XX_ROP3_S
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);
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OUTREG(R5XX_DP_CNTL, R5XX_DST_X_LEFT_TO_RIGHT | R5XX_DST_Y_TOP_TO_BOTTOM);
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OUTREG(R5XX_DST_PITCH_OFFSET, dstpixmap->pitch_offset);
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OUTREG(R5XX_SRC_PITCH_OFFSET, srcpixmap->pitch_offset);
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OUTREG(R5XX_SRC_Y_X,(blit->src_y<<16)|blit->src_x);
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OUTREG(R5XX_DST_Y_X,(blit->dst_y<<16)|blit->dst_x);
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OUTREG(R5XX_DST_HEIGHT_WIDTH,(blit->h<<16)|blit->w);
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#else
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BEGIN_RING();
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OUT_RING(CP_PACKET3(RADEON_CNTL_BITBLT, 5));
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@ -413,7 +453,10 @@ int PixBlit(pixblit_t *blit)
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RADEON_GMC_DST_32BPP |
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RADEON_GMC_SRC_DATATYPE_COLOR |
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RADEON_DP_SRC_SOURCE_MEMORY |
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(1 << 28)+(1 << 30) | R5XX_ROP3_S);
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R5XX_GMC_CLR_CMP_CNTL_DIS |
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R5XX_GMC_WR_MSK_DIS |
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R5XX_ROP3_S
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);
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OUT_RING(srcpixmap->pitch_offset);
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OUT_RING(dstpixmap->pitch_offset);
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@ -423,6 +466,8 @@ int PixBlit(pixblit_t *blit)
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OUT_RING((blit->w<<16)|blit->h);
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COMMIT_RING();
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#endif
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safe_sti(ifl);
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return ERR_OK;
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}
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@ -439,7 +484,7 @@ int TransBlit(pixblit_t *blit)
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pixmap_t *srcpixmap;
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pixmap_t *dstpixmap;
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dbgprintf("Transblit src: %x dst: %x\n",blit->srcpix, blit->dstpix);
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// dbgprintf("Transblit src: %x dst: %x\n",blit->srcpix, blit->dstpix);
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dstpixmap = (blit->dstpix == (void*)-1) ? &scr_pixmap : blit->dstpix ;
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srcpixmap = (blit->srcpix == (void*)-1) ? &scr_pixmap : blit->srcpix ;
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@ -453,6 +498,36 @@ int TransBlit(pixblit_t *blit)
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ifl = safe_cli();
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#if R300_PIO
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R5xxFIFOWait(10);
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OUTREG(R5XX_DP_GUI_MASTER_CNTL,
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RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
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RADEON_GMC_DST_PITCH_OFFSET_CNTL |
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RADEON_GMC_BRUSH_NONE |
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RADEON_GMC_DST_32BPP |
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RADEON_GMC_SRC_DATATYPE_COLOR |
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RADEON_DP_SRC_SOURCE_MEMORY |
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R5XX_GMC_WR_MSK_DIS |
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R5XX_ROP3_S
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);
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OUTREG(R5XX_DP_CNTL, R5XX_DST_X_LEFT_TO_RIGHT | R5XX_DST_Y_TOP_TO_BOTTOM);
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OUTREG(R5XX_CLR_CMP_CLR_SRC, 0xFF000000);
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OUTREG(R5XX_CLR_CMP_MASK, R5XX_CLR_CMP_MSK);
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OUTREG(R5XX_CLR_CMP_CNTL, R5XX_SRC_CMP_EQ_COLOR | R5XX_CLR_CMP_SRC_SOURCE);
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OUTREG(R5XX_DST_PITCH_OFFSET, dstpixmap->pitch_offset);
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OUTREG(R5XX_SRC_PITCH_OFFSET, srcpixmap->pitch_offset);
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OUTREG(R5XX_SRC_Y_X,(blit->src_y<<16)|blit->src_x);
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OUTREG(R5XX_DST_Y_X,(blit->dst_y<<16)|blit->dst_x);
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OUTREG(R5XX_DST_HEIGHT_WIDTH,(blit->h<<16)|blit->w);
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#else
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BEGIN_RING();
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OUT_RING(CP_PACKET3(RADEON_CNTL_TRANBLT, 8));
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@ -462,20 +537,25 @@ int TransBlit(pixblit_t *blit)
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RADEON_GMC_DST_32BPP |
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RADEON_GMC_SRC_DATATYPE_COLOR |
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RADEON_DP_SRC_SOURCE_MEMORY |
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(1 << 30) | R5XX_ROP3_S);
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R5XX_GMC_WR_MSK_DIS |
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R5XX_ROP3_S
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);
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OUT_RING(srcpixmap->pitch_offset);
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OUT_RING(dstpixmap->pitch_offset);
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OUT_RING((2<<24)+5);
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OUT_RING(R5XX_CLR_CMP_SRC_SOURCE | R5XX_SRC_CMP_EQ_COLOR);
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OUT_RING(0xFF000000);
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OUT_RING(0xFF000000);
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OUT_RING((blit->src_x<<16)|blit->src_y);
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OUT_RING((blit->dst_x<<16)|blit->dst_y);
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OUT_RING((blit->w<<16)|blit->h);
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COMMIT_RING();
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#endif
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safe_sti(ifl);
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return ERR_OK;
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}
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@ -69,7 +69,7 @@ u32 __stdcall drvEntry(int action)
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R5xx2DInit();
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rhd.has_tcl = 1;
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Init3DEngine(&rhd);
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// Init3DEngine(&rhd);
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//init_r500();
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@ -5,7 +5,7 @@
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#define IS_R300_3D 0
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#define IS_R500_3D 1
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#define R300_PIO 0
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#define R300_PIO 1
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enum RHD_CHIPSETS {
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RHD_UNKNOWN = 0,
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#define kmalloc malloc
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#define kfree free
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#define xcalloc calloc
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///////////////////////////////////////////////////////////////////////////////
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int memcmp(const void *s1, const void *s2, size_t n);
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//#define R300_TEST
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#define R300_TEST
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#include "r5xx_regs.h"
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@ -353,8 +353,8 @@ void R5xx2DInit()
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u32 base;
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#ifdef R300_TEST
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rhd.displayWidth = 800;
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rhd.displayHeight = 600;
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rhd.displayWidth = 1024;
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rhd.displayHeight = 768;
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#else
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rhd.displayWidth = INREG(D1GRPH_X_END);
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rhd.displayHeight = INREG(D1GRPH_Y_END);
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@ -407,7 +407,7 @@ void R5xx2DInit()
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MASKREG( RADEON_AIC_CNTL,0, RADEON_PCIGART_TRANSLATE_EN);
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load_microcode();
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// load_microcode();
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rhd.ring_base = CreateRingBuffer(0x8000, PG_SW | PG_NOCACHE);
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dbgprintf("create cp ring buffer %x\n", rhd.ring_base);
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