forked from KolibriOS/kolibrios
4237496c20
- Fixed a bug with displaying incorrect temperature values. - Fixed memory leak (temporary failure of dlmalloc). - Small refactoring. - Use gnu99 to make empty functions with no return return 0. git-svn-id: svn://kolibrios.org@9827 a494cfbc-eb01-0410-851d-a64ba20cac60
647 lines
18 KiB
C
647 lines
18 KiB
C
#include <syscall.h>
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#include <linux/pci.h>
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LIST_HEAD(devices);
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/* PCI control bits. Shares IORESOURCE_BITS with above PCI ROM. */
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#define IORESOURCE_PCI_FIXED (1<<4) /* Do not move resource */
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#define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
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#define IORESOURCE_ROM_COPY (1<<2) /* ROM is alloc'd copy, resource field overlaid */
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#define IORESOURCE_ROM_BIOS_COPY (1<<3) /* ROM is BIOS copy, resource field overlaid */
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static inline unsigned int pci_calc_resource_flags(unsigned int flags)
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{
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if (flags & PCI_BASE_ADDRESS_SPACE_IO)
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return IORESOURCE_IO;
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if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
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return IORESOURCE_MEM | IORESOURCE_PREFETCH;
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return IORESOURCE_MEM;
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}
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static u32 pci_size(u32 base, u32 maxbase, u32 mask)
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{
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u32 size = mask & maxbase; /* Find the significant bits */
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if (!size)
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return 0;
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/* Get the lowest of them to find the decode size, and
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from that the extent. */
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size = (size & ~(size-1)) - 1;
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/* base == maxbase can be valid only if the BAR has
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already been programmed with all 1s. */
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if (base == maxbase && ((base | size) & mask) != mask)
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return 0;
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return size;
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}
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static u64 pci_size64(u64 base, u64 maxbase, u64 mask)
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{
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u64 size = mask & maxbase; /* Find the significant bits */
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if (!size)
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return 0;
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/* Get the lowest of them to find the decode size, and
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from that the extent. */
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size = (size & ~(size-1)) - 1;
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/* base == maxbase can be valid only if the BAR has
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already been programmed with all 1s. */
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if (base == maxbase && ((base | size) & mask) != mask)
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return 0;
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return size;
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}
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static inline int is_64bit_memory(u32 mask)
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{
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if ((mask & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
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(PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64))
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return 1;
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return 0;
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}
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static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
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{
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u32 pos, reg, next;
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u32 l, sz;
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struct resource *res;
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for(pos=0; pos < howmany; pos = next)
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{
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u64 l64;
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u64 sz64;
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u32 raw_sz;
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next = pos + 1;
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res = &dev->resource[pos];
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reg = PCI_BASE_ADDRESS_0 + (pos << 2);
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l = PciRead32(dev->busnr, dev->devfn, reg);
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PciWrite32(dev->busnr, dev->devfn, reg, ~0);
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sz = PciRead32(dev->busnr, dev->devfn, reg);
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PciWrite32(dev->busnr, dev->devfn, reg, l);
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if (!sz || sz == 0xffffffff)
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continue;
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if (l == 0xffffffff)
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l = 0;
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raw_sz = sz;
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if ((l & PCI_BASE_ADDRESS_SPACE) ==
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PCI_BASE_ADDRESS_SPACE_MEMORY)
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{
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sz = pci_size(l, sz, (u32)PCI_BASE_ADDRESS_MEM_MASK);
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/*
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* For 64bit prefetchable memory sz could be 0, if the
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* real size is bigger than 4G, so we need to check
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* szhi for that.
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*/
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if (!is_64bit_memory(l) && !sz)
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continue;
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res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
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res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK;
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}
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else {
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sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
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if (!sz)
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continue;
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res->start = l & PCI_BASE_ADDRESS_IO_MASK;
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res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK;
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}
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res->end = res->start + (unsigned long) sz;
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res->flags |= pci_calc_resource_flags(l);
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if (is_64bit_memory(l))
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{
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u32 szhi, lhi;
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lhi = PciRead32(dev->busnr, dev->devfn, reg+4);
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PciWrite32(dev->busnr, dev->devfn, reg+4, ~0);
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szhi = PciRead32(dev->busnr, dev->devfn, reg+4);
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PciWrite32(dev->busnr, dev->devfn, reg+4, lhi);
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sz64 = ((u64)szhi << 32) | raw_sz;
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l64 = ((u64)lhi << 32) | l;
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sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK);
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next++;
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#if BITS_PER_LONG == 64
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if (!sz64) {
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res->start = 0;
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res->end = 0;
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res->flags = 0;
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continue;
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}
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res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK;
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res->end = res->start + sz64;
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#else
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if (sz64 > 0x100000000ULL) {
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printk(KERN_ERR "PCI: Unable to handle 64-bit "
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"BAR for device %s\n", pci_name(dev));
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res->start = 0;
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res->flags = 0;
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}
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else if (lhi)
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{
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/* 64-bit wide address, treat as disabled */
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PciWrite32(dev->busnr, dev->devfn, reg,
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l & ~(u32)PCI_BASE_ADDRESS_MEM_MASK);
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PciWrite32(dev->busnr, dev->devfn, reg+4, 0);
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res->start = 0;
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res->end = sz;
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}
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#endif
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}
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}
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if ( rom )
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{
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dev->rom_base_reg = rom;
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res = &dev->resource[PCI_ROM_RESOURCE];
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l = PciRead32(dev->busnr, dev->devfn, rom);
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PciWrite32(dev->busnr, dev->devfn, rom, ~PCI_ROM_ADDRESS_ENABLE);
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sz = PciRead32(dev->busnr, dev->devfn, rom);
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PciWrite32(dev->busnr, dev->devfn, rom, l);
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if (l == 0xffffffff)
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l = 0;
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if (sz && sz != 0xffffffff)
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{
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sz = pci_size(l, sz, (u32)PCI_ROM_ADDRESS_MASK);
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if (sz)
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{
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res->flags = (l & IORESOURCE_ROM_ENABLE) |
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IORESOURCE_MEM | IORESOURCE_PREFETCH |
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IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
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res->start = l & PCI_ROM_ADDRESS_MASK;
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res->end = res->start + (unsigned long) sz;
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}
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}
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}
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}
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static void pci_read_irq(struct pci_dev *dev)
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{
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u8 irq;
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irq = PciRead8(dev->busnr, dev->devfn, PCI_INTERRUPT_PIN);
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dev->pin = irq;
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if (irq)
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irq = PciRead8(dev->busnr, dev->devfn, PCI_INTERRUPT_LINE);
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dev->irq = irq;
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};
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int pci_setup_device(struct pci_dev *dev)
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{
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u32 class;
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class = PciRead32(dev->busnr, dev->devfn, PCI_CLASS_REVISION);
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dev->revision = class & 0xff;
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class >>= 8; /* upper 3 bytes */
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dev->class = class;
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/* "Unknown power state" */
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// dev->current_state = PCI_UNKNOWN;
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/* Early fixups, before probing the BARs */
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// pci_fixup_device(pci_fixup_early, dev);
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class = dev->class >> 8;
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switch (dev->hdr_type)
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{
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case PCI_HEADER_TYPE_NORMAL: /* standard header */
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if (class == PCI_CLASS_BRIDGE_PCI)
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goto bad;
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pci_read_irq(dev);
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pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
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dev->subsystem_vendor = PciRead16(dev->busnr, dev->devfn,PCI_SUBSYSTEM_VENDOR_ID);
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dev->subsystem_device = PciRead16(dev->busnr, dev->devfn, PCI_SUBSYSTEM_ID);
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/*
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* Do the ugly legacy mode stuff here rather than broken chip
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* quirk code. Legacy mode ATA controllers have fixed
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* addresses. These are not always echoed in BAR0-3, and
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* BAR0-3 in a few cases contain junk!
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*/
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if (class == PCI_CLASS_STORAGE_IDE)
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{
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u8 progif;
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progif = PciRead8(dev->busnr, dev->devfn,PCI_CLASS_PROG);
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if ((progif & 1) == 0)
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{
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dev->resource[0].start = 0x1F0;
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dev->resource[0].end = 0x1F7;
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dev->resource[0].flags = LEGACY_IO_RESOURCE;
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dev->resource[1].start = 0x3F6;
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dev->resource[1].end = 0x3F6;
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dev->resource[1].flags = LEGACY_IO_RESOURCE;
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}
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if ((progif & 4) == 0)
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{
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dev->resource[2].start = 0x170;
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dev->resource[2].end = 0x177;
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dev->resource[2].flags = LEGACY_IO_RESOURCE;
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dev->resource[3].start = 0x376;
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dev->resource[3].end = 0x376;
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dev->resource[3].flags = LEGACY_IO_RESOURCE;
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};
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}
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break;
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case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
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if (class != PCI_CLASS_BRIDGE_PCI)
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goto bad;
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/* The PCI-to-PCI bridge spec requires that subtractive
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decoding (i.e. transparent) bridge must have programming
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interface code of 0x01. */
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pci_read_irq(dev);
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dev->transparent = ((dev->class & 0xff) == 1);
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pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
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break;
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case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
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if (class != PCI_CLASS_BRIDGE_CARDBUS)
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goto bad;
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pci_read_irq(dev);
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pci_read_bases(dev, 1, 0);
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dev->subsystem_vendor = PciRead16(dev->busnr,
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dev->devfn,
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PCI_CB_SUBSYSTEM_VENDOR_ID);
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dev->subsystem_device = PciRead16(dev->busnr,
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dev->devfn,
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PCI_CB_SUBSYSTEM_ID);
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break;
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default: /* unknown header */
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printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n",
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pci_name(dev), dev->hdr_type);
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return -1;
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bad:
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printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n",
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pci_name(dev), class, dev->hdr_type);
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dev->class = PCI_CLASS_NOT_DEFINED;
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}
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/* We found a fine healthy device, go go go... */
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return 0;
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};
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static pci_dev_t* pci_scan_device(u32 busnr, int devfn)
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{
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pci_dev_t *dev;
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u32 id;
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u8 hdr;
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int timeout = 10;
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id = PciRead32(busnr, devfn, PCI_VENDOR_ID);
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/* some broken boards return 0 or ~0 if a slot is empty: */
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if (id == 0xffffffff || id == 0x00000000 ||
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id == 0x0000ffff || id == 0xffff0000)
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return NULL;
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while (id == 0xffff0001)
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{
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delay(timeout/10);
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timeout *= 2;
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id = PciRead32(busnr, devfn, PCI_VENDOR_ID);
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/* Card hasn't responded in 60 seconds? Must be stuck. */
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if (timeout > 60 * 100)
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{
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printk(KERN_WARNING "Device %04x:%02x:%02x.%d not "
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"responding\n", busnr,PCI_SLOT(devfn),PCI_FUNC(devfn));
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return NULL;
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}
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};
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/* if( pci_scan_filter(id, busnr, devfn) == 0)
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return NULL;*/
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hdr = PciRead8(busnr, devfn, PCI_HEADER_TYPE);
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dev = (pci_dev_t*)KernelZeroAlloc(sizeof(pci_dev_t));
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if(unlikely(dev == NULL))
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return NULL;
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INIT_LIST_HEAD(&dev->link);
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dev->pci_dev.busnr = busnr;
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dev->pci_dev.devfn = devfn;
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dev->pci_dev.hdr_type = hdr & 0x7f;
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dev->pci_dev.multifunction = !!(hdr & 0x80);
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dev->pci_dev.vendor = id & 0xffff;
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dev->pci_dev.device = (id >> 16) & 0xffff;
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pci_setup_device(&dev->pci_dev);
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return dev;
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};
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int _pci_scan_slot(u32 bus, int devfn)
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{
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int func, nr = 0;
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for (func = 0; func < 8; func++, devfn++)
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{
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pci_dev_t *dev;
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dev = pci_scan_device(bus, devfn);
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if( dev )
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{
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list_add(&dev->link, &devices);
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nr++;
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/*
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* If this is a single function device,
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* don't scan past the first function.
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*/
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if (!dev->pci_dev.multifunction)
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{
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if (func > 0) {
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dev->pci_dev.multifunction = 1;
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}
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else {
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break;
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}
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}
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}
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else {
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if (func == 0)
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break;
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}
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};
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return nr;
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};
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#define PCI_FIND_CAP_TTL 48
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static int __pci_find_next_cap_ttl(unsigned int bus, unsigned int devfn,
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u8 pos, int cap, int *ttl)
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{
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u8 id;
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while ((*ttl)--) {
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pos = PciRead8(bus, devfn, pos);
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if (pos < 0x40)
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break;
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pos &= ~3;
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id = PciRead8(bus, devfn, pos + PCI_CAP_LIST_ID);
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if (id == 0xff)
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break;
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if (id == cap)
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return pos;
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pos += PCI_CAP_LIST_NEXT;
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}
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return 0;
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}
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static int __pci_find_next_cap(unsigned int bus, unsigned int devfn,
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u8 pos, int cap)
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{
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int ttl = PCI_FIND_CAP_TTL;
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return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
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}
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static int __pci_bus_find_cap_start(unsigned int bus,
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unsigned int devfn, u8 hdr_type)
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{
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u16 status;
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status = PciRead16(bus, devfn, PCI_STATUS);
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if (!(status & PCI_STATUS_CAP_LIST))
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return 0;
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switch (hdr_type) {
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case PCI_HEADER_TYPE_NORMAL:
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case PCI_HEADER_TYPE_BRIDGE:
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return PCI_CAPABILITY_LIST;
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case PCI_HEADER_TYPE_CARDBUS:
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return PCI_CB_CAPABILITY_LIST;
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default:
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return 0;
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}
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return 0;
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}
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int pci_find_capability(struct pci_dev *dev, int cap)
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{
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int pos;
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pos = __pci_bus_find_cap_start(dev->busnr, dev->devfn, dev->hdr_type);
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if (pos)
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pos = __pci_find_next_cap(dev->busnr, dev->devfn, pos, cap);
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return pos;
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}
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int enum_pci_devices(void)
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{
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pci_dev_t *dev;
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u32 last_bus;
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u32 bus = 0 , devfn = 0;
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last_bus = PciApi(1);
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if( unlikely(last_bus == -1))
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return -1;
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for(;bus <= last_bus; bus++)
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{
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for (devfn = 0; devfn < 0x100; devfn += 8){
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_pci_scan_slot(bus, devfn);
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}
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}
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dev = (pci_dev_t*)devices.next;
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while(&dev->link != &devices)
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{
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/*printk("PCI device %x:%x bus:%x devfn:%x\n",
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dev->pci_dev.vendor,
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dev->pci_dev.device,
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dev->pci_dev.busnr,
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dev->pci_dev.devfn);*/
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dev = (pci_dev_t*)dev->link.next;
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}
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return 0;
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}
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void free_pci_devices(void)
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{
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pci_dev_t *dev = (pci_dev_t*)devices.next;
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while(&dev->link != &devices) {
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pci_dev_t *temp = dev;
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dev = (pci_dev_t*)dev->link.next;
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KernelFree(temp);
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}
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}
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const struct pci_device_id* find_pci_device(pci_dev_t* pdev, const struct pci_device_id *idlist)
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{
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pci_dev_t *dev;
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const struct pci_device_id *ent;
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for(dev = (pci_dev_t*)devices.next;
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&dev->link != &devices;
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dev = (pci_dev_t*)dev->link.next)
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{
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if( dev->pci_dev.vendor != idlist->vendor )
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continue;
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for(ent = idlist; ent->vendor != 0; ent++)
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{
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if(unlikely(ent->device == dev->pci_dev.device))
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{
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pdev->pci_dev = dev->pci_dev;
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return ent;
|
|
}
|
|
};
|
|
}
|
|
|
|
return NULL;
|
|
};
|
|
|
|
struct pci_dev *
|
|
pci_get_device(unsigned int vendor, unsigned int device, struct pci_dev *from)
|
|
{
|
|
pci_dev_t *dev;
|
|
|
|
dev = (pci_dev_t*)devices.next;
|
|
|
|
if(from != NULL)
|
|
{
|
|
for(; &dev->link != &devices;
|
|
dev = (pci_dev_t*)dev->link.next)
|
|
{
|
|
if( &dev->pci_dev == from)
|
|
{
|
|
dev = (pci_dev_t*)dev->link.next;
|
|
break;
|
|
};
|
|
}
|
|
};
|
|
|
|
for(; &dev->link != &devices;
|
|
dev = (pci_dev_t*)dev->link.next)
|
|
{
|
|
if((dev->pci_dev.vendor != vendor) && (vendor != PCI_ANY_ID))
|
|
continue;
|
|
|
|
if((dev->pci_dev.device == device || device == PCI_ANY_ID))
|
|
{
|
|
return &dev->pci_dev;
|
|
}
|
|
}
|
|
return NULL;
|
|
};
|
|
|
|
|
|
struct pci_dev * _pci_get_bus_and_slot(unsigned int bus, unsigned int devfn)
|
|
{
|
|
pci_dev_t *dev;
|
|
|
|
for(dev = (pci_dev_t*)devices.next;
|
|
&dev->link != &devices;
|
|
dev = (pci_dev_t*)dev->link.next)
|
|
{
|
|
if ( dev->pci_dev.busnr == bus && dev->pci_dev.devfn == devfn)
|
|
return &dev->pci_dev;
|
|
}
|
|
return NULL;
|
|
}
|
|
|
|
struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from)
|
|
{
|
|
pci_dev_t *dev;
|
|
|
|
dev = (pci_dev_t*)devices.next;
|
|
|
|
if(from != NULL)
|
|
{
|
|
for(; &dev->link != &devices;
|
|
dev = (pci_dev_t*)dev->link.next)
|
|
{
|
|
if( &dev->pci_dev == from)
|
|
{
|
|
dev = (pci_dev_t*)dev->link.next;
|
|
break;
|
|
};
|
|
}
|
|
};
|
|
|
|
for(; &dev->link != &devices;
|
|
dev = (pci_dev_t*)dev->link.next)
|
|
{
|
|
if( dev->pci_dev.class == class)
|
|
{
|
|
return &dev->pci_dev;
|
|
}
|
|
}
|
|
|
|
return NULL;
|
|
}
|
|
|
|
|
|
int pci_bus_read_config_byte (struct pci_bus *bus, u32 devfn, int pos, u8 *value)
|
|
{
|
|
// raw_spin_lock_irqsave(&pci_lock, flags);
|
|
*value = PciRead8(bus->number, devfn, pos);
|
|
// raw_spin_unlock_irqrestore(&pci_lock, flags);
|
|
return 0;
|
|
}
|
|
|
|
int pci_bus_read_config_word (struct pci_bus *bus, u32 devfn, int pos, u16 *value)
|
|
{
|
|
if ( pos & 1)
|
|
return PCIBIOS_BAD_REGISTER_NUMBER;
|
|
// raw_spin_lock_irqsave(&pci_lock, flags);
|
|
*value = PciRead16(bus->number, devfn, pos);
|
|
// raw_spin_unlock_irqrestore(&pci_lock, flags);
|
|
return 0;
|
|
}
|
|
|
|
|
|
int pci_bus_read_config_dword (struct pci_bus *bus, u32 devfn, int pos, u32 *value)
|
|
{
|
|
if ( pos & 3)
|
|
return PCIBIOS_BAD_REGISTER_NUMBER;
|
|
*value = PciRead32(bus->number, devfn, pos);
|
|
return 0;
|
|
}
|
|
|
|
int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 val)
|
|
{
|
|
if ( where & 3)
|
|
return PCIBIOS_BAD_REGISTER_NUMBER;
|
|
PciWrite32(bus->number, devfn,where, val);
|
|
return 0;
|
|
}
|