forked from KolibriOS/kolibrios
420 lines
12 KiB
C
420 lines
12 KiB
C
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#include <ddk.h>
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#include <linux/errno.h>
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#include <mutex.h>
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#include <pci.h>
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#include <syscall.h>
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#define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
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/**
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* pci_setup_device - fill in class and map information of a device
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* @dev: the device structure to fill
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*
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* Initialize the device structure with information about the device's
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* vendor,class,memory and IO-space addresses,IRQ lines etc.
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* Called at initialisation of the PCI subsystem and by CardBus services.
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* Returns 0 on success and negative if unknown type of device (not normal,
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* bridge or CardBus).
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*/
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int pci_setup_device(struct pci_dev *dev)
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{
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u32 class;
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u8 hdr_type;
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struct pci_slot *slot;
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int pos = 0;
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if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
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return -EIO;
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dev->sysdata = dev->bus->sysdata;
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// dev->dev.parent = dev->bus->bridge;
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// dev->dev.bus = &pci_bus_type;
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dev->hdr_type = hdr_type & 0x7f;
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dev->multifunction = !!(hdr_type & 0x80);
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dev->error_state = pci_channel_io_normal;
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set_pcie_port_type(dev);
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list_for_each_entry(slot, &dev->bus->slots, list)
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if (PCI_SLOT(dev->devfn) == slot->number)
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dev->slot = slot;
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/* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
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set this higher, assuming the system even supports it. */
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dev->dma_mask = 0xffffffff;
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// dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
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// dev->bus->number, PCI_SLOT(dev->devfn),
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// PCI_FUNC(dev->devfn));
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pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
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dev->revision = class & 0xff;
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class >>= 8; /* upper 3 bytes */
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dev->class = class;
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class >>= 8;
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dbgprintf("found [%04x:%04x] class %06x header type %02x\n",
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dev->vendor, dev->device, class, dev->hdr_type);
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/* need to have dev->class ready */
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dev->cfg_size = pci_cfg_space_size(dev);
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/* "Unknown power state" */
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dev->current_state = PCI_UNKNOWN;
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/* Early fixups, before probing the BARs */
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// pci_fixup_device(pci_fixup_early, dev);
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/* device class may be changed after fixup */
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class = dev->class >> 8;
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switch (dev->hdr_type) { /* header type */
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case PCI_HEADER_TYPE_NORMAL: /* standard header */
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if (class == PCI_CLASS_BRIDGE_PCI)
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goto bad;
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pci_read_irq(dev);
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pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
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pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
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pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
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/*
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* Do the ugly legacy mode stuff here rather than broken chip
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* quirk code. Legacy mode ATA controllers have fixed
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* addresses. These are not always echoed in BAR0-3, and
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* BAR0-3 in a few cases contain junk!
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*/
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if (class == PCI_CLASS_STORAGE_IDE) {
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u8 progif;
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pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
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if ((progif & 1) == 0) {
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dev->resource[0].start = 0x1F0;
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dev->resource[0].end = 0x1F7;
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dev->resource[0].flags = LEGACY_IO_RESOURCE;
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dev->resource[1].start = 0x3F6;
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dev->resource[1].end = 0x3F6;
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dev->resource[1].flags = LEGACY_IO_RESOURCE;
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}
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if ((progif & 4) == 0) {
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dev->resource[2].start = 0x170;
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dev->resource[2].end = 0x177;
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dev->resource[2].flags = LEGACY_IO_RESOURCE;
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dev->resource[3].start = 0x376;
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dev->resource[3].end = 0x376;
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dev->resource[3].flags = LEGACY_IO_RESOURCE;
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}
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}
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break;
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case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
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if (class != PCI_CLASS_BRIDGE_PCI)
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goto bad;
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/* The PCI-to-PCI bridge spec requires that subtractive
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decoding (i.e. transparent) bridge must have programming
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interface code of 0x01. */
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pci_read_irq(dev);
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dev->transparent = ((dev->class & 0xff) == 1);
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pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
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set_pcie_hotplug_bridge(dev);
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pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
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if (pos) {
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pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
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pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
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}
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break;
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case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
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if (class != PCI_CLASS_BRIDGE_CARDBUS)
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goto bad;
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pci_read_irq(dev);
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pci_read_bases(dev, 1, 0);
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pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
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pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
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break;
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default: /* unknown header */
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dbgprintf("unknown header type %02x, "
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"ignoring device\n", dev->hdr_type);
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return -EIO;
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bad:
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dbgprintf("ignoring class %02x (doesn't match header "
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"type %02x)\n", class, dev->hdr_type);
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dev->class = PCI_CLASS_NOT_DEFINED;
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}
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/* We found a fine healthy device, go go go... */
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return 0;
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}
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struct pci_dev *alloc_pci_dev(void)
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{
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struct pci_dev *dev;
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dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
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if (!dev)
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return NULL;
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INIT_LIST_HEAD(&dev->bus_list);
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return dev;
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}
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/*
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* Read the config data for a PCI device, sanity-check it
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* and fill in the dev structure...
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*/
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static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
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{
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struct pci_dev *dev;
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u32 l;
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int timeout = 10;
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if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
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return NULL;
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/* some broken boards return 0 or ~0 if a slot is empty: */
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if (l == 0xffffffff || l == 0x00000000 ||
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l == 0x0000ffff || l == 0xffff0000)
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return NULL;
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/* Configuration request Retry Status */
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while (l == 0xffff0001) {
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delay(timeout/10);
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timeout *= 2;
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if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
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return NULL;
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/* Card hasn't responded in 60 seconds? Must be stuck. */
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if (delay > 60 * 1000) {
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printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not "
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"responding\n", pci_domain_nr(bus),
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bus->number, PCI_SLOT(devfn),
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PCI_FUNC(devfn));
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return NULL;
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}
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}
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dev = alloc_pci_dev();
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if (!dev)
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return NULL;
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dev->bus = bus;
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dev->devfn = devfn;
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dev->vendor = l & 0xffff;
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dev->device = (l >> 16) & 0xffff;
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if (pci_setup_device(dev)) {
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kfree(dev);
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return NULL;
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}
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return dev;
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}
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struct pci_dev * pci_scan_single_device(struct pci_bus *bus, int devfn)
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{
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struct pci_dev *dev;
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dev = pci_get_slot(bus, devfn);
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if (dev) {
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// pci_dev_put(dev);
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return dev;
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}
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dev = pci_scan_device(bus, devfn);
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if (!dev)
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return NULL;
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pci_device_add(dev, bus);
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return dev;
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}
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static unsigned next_ari_fn(struct pci_dev *dev, unsigned fn)
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{
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u16 cap;
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unsigned pos, next_fn;
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if (!dev)
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return 0;
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pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
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if (!pos)
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return 0;
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pci_read_config_word(dev, pos + 4, &cap);
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next_fn = cap >> 8;
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if (next_fn <= fn)
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return 0;
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return next_fn;
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}
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static unsigned next_trad_fn(struct pci_dev *dev, unsigned fn)
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{
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return (fn + 1) % 8;
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}
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static unsigned no_next_fn(struct pci_dev *dev, unsigned fn)
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{
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return 0;
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}
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static int only_one_child(struct pci_bus *bus)
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{
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struct pci_dev *parent = bus->self;
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if (!parent || !pci_is_pcie(parent))
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return 0;
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if (parent->pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
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parent->pcie_type == PCI_EXP_TYPE_DOWNSTREAM)
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return 1;
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return 0;
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}
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/**
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* pci_scan_slot - scan a PCI slot on a bus for devices.
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* @bus: PCI bus to scan
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* @devfn: slot number to scan (must have zero function.)
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*
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* Scan a PCI slot on the specified PCI bus for devices, adding
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* discovered devices to the @bus->devices list. New devices
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* will not have is_added set.
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*
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* Returns the number of new devices found.
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*/
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int pci_scan_slot(struct pci_bus *bus, int devfn)
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{
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unsigned fn, nr = 0;
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struct pci_dev *dev;
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unsigned (*next_fn)(struct pci_dev *, unsigned) = no_next_fn;
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if (only_one_child(bus) && (devfn > 0))
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return 0; /* Already scanned the entire slot */
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dev = pci_scan_single_device(bus, devfn);
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if (!dev)
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return 0;
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if (!dev->is_added)
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nr++;
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if (pci_ari_enabled(bus))
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next_fn = next_ari_fn;
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else if (dev->multifunction)
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next_fn = next_trad_fn;
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for (fn = next_fn(dev, 0); fn > 0; fn = next_fn(dev, fn)) {
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dev = pci_scan_single_device(bus, devfn + fn);
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if (dev) {
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if (!dev->is_added)
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nr++;
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dev->multifunction = 1;
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}
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}
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/* only one slot has pcie device */
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if (bus->self && nr)
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pcie_aspm_init_link_state(bus->self);
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return nr;
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}
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unsigned int pci_scan_child_bus(struct pci_bus *bus)
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{
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unsigned int devfn, pass, max = bus->secondary;
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struct pci_dev *dev;
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dbgprintf("scanning bus\n");
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/* Go find them, Rover! */
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for (devfn = 0; devfn < 0x100; devfn += 8)
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pci_scan_slot(bus, devfn);
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/* Reserve buses for SR-IOV capability. */
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max += pci_iov_bus_range(bus);
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/*
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* After performing arch-dependent fixup of the bus, look behind
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* all PCI-to-PCI bridges on this bus.
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*/
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if (!bus->is_added) {
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dbgprintf("fixups for bus\n");
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pcibios_fixup_bus(bus);
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if (pci_is_root_bus(bus))
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bus->is_added = 1;
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}
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for (pass=0; pass < 2; pass++)
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list_for_each_entry(dev, &bus->devices, bus_list) {
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if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
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dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
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max = pci_scan_bridge(bus, dev, max, pass);
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}
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/*
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* We've scanned the bus and so we know all about what's on
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* the other side of any bridges that may be on this bus plus
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* any devices.
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*
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* Return how far we've got finding sub-buses.
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*/
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dbgprintf("bus scan returning with max=%02x\n", max);
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return max;
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}
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/**
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* pci_cfg_space_size - get the configuration space size of the PCI device.
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* @dev: PCI device
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*
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* Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
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* have 4096 bytes. Even if the device is capable, that doesn't mean we can
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* access it. Maybe we don't have a way to generate extended config space
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* accesses, or the device is behind a reverse Express bridge. So we try
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* reading the dword at 0x100 which must either be 0 or a valid extended
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* capability header.
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*/
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int pci_cfg_space_size_ext(struct pci_dev *dev)
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{
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u32 status;
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int pos = PCI_CFG_SPACE_SIZE;
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if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
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goto fail;
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if (status == 0xffffffff)
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goto fail;
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return PCI_CFG_SPACE_EXP_SIZE;
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fail:
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return PCI_CFG_SPACE_SIZE;
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}
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int pci_cfg_space_size(struct pci_dev *dev)
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{
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int pos;
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u32 status;
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u16 class;
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class = dev->class >> 8;
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if (class == PCI_CLASS_BRIDGE_HOST)
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return pci_cfg_space_size_ext(dev);
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pos = pci_pcie_cap(dev);
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if (!pos) {
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pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
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if (!pos)
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goto fail;
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pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
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if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
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goto fail;
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}
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return pci_cfg_space_size_ext(dev);
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fail:
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return PCI_CFG_SPACE_SIZE;
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}
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