forked from KolibriOS/kolibrios
179 lines
4.1 KiB
C
179 lines
4.1 KiB
C
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#define FILL_RECT 1
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#define DRAW_RECT 2
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#define LINE_2P 3
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#define BLIT 4
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#define COMPIZ 5
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#define PIXMAP 6
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#define PIXBLIT 7
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#define PIXLOCK 8
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#define PIXUNLOCK 9
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#define PIXDESTROY 10
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#define TRANSBLIT 11
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typedef unsigned int color_t;
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typedef struct
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{
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pixmap_t *dstpix;
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int x;
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int y;
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u32_t w;
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u32_t h;
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color_t color;
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}draw_t;
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typedef struct
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{
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pixmap_t *dstpix;
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int x;
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int y;
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int w;
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int h;
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color_t bkcolor;
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color_t fcolor;
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u32_t bmp0;
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u32_t bmp1;
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}fill_t;
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typedef struct
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{
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int src_x;
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int src_y;
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int dst_x;
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int dst_y;
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int w;
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int h;
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}blit_t;
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typedef struct
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{
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int x0;
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int y0;
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int x1;
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int y1;
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u32 color;
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}line2p_t;
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typedef struct
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{
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pixmap_t *pixmap;
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void *usermap;
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u32_t format;
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u32_t pitch;
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u32_t width;
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u32_t height;
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}userpixmap_t;
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typedef struct
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{
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pixmap_t *dstpix;
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int dst_x;
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int dst_y;
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pixmap_t *srcpix;
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int src_x;
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int src_y;
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int w;
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int h;
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}pixblit_t;
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int LineClip( int *x1, int *y1, int *x2, int *y2 );
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int BlockClip( int *x1, int *y1, int *x2, int* y2);
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int DrawRect(draw_t * draw);
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int FillRect(fill_t * fill);
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int Line2P(line2p_t *draw);
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int Blit(blit_t *blit);
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int RadeonComposite( blit_t *blit);
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int CreatePixmap(userpixmap_t *io);
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int DestroyPixmap(userpixmap_t *io);
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int LockPixmap(userpixmap_t *io);
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int UnlockPixmap(userpixmap_t *io);
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int PixBlit(pixblit_t* blit);
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# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
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# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
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# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
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# define RADEON_GMC_BRUSH_NONE (15 << 4)
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# define RADEON_GMC_DST_16BPP (4 << 8)
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# define RADEON_GMC_DST_24BPP (5 << 8)
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# define RADEON_GMC_DST_32BPP (6 << 8)
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# define RADEON_GMC_DST_DATATYPE_SHIFT 8
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# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
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# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
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# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
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# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
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# define RADEON_GMC_WR_MSK_DIS (1 << 30)
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# define RADEON_ROP3_S 0x00cc0000
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# define RADEON_ROP3_P 0x00f00000
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#define RADEON_CP_PACKET0 0x00000000
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#define RADEON_CP_PACKET1 0x40000000
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#define RADEON_CP_PACKET2 0x80000000
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#define RADEON_CP_PACKET3 0xC0000000
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# define RADEON_CNTL_PAINT 0x00009100
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# define RADEON_CNTL_BITBLT 0x00009200
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# define RADEON_CNTL_TRANBLT 0x00009C00
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# define RADEON_CNTL_PAINT_POLYLINE 0x00009500
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# define RADEON_CNTL_PAINT_MULTI 0x00009A00
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#define CP_PACKET0(reg, n) \
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(RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
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#define CP_PACKET1(reg0, reg1) \
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(RADEON_CP_PACKET1 | (((reg1) >> 2) << 11) | ((reg0) >> 2))
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#define CP_PACKET2() \
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(RADEON_CP_PACKET2)
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#define CP_PACKET3( pkt, n ) \
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(RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
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#define BEGIN_RING( n ) do { \
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ring = rhd.ring_base; \
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write = rhd.ring_wp; \
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} while (0)
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#define ADVANCE_RING()
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#define OUT_RING( x ) do { \
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ring[write++] = (x); \
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} while (0)
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#define OUT_RING_REG(reg, val) \
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do { \
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OUT_RING(CP_PACKET0(reg, 0)); \
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OUT_RING(val); \
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} while (0)
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#define DRM_MEMORYBARRIER() __asm volatile("lock; addl $0,0(%%esp)" : : : "memory");
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#define COMMIT_RING() do { \
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rhd.ring_wp = write & 0x1FFF; \
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/* Flush writes to ring */ \
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DRM_MEMORYBARRIER(); \
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/*GET_RING_HEAD( dev_priv ); */ \
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OUTREG( RADEON_CP_RB_WPTR, rhd.ring_wp); \
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/* read from PCI bus to ensure correct posting */ \
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INREG( RADEON_CP_RB_RPTR ); \
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} while (0)
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