forked from KolibriOS/kolibrios
453 lines
12 KiB
C
453 lines
12 KiB
C
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typedef void *pointer;
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typedef unsigned int Bool;
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typedef unsigned int memType;
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typedef struct { float hi, lo; } range;
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#include "pci.h"
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#include "rhd_regs.h"
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#define IS_R300_3D 0
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#define IS_R500_3D 1
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#define R300_PIO 1
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enum RHD_CHIPSETS {
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RHD_UNKNOWN = 0,
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RHD_R300,
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RHD_R350,
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RHD_RV350,
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RHD_RV370,
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RHD_RV380,
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/* R500 */
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RHD_RV505,
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RHD_RV515,
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RHD_RV516,
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RHD_R520,
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RHD_RV530,
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RHD_RV535,
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RHD_RV550,
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RHD_RV560,
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RHD_RV570,
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RHD_R580,
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/* R500 Mobility */
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RHD_M52,
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RHD_M54,
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RHD_M56,
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RHD_M58,
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RHD_M62,
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RHD_M64,
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RHD_M66,
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RHD_M68,
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RHD_M71,
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/* R500 integrated */
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RHD_RS600,
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RHD_RS690,
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RHD_RS740,
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/* R600 */
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RHD_R600,
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RHD_RV610,
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RHD_RV630,
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/* R600 Mobility */
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RHD_M72,
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RHD_M74,
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RHD_M76,
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/* RV670 came into existence after RV6x0 and M7x */
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RHD_RV670,
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RHD_R680,
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RHD_RV620,
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RHD_M82,
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RHD_RV635,
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RHD_M86,
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RHD_RS780,
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RHD_CHIP_END
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};
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enum RHD_FAMILIES {
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RHD_FAMILY_UNKNOWN = 0,
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RHD_FAMILY_RADEON,
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RHD_FAMILY_RV100,
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RHD_FAMILY_RS100, /* U1 (IGP320M) or A3 (IGP320)*/
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RHD_FAMILY_RV200,
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RHD_FAMILY_RS200, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350), RS250 (IGP 7000) */
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RHD_FAMILY_R200,
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RHD_FAMILY_RV250,
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RHD_FAMILY_RS300, /* RS300/RS350 */
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RHD_FAMILY_RV280,
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RHD_FAMILY_R300,
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RHD_FAMILY_R350,
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RHD_FAMILY_RV350,
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RHD_FAMILY_RV380, /* RV370/RV380/M22/M24 */
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RHD_FAMILY_R420, /* R420/R423/M18 */
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RHD_FAMILY_RV410, /* RV410, M26 */
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RHD_FAMILY_RS400, /* xpress 200, 200m (RS400) Intel */
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RHD_FAMILY_RS480, /* xpress 200, 200m (RS410/480/482/485) AMD */
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RHD_FAMILY_RV515,
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RHD_FAMILY_R520,
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RHD_FAMILY_RV530,
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RHD_FAMILY_RV560,
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RHD_FAMILY_RV570,
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RHD_FAMILY_R580,
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RHD_FAMILY_RS690,
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RHD_FAMILY_R600,
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RHD_FAMILY_RV610,
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RHD_FAMILY_RV630,
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RHD_FAMILY_RV670,
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RHD_FAMILY_RV620,
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RHD_FAMILY_RV635,
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RHD_FAMILY_RS780
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};
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#define RHD_FB_BAR 0
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#define RHD_MMIO_BAR 2
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#define RHD_MEM_GART 1
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#define RHD_MEM_FB 2
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typedef struct RHDRec
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{
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u32_t MMIOBase;
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u32_t MMIOMapSize;
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u32_t videoRam;
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// CARD32 FbBase; /* map base of fb */
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u32_t PhisBase;
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u32_t FbIntAddress; /* card internal address of FB */
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u32_t FbMapSize;
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u32_t FbFreeStart;
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u32_t FbFreeSize;
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/* visible part of the framebuffer */
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unsigned int FbScanoutStart;
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unsigned int FbScanoutSize;
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enum RHD_CHIPSETS ChipSet;
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enum RHD_FAMILIES ChipFamily;
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char *ChipName;
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Bool IsIGP;
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u32_t bus;
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u32_t devfn;
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PCITAG PciTag;
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u16_t PciDeviceID;
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u16_t subvendor_id;
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u16_t subdevice_id;
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u32_t memBase[6];
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u32_t ioBase[6];
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u32_t memtype[6];
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u32_t memsize[6];
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struct mem_block *fb_heap;
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struct mem_block *gart_heap;
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u32_t displayWidth;
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u32_t displayHeight;
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int __xmin;
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int __ymin;
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int __xmax;
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int __ymax;
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u32_t gui_control;
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u32_t dst_pitch_offset;
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u32_t surface_cntl;
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u32_t *ring_base;
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u32_t ring_rp;
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u32_t ring_wp;
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int num_gb_pipes;
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Bool has_tcl;
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}RHD_t, *RHDPtr;
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extern RHD_t rhd;
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#define R5XX_DP_BRUSH_BKGD_CLR 0x1478
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#define R5XX_DP_BRUSH_FRGD_CLR 0x147c
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#define R5XX_BRUSH_DATA0 0x1480
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#define R5XX_BRUSH_DATA1 0x1484
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# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
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# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
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# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
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# define RADEON_GMC_BRUSH_NONE (15 << 4)
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# define RADEON_GMC_DST_16BPP (4 << 8)
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# define RADEON_GMC_DST_24BPP (5 << 8)
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# define RADEON_GMC_DST_32BPP (6 << 8)
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# define RADEON_GMC_DST_DATATYPE_SHIFT 8
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# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
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# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
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# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
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# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
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# define RADEON_GMC_WR_MSK_DIS (1 << 30)
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# define RADEON_ROP3_S 0x00cc0000
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# define RADEON_ROP3_P 0x00f00000
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#define RADEON_CP_PACKET0 0x00000000
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#define RADEON_CP_PACKET1 0x40000000
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#define RADEON_CP_PACKET2 0x80000000
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#define RADEON_CP_PACKET3 0xC0000000
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# define RADEON_CNTL_PAINT 0x00009100
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# define RADEON_CNTL_BITBLT 0x00009200
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# define RADEON_CNTL_TRANBLT 0x00009C00
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# define RADEON_CNTL_PAINT_POLYLINE 0x00009500
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# define RADEON_CNTL_PAINT_MULTI 0x00009A00
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#define CP_PACKET0(reg, n) \
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(RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
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#define CP_PACKET1(reg0, reg1) \
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(RADEON_CP_PACKET1 | (((reg1) >> 2) << 11) | ((reg0) >> 2))
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#define CP_PACKET2() \
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(RADEON_CP_PACKET2)
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#define CP_PACKET3( pkt, n ) \
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(RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
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#define BEGIN_RING( n ) do { \
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ring = rhd.ring_base; \
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write = rhd.ring_wp; \
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} while (0)
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#define ADVANCE_RING()
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#define OUT_RING( x ) do { \
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ring[write++] = (x); \
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} while (0)
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#define OUT_RING_REG(reg, val) \
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do { \
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OUT_RING(CP_PACKET0(reg, 0)); \
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OUT_RING(val); \
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} while (0)
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#define DRM_MEMORYBARRIER() __asm volatile("lock; addl $0,0(%%esp)" : : : "memory");
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#define COMMIT_RING() do { \
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rhd.ring_wp = write & 0x1FFF; \
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/* Flush writes to ring */ \
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DRM_MEMORYBARRIER(); \
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/*GET_RING_HEAD( dev_priv ); */ \
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OUTREG( RADEON_CP_RB_WPTR, rhd.ring_wp); \
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/* read from PCI bus to ensure correct posting */ \
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INREG( RADEON_CP_RB_RPTR ); \
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} while (0)
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typedef struct {
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int token; /* id of the token */
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const char * name; /* token name */
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} SymTabRec, *SymTabPtr;
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extern inline void
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OUTREG8(u16_t offset, u8_t value)
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{
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*(volatile u8_t *)((u8_t *)(rhd.MMIOBase + offset)) = value;
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}
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extern inline u32_t INREG(u16_t offset)
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{
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return *(volatile u32_t *)((u8_t*)(rhd.MMIOBase + offset));
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}
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//#define INREG(offset) *(volatile CARD32 *)((CARD8*)(rhd.MMIOBase + (offset)))
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extern inline void
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OUTREG(u16_t offset, u32_t value)
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{
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*(volatile u32_t *)((u8_t *)(rhd.MMIOBase + offset)) = value;
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}
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extern inline u32_t _RHDRegRead(RHDPtr rhdPtr, u16_t offset)
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{
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return *(volatile u32_t *)((u8_t*)(rhdPtr->MMIOBase + offset));
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}
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extern inline void
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MASKREG(u16_t offset, u32_t value, u32_t mask)
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{
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u32_t tmp;
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tmp = INREG(offset);
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tmp &= ~mask;
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tmp |= (value & mask);
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OUTREG(offset, tmp);
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};
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extern inline void
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_RHDRegWrite(RHDPtr rhdPtr, u16_t offset, u32_t value)
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{
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*(volatile u32_t *)((u8_t *)(rhdPtr->MMIOBase + offset)) = value;
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}
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extern inline void
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_RHDRegMask(RHDPtr rhdPtr, u16_t offset, u32_t value, u32_t mask)
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{
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u32_t tmp;
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tmp = _RHDRegRead(rhdPtr, offset);
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tmp &= ~mask;
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tmp |= (value & mask);
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_RHDRegWrite(rhdPtr, offset, tmp);
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};
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enum RHD_FAMILIES RHDFamily(enum RHD_CHIPSETS chipset);
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#define RHDRegRead(ptr, offset) _RHDRegRead((ptr)->rhdPtr, (offset))
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#define RHDRegWrite(ptr, offset, value) _RHDRegWrite((ptr)->rhdPtr, (offset), (value))
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#define RHDRegMask(ptr, offset, value, mask) _RHDRegMask((ptr)->rhdPtr, (offset), (value), (mask))
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RHDPtr FindPciDevice();
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Bool RHDPreInit();
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int rhdInitHeap(RHDPtr rhdPtr);
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#define RHDFUNC(ptr)
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#define DBG(x) x
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// #define DBG(x)
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#pragma pack (push,1)
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typedef struct s_cursor
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{
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u32_t magic; // 'CURS'
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void (*destroy)(struct s_cursor*); // destructor
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u32_t fd; // next object in list
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u32_t bk; // prev object in list
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u32_t pid; // owner id
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void *base; // allocated memory
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u32_t hot_x; // hotspot coords
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u32_t hot_y;
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}cursor_t;
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#pragma pack (pop)
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#define LOAD_FROM_FILE 0
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#define LOAD_FROM_MEM 1
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#define LOAD_INDIRECT 2
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cursor_t *create_cursor(u32_t pid, void *src, u32_t flags);
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void __stdcall copy_cursor(void *img, void *src);
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void destroy_cursor(cursor_t *cursor);
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void __destroy_cursor(cursor_t *cursor); // wrap
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void __stdcall r500_SelectCursor(cursor_t *cursor);
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void __stdcall r500_SetCursor(cursor_t *cursor, int x, int y);
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void __stdcall r500_CursorRestore(int x, int y);
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void R5xx2DInit();
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typedef struct {
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u32_t x ;
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u32_t y ;
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} xPointFixed;
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typedef u32_t xFixed_16_16;
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typedef xFixed_16_16 xFixed;
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#define XFIXED_BITS 16
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#define xFixedToInt(f) (int) ((f) >> XFIXED_BITS)
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#define IntToxFixed(i) ((xFixed) (i) << XFIXED_BITS)
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#define xFixedToFloat(f) (((float) (f)) / 65536)
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#define PICT_FORMAT(bpp,type,a,r,g,b) (((bpp) << 24) | \
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((type) << 16) | \
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((a) << 12) | \
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((r) << 8) | \
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((g) << 4) | \
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((b)))
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#define PICT_FORMAT_A(f) (((f) >> 12) & 0x0f)
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#define PICT_FORMAT_RGB(f) (((f) ) & 0xfff)
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#define PICT_TYPE_OTHER 0
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#define PICT_TYPE_A 1
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#define PICT_TYPE_ARGB 2
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#define PICT_TYPE_ABGR 3
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#define PICT_TYPE_COLOR 4
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#define PICT_TYPE_GRAY 5
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typedef enum _PictFormatShort {
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PICT_a8r8g8b8 = PICT_FORMAT(32,PICT_TYPE_ARGB,8,8,8,8),
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PICT_x8r8g8b8 = PICT_FORMAT(32,PICT_TYPE_ARGB,0,8,8,8),
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PICT_a8b8g8r8 = PICT_FORMAT(32,PICT_TYPE_ABGR,8,8,8,8),
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PICT_x8b8g8r8 = PICT_FORMAT(32,PICT_TYPE_ABGR,0,8,8,8),
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/* 24bpp formats */
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PICT_r8g8b8 = PICT_FORMAT(24,PICT_TYPE_ARGB,0,8,8,8),
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PICT_b8g8r8 = PICT_FORMAT(24,PICT_TYPE_ABGR,0,8,8,8),
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/* 16bpp formats */
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PICT_r5g6b5 = PICT_FORMAT(16,PICT_TYPE_ARGB,0,5,6,5),
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PICT_b5g6r5 = PICT_FORMAT(16,PICT_TYPE_ABGR,0,5,6,5),
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PICT_a1r5g5b5 = PICT_FORMAT(16,PICT_TYPE_ARGB,1,5,5,5),
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PICT_x1r5g5b5 = PICT_FORMAT(16,PICT_TYPE_ARGB,0,5,5,5),
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PICT_a1b5g5r5 = PICT_FORMAT(16,PICT_TYPE_ABGR,1,5,5,5),
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PICT_x1b5g5r5 = PICT_FORMAT(16,PICT_TYPE_ABGR,0,5,5,5),
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PICT_a4r4g4b4 = PICT_FORMAT(16,PICT_TYPE_ARGB,4,4,4,4),
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PICT_x4r4g4b4 = PICT_FORMAT(16,PICT_TYPE_ARGB,0,4,4,4),
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PICT_a4b4g4r4 = PICT_FORMAT(16,PICT_TYPE_ABGR,4,4,4,4),
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PICT_x4b4g4r4 = PICT_FORMAT(16,PICT_TYPE_ABGR,0,4,4,4),
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/* 8bpp formats */
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PICT_a8 = PICT_FORMAT(8,PICT_TYPE_A,8,0,0,0),
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PICT_r3g3b2 = PICT_FORMAT(8,PICT_TYPE_ARGB,0,3,3,2),
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PICT_b2g3r3 = PICT_FORMAT(8,PICT_TYPE_ABGR,0,3,3,2),
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PICT_a2r2g2b2 = PICT_FORMAT(8,PICT_TYPE_ARGB,2,2,2,2),
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PICT_a2b2g2r2 = PICT_FORMAT(8,PICT_TYPE_ABGR,2,2,2,2),
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PICT_c8 = PICT_FORMAT(8,PICT_TYPE_COLOR,0,0,0,0),
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PICT_g8 = PICT_FORMAT(8,PICT_TYPE_GRAY,0,0,0,0),
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PICT_x4a4 = PICT_FORMAT(8,PICT_TYPE_A,4,0,0,0),
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PICT_x4c4 = PICT_FORMAT(8,PICT_TYPE_COLOR,0,0,0,0),
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PICT_x4g4 = PICT_FORMAT(8,PICT_TYPE_GRAY,0,0,0,0),
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/* 4bpp formats */
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PICT_a4 = PICT_FORMAT(4,PICT_TYPE_A,4,0,0,0),
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PICT_r1g2b1 = PICT_FORMAT(4,PICT_TYPE_ARGB,0,1,2,1),
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PICT_b1g2r1 = PICT_FORMAT(4,PICT_TYPE_ABGR,0,1,2,1),
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PICT_a1r1g1b1 = PICT_FORMAT(4,PICT_TYPE_ARGB,1,1,1,1),
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PICT_a1b1g1r1 = PICT_FORMAT(4,PICT_TYPE_ABGR,1,1,1,1),
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PICT_c4 = PICT_FORMAT(4,PICT_TYPE_COLOR,0,0,0,0),
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PICT_g4 = PICT_FORMAT(4,PICT_TYPE_GRAY,0,0,0,0),
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/* 1bpp formats */
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PICT_a1 = PICT_FORMAT(1,PICT_TYPE_A,1,0,0,0),
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PICT_g1 = PICT_FORMAT(1,PICT_TYPE_GRAY,0,0,0,0),
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} PictFormatShort;
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void dump_mem();
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