forked from KolibriOS/kolibrios
1699 lines
46 KiB
NASM
1699 lines
46 KiB
NASM
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; ;;
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;; Copyright (C) KolibriOS team 2004-2021. All rights reserved. ;;
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;; Distributed under terms of the GNU General Public License ;;
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;; ;;
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;; AMD PCnet driver for KolibriOS ;;
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;; ;;
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;; By hidnplayr & clevermouse ;;
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;; ;;
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;; Based on the PCnet32 driver for MenuetOS, by Jarek Pelczar ;;
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;; ;;
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;; GNU GENERAL PUBLIC LICENSE ;;
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;; Version 2, June 1991 ;;
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;; ;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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format PE DLL native
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entry START
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CURRENT_API = 0x0200
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COMPATIBLE_API = 0x0100
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API_VERSION = (COMPATIBLE_API shl 16) + CURRENT_API
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; configureable area
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MAX_DEVICES = 16 ; Maximum number of devices this driver may handle
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__DEBUG__ = 1 ; 1 = on, 0 = off
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__DEBUG_LEVEL__ = 2 ; 1 = verbose, 2 = errors only
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TX_RING_SIZE = 32 ; Number of packets in send ring buffer
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RX_RING_SIZE = 32 ; Number of packets in receive ring buffer
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; end configureable area
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section '.flat' readable writable executable
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include '../struct.inc'
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include '../macros.inc'
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include '../proc32.inc'
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include '../fdo.inc'
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include '../netdrv.inc'
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if (bsr TX_RING_SIZE)>(bsf TX_RING_SIZE)
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display 'TX_RING_SIZE must be a power of two'
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err
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end if
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if (bsr RX_RING_SIZE)>(bsf RX_RING_SIZE)
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display 'RX_RING_SIZE must be a power of two'
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err
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end if
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PORT_AUI = 0x00
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PORT_10BT = 0x01
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PORT_GPSI = 0x02
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PORT_MII = 0x03
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PORT_PORTSEL = 0x03
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PORT_ASEL = 0x04
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PORT_100 = 0x40
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PORT_FD = 0x80
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DMA_MASK = 0xffffffff
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TX_RING_LEN_BITS = ((bsf TX_RING_SIZE) shl 12)
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RX_RING_LEN_BITS = ((bsf RX_RING_SIZE) shl 4)
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PKT_BUF_SZ = 1544
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WIO_RDP = 0x10
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WIO_RAP = 0x12
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WIO_RESET = 0x14
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WIO_BDP = 0x16
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DWIO_RDP = 0x10
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DWIO_RAP = 0x14
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DWIO_RESET = 0x18
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DWIO_BDP = 0x1C
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; CSR registers
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CSR_CSR = 0x00
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CSR_IAB0 = 0x01
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CSR_IAB1 = 0x02
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CSR_IMR = 0x03
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CSR_TFEAT = 0x04
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CSR_EXTCTL1 = 0x05
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CSR_DTBLLEN = 0x06
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CSR_EXTCTL2 = 0x07
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CSR_MAR0 = 0x08
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CSR_MAR1 = 0x09
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CSR_MAR2 = 0x0A
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CSR_MAR3 = 0x0B
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CSR_PAR0 = 0x0C
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CSR_PAR1 = 0x0D
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CSR_PAR2 = 0x0E
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CSR_MODE = 0x0F
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CSR_RXADDR0 = 0x18
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CSR_RXADDR1 = 0x19
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CSR_TXADDR0 = 0x1E
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CSR_TXADDR1 = 0x1F
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CSR_TXPOLL = 0x2F
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CSR_RXPOLL = 0x31
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CSR_RXRINGLEN = 0x4C
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CSR_TXRINGLEN = 0x4E
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CSR_DMACTL = 0x50
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CSR_BUSTIMER = 0x52
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CSR_MEMERRTIMEO = 0x64
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CSR_ONNOWMISC = 0x74
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CSR_ADVFEAT = 0x7A
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CSR_MACCFG = 0x7D
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CSR_CHIPID0 = 0x58
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CSR_CHIPID1 = 0x59
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; Control and Status Register (CSR0)
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CSR_INIT = 0x0001 ;1 shl 0
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CSR_START = 0x0002 ;1 shl 1
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CSR_STOP = 0x0004 ;1 shl 2
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CSR_TX = 0x0008 ;1 shl 3
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CSR_TXON = 0x0010 ;1 shl 4
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CSR_RXON = 0x0020 ;1 shl 5
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CSR_INTEN = 0x0040 ;1 shl 6
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CSR_INTR = 0x0080 ;1 shl 7
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CSR_IDONE = 0x0100 ;1 shl 8
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CSR_TINT = 0x0200 ;1 shl 9
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CSR_RINT = 0x0400 ;1 shl 10
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CSR_MERR = 0x0800 ;1 shl 11
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CSR_MISS = 0x1000 ;1 shl 12
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CSR_CERR = 0x2000 ;1 shl 13
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; Interrupt masks and deferral control (CSR3)
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IMR_BSWAP = 0x0004
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IMR_ENMBA = 0x0008 ; enable modified backoff alg
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IMR_DXMT2PD = 0x0010
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IMR_LAPPEN = 0x0020 ; lookahead packet processing enb
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IMR_DXSUFLO = 0x0040 ; disable TX stop on underflow
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IMR_IDONE = 0x0100
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IMR_TINT = 0x0200
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IMR_RINT = 0x0400
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IMR_MERR = 0x0800
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IMR_MISS = 0x1000
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; Masked interrupts will be disabled.
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IMR = 0 ;IMR_IDONE ;or IMR_TINT or IMR_RINT or IMR_MERR or IMR_MISS
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; Test and features control (CSR4)
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TFEAT_TXSTRTMASK = 0x0004
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TFEAT_TXSTRT = 0x0008
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TFEAT_RXCCOFLOWM = 0x0010 ; Rx collision counter oflow
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TFEAT_RXCCOFLOW = 0x0020
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TFEAT_UINT = 0x0040
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TFEAT_UINTREQ = 0x0080
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TFEAT_MISSOFLOWM = 0x0100
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TFEAT_MISSOFLOW = 0x0200
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TFEAT_STRIP_FCS = 0x0400
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TFEAT_PAD_TX = 0x0800
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TFEAT_TXDPOLL = 0x1000
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TFEAT_DMAPLUS = 0x4000
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; Extended control and interrupt 1 (CSR5)
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EXTCTL1_SPND = 0x0001 ; suspend
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EXTCTL1_MPMODE = 0x0002 ; magic packet mode
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EXTCTL1_MPENB = 0x0004 ; magic packet enable
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EXTCTL1_MPINTEN = 0x0008 ; magic packet interrupt enable
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EXTCTL1_MPINT = 0x0010 ; magic packet interrupt
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EXTCTL1_MPPLBA = 0x0020 ; magic packet phys. logical bcast
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EXTCTL1_EXDEFEN = 0x0040 ; excessive deferral interrupt enb.
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EXTCTL1_EXDEF = 0x0080 ; excessive deferral interrupt
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EXTCTL1_SINTEN = 0x0400 ; system interrupt enable
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EXTCTL1_SINT = 0x0800 ; system interrupt
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EXTCTL1_LTINTEN = 0x4000 ; last TX interrupt enb
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EXTCTL1_TXOKINTD = 0x8000 ; TX OK interrupt disable
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; RX/TX descriptor len (CSR6)
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DTBLLEN_RLEN = 0x0F00
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DTBLLEN_TLEN = 0xF000
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; Extended control and interrupt 2 (CSR7)
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EXTCTL2_MIIPDTINTE = 0x0001
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EXTCTL2_MIIPDTINT = 0x0002
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EXTCTL2_MCCIINTE = 0x0004
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EXTCTL2_MCCIINT = 0x0008
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EXTCTL2_MCCINTE = 0x0010
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EXTCTL2_MCCINT = 0x0020
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EXTCTL2_MAPINTE = 0x0040
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EXTCTL2_MAPINT = 0x0080
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EXTCTL2_MREINTE = 0x0100
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EXTCTL2_MREINT = 0x0200
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EXTCTL2_STINTE = 0x0400
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EXTCTL2_STINT = 0x0800
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EXTCTL2_RXDPOLL = 0x1000
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EXTCTL2_RDMD = 0x2000
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EXTCTL2_RXFRTG = 0x4000
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EXTCTL2_FASTSPNDE = 0x8000
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; Mode (CSR15)
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MODE_RXD = 0x0001 ; RX disable
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MODE_TXD = 0x0002 ; TX disable
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MODE_LOOP = 0x0004 ; loopback enable
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MODE_TXCRCD = 0x0008
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MODE_FORCECOLL = 0x0010
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MODE_RETRYD = 0x0020
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MODE_INTLOOP = 0x0040
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MODE_PORTSEL = 0x0180
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MODE_RXVPAD = 0x2000
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MODE_RXNOBROAD = 0x4000
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MODE_PROMISC = 0x8000
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; BCR (Bus Control Registers)
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BCR_MMRA = 0x00 ; Master Mode Read Active
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BCR_MMW = 0x01 ; Master Mode Write Active
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BCR_MISCCFG = 0x02
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BCR_LED0 = 0x04
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BCR_LED1 = 0x05
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BCR_LED2 = 0x06
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BCR_LED3 = 0x07
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BCR_DUPLEX = 0x09
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BCR_BUSCTL = 0x12
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BCR_EECTL = 0x13
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BCR_SSTYLE = 0x14
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BCR_PCILAT = 0x16
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BCR_PCISUBVENID = 0x17
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BCR_PCISUBSYSID = 0x18
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BCR_SRAMSIZE = 0x19
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BCR_SRAMBOUND = 0x1A
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BCR_SRAMCTL = 0x1B
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BCR_MIICTL = 0x20
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BCR_MIIADDR = 0x21
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BCR_MIIDATA = 0x22
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BCR_PCIVENID = 0x23
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BCR_PCIPCAP = 0x24
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BCR_DATA0 = 0x25
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BCR_DATA1 = 0x26
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BCR_DATA2 = 0x27
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BCR_DATA3 = 0x28
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BCR_DATA4 = 0x29
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BCR_DATA5 = 0x2A
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BCR_DATA6 = 0x2B
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BCR_DATA7 = 0x2C
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BCR_ONNOWPAT0 = 0x2D
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BCR_ONNOWPAT1 = 0x2E
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BCR_ONNOWPAT2 = 0x2F
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BCR_PHYSEL = 0x31
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; RX status register
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RXSTAT_BPE = 0x0080 ; bus parity error
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RXSTAT_ENP = 0x0100 ; end of packet
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RXSTAT_STP = 0x0200 ; start of packet
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RXSTAT_BUFF = 0x0400 ; buffer error
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RXSTAT_CRC = 0x0800 ; CRC error
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RXSTAT_OFLOW = 0x1000 ; rx overrun
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RXSTAT_FRAM = 0x2000 ; framing error
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RXSTAT_ERR = 0x4000 ; error summary
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RXSTAT_OWN = 0x8000
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; TX status register
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TXSTAT_TRC = 0x0000000F ; transmit retries
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TXSTAT_RTRY = 0x04000000 ; retry
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TXSTAT_LCAR = 0x08000000 ; lost carrier
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TXSTAT_LCOL = 0x10000000 ; late collision
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TXSTAT_EXDEF = 0x20000000 ; excessive deferrals
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TXSTAT_UFLOW = 0x40000000 ; transmit underrun
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TXSTAT_BUFF = 0x80000000 ; buffer error
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TXCTL_OWN = 0x8000
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TXCTL_ERR = 0x4000 ; error summary
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TXCTL_ADD_FCS = 0x2000 ; add FCS to pkt
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TXCTL_MORE_LTINT = 0x1000
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TXCTL_ONE = 0x0800
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TXCTL_DEF = 0x0400
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TXCTL_STP = 0x0200
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TXCTL_ENP = 0x0100
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TXCTL_BPE = 0x0080
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TXCTL_MBO = 0x0000F000
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TXCTL_BUFSZ = 0x00000FFF
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MAX_PHYS = 32
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; Pcnet configuration structure
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struct pcnet_init_block
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mode dw ?
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tlen_rlen dw ?
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phys_addr dp ?
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reserved dw ?
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filter dq ?
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rx_ring_phys dd ?
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tx_ring_phys dd ?
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ends
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struct device ETH_DEVICE
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rb 0x100-($ and 0xff) ; align 256
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init_block pcnet_init_block
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rb 0x100-($ and 0xff) ; align 256
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rx_ring rb RX_RING_SIZE * sizeof.descriptor
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rb 0x100-($ and 0xff) ; align 256
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tx_ring rb TX_RING_SIZE * sizeof.descriptor
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cur_rx dd ?
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cur_tx dd ?
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last_tx dd ?
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options dd ?
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full_duplex db ?
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chip_version dw ?
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mii db ?
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ltint db ?
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dxsuflo db ?
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fset db ?
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fdx db ?
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io_addr dd ?
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irq_line db ?
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pci_bus dd ?
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pci_dev dd ?
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phy dw ?
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link_timer dd ?
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rb 0x100-($ and 0xff) ; align 256
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read_csr dd ?
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write_csr dd ?
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read_bcr dd ?
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write_bcr dd ?
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read_rap dd ?
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write_rap dd ?
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sw_reset dd ?
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ends
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struct descriptor
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base dd ?
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length dw ?
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status dw ?
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msg_length dw ?
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misc dw ?
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virtual dd ?
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ends
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; ;;
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;; proc START ;;
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;; ;;
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;; (standard driver proc) ;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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proc START c, reason:dword, cmdline:dword
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cmp [reason], DRV_ENTRY
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jne .fail
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DEBUGF 2,"Loading driver\n"
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invoke RegService, my_service, service_proc
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ret
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.fail:
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xor eax, eax
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ret
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endp
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; ;;
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;; proc SERVICE_PROC ;;
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;; ;;
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;; (standard driver proc) ;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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align 4
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proc service_proc stdcall, ioctl:dword
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mov edx, [ioctl]
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mov eax, [edx + IOCTL.io_code]
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;------------------------------------------------------
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cmp eax, 0 ;SRV_GETVERSION
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jne @F
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cmp [edx + IOCTL.out_size], 4
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jb .fail
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mov eax, [edx + IOCTL.output]
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mov [eax], dword API_VERSION
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xor eax, eax
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ret
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;------------------------------------------------------
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@@:
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cmp eax, 1 ;SRV_HOOK
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jne .fail
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cmp [edx + IOCTL.inp_size], 3 ; Data input must be at least 3 bytes
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jb .fail
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mov eax, [edx + IOCTL.input]
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cmp byte[eax], 1 ; 1 means device number and bus number (pci) are given
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jne .fail ; other types arent supported for this card yet
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; check if the device is already listed
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mov ecx, [devices]
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test ecx, ecx
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jz .firstdevice
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mov esi, device_list
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; mov eax, [edx + IOCTL.input] ; get the pci bus and device numbers
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mov ax, [eax+1] ;
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.nextdevice:
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mov ebx, [esi]
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cmp al, byte[ebx + device.pci_bus]
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jne @f
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cmp ah, byte[ebx + device.pci_dev]
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je .find_devicenum ; Device is already loaded, let's find it's device number
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@@:
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add esi, 4
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loop .nextdevice
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; This device doesnt have its own eth_device structure yet, lets create one
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.firstdevice:
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cmp [devices], MAX_DEVICES ; First check if the driver can handle one more card
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jae .fail
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allocate_and_clear ebx, sizeof.device, .fail
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; Fill in the direct call addresses into the struct
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mov [ebx + device.reset], reset
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mov [ebx + device.transmit], transmit
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mov [ebx + device.unload], unload
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mov [ebx + device.name], my_service
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; save the pci bus and device numbers
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mov eax, [edx + IOCTL.input]
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movzx ecx, byte[eax+1]
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mov [ebx + device.pci_bus], ecx
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movzx ecx, byte[eax+2]
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mov [ebx + device.pci_dev], ecx
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; Now, it's time to find the base io addres of the PCI device
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stdcall PCI_find_io, [ebx + device.pci_bus], [ebx + device.pci_dev]
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mov [ebx + device.io_addr], eax
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; We've found the io address, find IRQ now
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invoke PciRead8, [ebx + device.pci_bus], [ebx + device.pci_dev], PCI_header00.interrupt_line
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mov [ebx + device.irq_line], al
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DEBUGF 1,"Hooking into device, dev:%x, bus:%x, irq:%x, addr:%x\n",\
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[ebx + device.pci_dev]:1,[ebx + device.pci_bus]:1,[ebx + device.irq_line]:1,[ebx + device.io_addr]:4
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; Ok, the eth_device structure is ready, let's probe the device
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; Because initialization fires IRQ, IRQ handler must be aware of this device
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mov eax, [devices] ; Add the device structure to our device list
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mov [device_list+4*eax], ebx ; (IRQ handler uses this list to find device)
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inc [devices] ;
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call probe ; this function will output in eax
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test eax, eax
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jnz .destroy ; If an error occured, exit
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mov [ebx + device.type], NET_TYPE_ETH
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invoke NetRegDev
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cmp eax, -1
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je .destroy
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ret
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; If the device was already loaded, find the device number and return it in eax
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.find_devicenum:
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DEBUGF 1,"Trying to find device number of already registered device\n"
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invoke NetPtrToNum ; This kernel procedure converts a pointer to device struct in ebx
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; into a device number in edi
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mov eax, edi ; Application wants it in eax instead
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DEBUGF 1,"Kernel says: %u\n", eax
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ret
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; If an error occured, remove all allocated data and exit (returning -1 in eax)
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.destroy:
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; todo: reset device into virgin state
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add eax, NET_BUFF.data
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dec [devices]
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.err:
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DEBUGF 2,"Error, removing all data !\n"
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invoke KernelFree, ebx
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.fail:
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or eax, -1
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ret
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;------------------------------------------------------
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endp
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;;/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\;;
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;; ;;
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;; Actual Hardware dependent code starts here ;;
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;; ;;
|
|
;;/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\;;
|
|
|
|
align 4
|
|
unload:
|
|
|
|
cmp [ebx + device.link_timer], 0
|
|
je @f
|
|
invoke CancelTimerHS, [ebx + device.link_timer]
|
|
@@:
|
|
|
|
; TODO: (in this particular order)
|
|
;
|
|
; - Stop the device
|
|
; - Detach int handler
|
|
; - Remove device from local list (device_list)
|
|
; - call unregister function in kernel
|
|
; - Remove all allocated structures and buffers the card used
|
|
|
|
or eax, -1
|
|
ret
|
|
|
|
|
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
;;
|
|
;; probe: enables the device (if it really is a PCnet device)
|
|
;;
|
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
|
|
align 4
|
|
probe:
|
|
|
|
mov edx, [ebx + device.io_addr]
|
|
|
|
call wio_reset
|
|
|
|
xor ecx, ecx
|
|
call wio_read_csr
|
|
cmp eax, 4
|
|
jne .try_dwio
|
|
|
|
; Try Word I/O
|
|
mov ax, 88
|
|
add edx, WIO_RAP
|
|
out dx, ax
|
|
nop
|
|
nop
|
|
in ax, dx
|
|
sub edx, WIO_RAP
|
|
cmp ax, 88
|
|
jne .try_dwio
|
|
|
|
call switch_to_wio
|
|
|
|
jmp .L1
|
|
|
|
.try_dwio:
|
|
call dwio_reset
|
|
|
|
xor ecx, ecx
|
|
call dwio_read_csr
|
|
cmp eax, 4
|
|
jne .no_dev
|
|
|
|
; Try Dword I/O
|
|
add edx, DWIO_RAP
|
|
mov eax, 88
|
|
out dx, eax
|
|
nop
|
|
nop
|
|
in eax, dx
|
|
sub edx, DWIO_RAP
|
|
and eax, 0xffff
|
|
cmp eax, 88
|
|
jne .no_dev
|
|
|
|
call switch_to_dwio
|
|
|
|
jmp .L1
|
|
|
|
.no_dev:
|
|
DEBUGF 2,"device not found!\n"
|
|
mov eax, 1
|
|
ret
|
|
|
|
.L1:
|
|
mov ecx, CSR_CHIPID0
|
|
call [ebx + device.read_csr]
|
|
|
|
mov esi, eax
|
|
shr esi, 12
|
|
|
|
and ax, 0xfff
|
|
cmp ax, 3
|
|
jne .no_dev
|
|
|
|
mov ecx, CSR_CHIPID1
|
|
call [ebx + device.read_csr]
|
|
shl eax, 4
|
|
or eax, esi
|
|
mov [ebx + device.chip_version], ax
|
|
|
|
mov [ebx + device.fdx], 0
|
|
mov [ebx + device.mii], 0
|
|
mov [ebx + device.fset], 0
|
|
mov [ebx + device.dxsuflo], 0
|
|
mov [ebx + device.ltint], 0
|
|
|
|
cmp ax, 0x2420
|
|
je .L2
|
|
cmp ax, 0x2430
|
|
je .L2
|
|
|
|
mov [ebx + device.fdx], 1
|
|
|
|
cmp ax, 0x2621
|
|
je .L4
|
|
cmp ax, 0x2623
|
|
je .L5
|
|
cmp ax, 0x2624
|
|
je .L6
|
|
cmp ax, 0x2625
|
|
je .L7
|
|
cmp ax, 0x2626
|
|
je .L8
|
|
cmp ax, 0x2627
|
|
je .L9
|
|
|
|
DEBUGF 2,"Invalid chip rev\n"
|
|
jmp .no_dev
|
|
.L2:
|
|
mov [ebx + device.name], device_l2
|
|
jmp .L10
|
|
.L4:
|
|
mov [ebx + device.name], device_l4
|
|
; mov [ebx + device.fdx], 1
|
|
jmp .L10
|
|
.L5:
|
|
mov [ebx + device.name], device_l5
|
|
; mov [ebx + device.fdx], 1
|
|
mov [ebx + device.mii], 1
|
|
mov [ebx + device.fset], 1
|
|
mov [ebx + device.ltint], 1
|
|
jmp .L10
|
|
.L6:
|
|
mov [ebx + device.name], device_l6
|
|
; mov [ebx + device.fdx], 1
|
|
mov [ebx + device.mii], 1
|
|
mov [ebx + device.fset], 1
|
|
jmp .L10
|
|
.L7:
|
|
mov [ebx + device.name], device_l7
|
|
; mov [ebx + device.fdx], 1
|
|
mov [ebx + device.mii], 1
|
|
jmp .L10
|
|
.L8:
|
|
mov [ebx + device.name], device_l8
|
|
; mov [ebx + device.fdx], 1
|
|
mov ecx, CSR_RXPOLL
|
|
call dword [ebx + device.read_bcr]
|
|
call dword [ebx + device.write_bcr]
|
|
jmp .L10
|
|
.L9:
|
|
mov [ebx + device.name], device_l9
|
|
; mov [ebx + device.fdx], 1
|
|
mov [ebx + device.mii], 1
|
|
.L10:
|
|
DEBUGF 1,"device name: %s\n", [ebx + device.name]
|
|
|
|
cmp [ebx + device.fset], 1
|
|
jne .L11
|
|
mov ecx, BCR_BUSCTL
|
|
call [ebx + device.read_bcr]
|
|
or eax, 0x800
|
|
call [ebx + device.write_bcr]
|
|
|
|
mov ecx, CSR_DMACTL
|
|
; call [ebx + device.read_csr]
|
|
mov eax, 0xc00
|
|
call [ebx + device.write_csr]
|
|
|
|
mov [ebx + device.dxsuflo],1
|
|
mov [ebx + device.ltint],1
|
|
.L11:
|
|
|
|
; Make the device a bus master
|
|
invoke PciRead32, [ebx + device.pci_bus], [ebx + device.pci_dev], PCI_header00.command
|
|
or al, PCI_CMD_MASTER
|
|
invoke PciWrite32, [ebx + device.pci_bus], [ebx + device.pci_dev], PCI_header00.command, eax
|
|
|
|
mov [ebx + device.options], PORT_ASEL
|
|
mov [ebx + device.init_block.mode], MODE_RXD + MODE_TXD ; disable receive and transmit
|
|
mov [ebx + device.init_block.tlen_rlen], (TX_RING_LEN_BITS or RX_RING_LEN_BITS)
|
|
|
|
mov dword[ebx + device.init_block.filter], 0
|
|
mov dword[ebx + device.init_block.filter+4], 0
|
|
|
|
align 4
|
|
reset:
|
|
|
|
; Stop link check timer if it was already running
|
|
cmp [ebx + device.link_timer], 0
|
|
je @f
|
|
invoke CancelTimerHS, [ebx + device.link_timer]
|
|
@@:
|
|
|
|
; attach int handler
|
|
|
|
movzx eax, [ebx + device.irq_line]
|
|
DEBUGF 1,"Attaching int handler to irq %x\n", eax:1
|
|
invoke AttachIntHandler, eax, int_handler, ebx
|
|
test eax, eax
|
|
jnz @f
|
|
DEBUGF 2,"Could not attach int handler!\n"
|
|
or eax, -1
|
|
ret
|
|
@@:
|
|
|
|
mov edx, [ebx + device.io_addr]
|
|
call [ebx + device.sw_reset]
|
|
|
|
; Switch pcnet32 to 32bit mode
|
|
mov ecx, BCR_SSTYLE
|
|
mov eax, 2
|
|
call [ebx + device.write_bcr]
|
|
|
|
; set/reset autoselect bit
|
|
mov ecx, BCR_MISCCFG
|
|
call [ebx + device.read_bcr]
|
|
and eax, not 2
|
|
test [ebx + device.options], PORT_ASEL
|
|
jz @f
|
|
or eax, 2
|
|
@@:
|
|
call [ebx + device.write_bcr]
|
|
|
|
; Handle full duplex setting
|
|
cmp byte [ebx + device.full_duplex], 0
|
|
je .duplex_ok
|
|
mov ecx, BCR_DUPLEX
|
|
call [ebx + device.read_bcr]
|
|
and eax, not 3
|
|
test [ebx + device.options], PORT_FD
|
|
jz @f
|
|
or eax, 1
|
|
cmp [ebx + device.options], PORT_FD or PORT_AUI
|
|
jne .set_duplex
|
|
or eax, 2
|
|
jmp .set_duplex
|
|
@@:
|
|
test [ebx + device.options], PORT_ASEL
|
|
jz .set_duplex
|
|
cmp [ebx + device.chip_version], 0x2627
|
|
jne .set_duplex
|
|
or eax, 3
|
|
.set_duplex:
|
|
mov ecx, BCR_DUPLEX
|
|
call [ebx + device.write_bcr]
|
|
.duplex_ok:
|
|
|
|
; set/reset GPSI bit in test register
|
|
mov ecx, 124
|
|
call [ebx + device.read_csr]
|
|
mov ecx, [ebx + device.options]
|
|
and ecx, PORT_PORTSEL
|
|
cmp ecx, PORT_GPSI
|
|
jne @f
|
|
or eax, 0x10
|
|
@@:
|
|
call [ebx + device.write_csr]
|
|
cmp [ebx + device.mii], 0
|
|
je .L6
|
|
test [ebx + device.options], PORT_ASEL
|
|
jnz .L6
|
|
mov ecx, BCR_MIICTL
|
|
call [ebx + device.read_bcr]
|
|
and eax, not 0x38
|
|
test [ebx + device.options], PORT_FD
|
|
jz @f
|
|
or eax, 0x10
|
|
@@:
|
|
test [ebx + device.options], PORT_100
|
|
jz @f
|
|
or eax, 0x08
|
|
@@:
|
|
call [ebx + device.write_bcr]
|
|
jmp .L9
|
|
.L6:
|
|
test [ebx + device.options], PORT_ASEL
|
|
jz .L9
|
|
mov ecx, BCR_MIICTL
|
|
DEBUGF 1,"ASEL, enable auto-negotiation\n"
|
|
call [ebx + device.read_bcr]
|
|
and eax, not 0x98
|
|
or eax, 0x20
|
|
call [ebx + device.write_bcr]
|
|
.L9:
|
|
cmp [ebx + device.ltint], 0
|
|
je @f
|
|
mov ecx, 5
|
|
call [ebx + device.read_csr]
|
|
or eax, (1 shl 14)
|
|
call [ebx + device.write_csr]
|
|
@@:
|
|
mov eax, [ebx + device.options]
|
|
and eax, PORT_PORTSEL
|
|
shl eax, 7
|
|
mov [ebx + device.init_block.mode], ax
|
|
mov dword [ebx + device.init_block.filter], -1
|
|
mov dword [ebx + device.init_block.filter+4], -1
|
|
|
|
|
|
|
|
;-----------------------------
|
|
|
|
test [ebx + device.mii], 1
|
|
jz .no_mii
|
|
|
|
mov [ebx + device.phy], 0
|
|
|
|
.mii_loop:
|
|
mov ecx, MII_PHYSID1
|
|
call mdio_read
|
|
cmp ax, 0xffff
|
|
je .next
|
|
|
|
DEBUGF 1, "PHY ID1: 0x%x\n", ax
|
|
|
|
mov ecx, MII_PHYSID2
|
|
call mdio_read
|
|
cmp ax, 0xffff
|
|
je .next
|
|
|
|
DEBUGF 1, "PHY ID2: 0x%x\n", ax
|
|
|
|
jmp .got_phy
|
|
|
|
cmp [ebx + device.phy], 31
|
|
jne .next
|
|
mov ax, [ebx + device.chip_version]
|
|
inc ax
|
|
and ax, 0xfffe
|
|
cmp ax, 0x2624 ; 79c971 & 79c972 have phantom phy at id 31
|
|
je .got_phy
|
|
|
|
.next:
|
|
inc [ebx + device.phy]
|
|
cmp [ebx + device.phy], MAX_PHYS
|
|
jb .mii_loop
|
|
|
|
DEBUGF 2, "No PHY found!\n"
|
|
or eax, -1
|
|
ret
|
|
|
|
.got_phy:
|
|
DEBUGF 1, "Found PHY at 0x%x\n", [ebx + device.phy]:4
|
|
|
|
.no_mii:
|
|
|
|
;-----------------------------------------------
|
|
|
|
call read_mac
|
|
|
|
lea esi, [ebx + device.mac]
|
|
lea edi, [ebx + device.init_block.phys_addr]
|
|
movsd
|
|
movsw
|
|
|
|
call init_ring
|
|
test eax, eax
|
|
jnz .fail
|
|
|
|
mov edx, [ebx + device.io_addr] ; init ring destroys edx
|
|
|
|
lea eax, [ebx + device.init_block]
|
|
invoke GetPhysAddr
|
|
push eax
|
|
and eax, 0xffff
|
|
mov ecx, CSR_IAB0
|
|
call [ebx + device.write_csr]
|
|
pop eax
|
|
shr eax, 16
|
|
mov ecx, CSR_IAB1
|
|
call [ebx + device.write_csr]
|
|
|
|
mov ecx, CSR_TFEAT
|
|
mov eax, 0x0915 ; Auto TX PAD ?
|
|
call [ebx + device.write_csr]
|
|
|
|
; Set the interrupt mask
|
|
mov ecx, CSR_IMR
|
|
mov eax, IMR
|
|
call [ebx + device.write_csr]
|
|
|
|
; Initialise the device
|
|
xor ecx, ecx
|
|
mov eax, CSR_INIT
|
|
call [ebx + device.write_csr]
|
|
|
|
mov esi, 100
|
|
; xor ecx, ecx
|
|
@@:
|
|
call [ebx + device.read_csr]
|
|
test ax, CSR_IDONE
|
|
jnz @f
|
|
|
|
dec esi
|
|
jnz @r
|
|
DEBUGF 2,"Initialize timeout!\n"
|
|
@@:
|
|
|
|
; Start the device and enable interrupts
|
|
xor ecx, ecx
|
|
mov eax, CSR_START + CSR_INTEN
|
|
call [ebx + device.write_csr]
|
|
|
|
; Set the MTU
|
|
mov [ebx + device.mtu], 1514
|
|
|
|
mov [ebx + device.state], ETH_LINK_UNKNOWN
|
|
; Start media check timer
|
|
cmp [ebx + device.mii], 0
|
|
je @f
|
|
mov [ebx + device.state], ETH_LINK_DOWN
|
|
invoke TimerHS, 0, 50, check_media_mii, ebx
|
|
mov [ebx + device.link_timer], eax
|
|
@@:
|
|
|
|
DEBUGF 1,"reset complete\n"
|
|
xor eax, eax
|
|
.fail:
|
|
ret
|
|
|
|
|
|
align 4
|
|
init_ring:
|
|
|
|
DEBUGF 1,"init ring\n"
|
|
|
|
lea edi, [ebx + device.rx_ring]
|
|
mov eax, edi
|
|
invoke GetPhysAddr
|
|
mov [ebx + device.init_block.rx_ring_phys], eax
|
|
mov ecx, RX_RING_SIZE
|
|
.rx_init:
|
|
push ecx
|
|
invoke NetAlloc, PKT_BUF_SZ+NET_BUFF.data
|
|
pop ecx
|
|
test eax, eax
|
|
jz .out_of_mem
|
|
mov [edi + descriptor.virtual], eax
|
|
invoke GetPhysAddr
|
|
add eax, NET_BUFF.data
|
|
mov [edi + descriptor.base], eax
|
|
mov [edi + descriptor.length], - PKT_BUF_SZ
|
|
mov dword[edi + descriptor.msg_length], 0 ; also clears misc field
|
|
mov [edi + descriptor.status], RXSTAT_OWN
|
|
add edi, sizeof.descriptor
|
|
dec ecx
|
|
jnz .rx_init
|
|
|
|
lea edi, [ebx + device.tx_ring]
|
|
mov eax, edi
|
|
invoke GetPhysAddr
|
|
mov [ebx + device.init_block.tx_ring_phys], eax
|
|
mov ecx, TX_RING_SIZE
|
|
.tx_init:
|
|
mov [edi + descriptor.status], 0
|
|
add edi, sizeof.descriptor
|
|
dec ecx
|
|
jnz .tx_init
|
|
|
|
mov [ebx + device.init_block.tlen_rlen], (TX_RING_LEN_BITS or RX_RING_LEN_BITS)
|
|
|
|
mov [ebx + device.cur_tx], 0
|
|
mov [ebx + device.last_tx], 0
|
|
mov [ebx + device.cur_rx], 0
|
|
|
|
xor eax, eax
|
|
ret
|
|
|
|
.out_of_mem:
|
|
DEBUGF 2,"Out of memory!\n"
|
|
|
|
or eax, -1
|
|
ret
|
|
|
|
|
|
|
|
|
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
;; ;;
|
|
;; Transmit ;;
|
|
;; ;;
|
|
;; In: pointer to device structure in ebx ;;
|
|
;; ;;
|
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
|
|
|
proc transmit stdcall bufferptr
|
|
|
|
spin_lock_irqsave
|
|
|
|
mov esi, [bufferptr]
|
|
DEBUGF 1,"Transmitting packet, buffer:%x, size:%u\n", [bufferptr], [esi + NET_BUFF.length]
|
|
lea eax, [esi + NET_BUFF.data]
|
|
DEBUGF 1,"To: %x-%x-%x-%x-%x-%x From: %x-%x-%x-%x-%x-%x Type:%x%x\n",\
|
|
[eax+00]:2,[eax+01]:2,[eax+02]:2,[eax+03]:2,[eax+04]:2,[eax+05]:2,\
|
|
[eax+06]:2,[eax+07]:2,[eax+08]:2,[eax+09]:2,[eax+10]:2,[eax+11]:2,\
|
|
[eax+13]:2,[eax+12]:2
|
|
|
|
cmp [esi + NET_BUFF.length], 1514
|
|
ja .error
|
|
cmp [esi + NET_BUFF.length], 60
|
|
jb .error
|
|
|
|
; check descriptor
|
|
lea edi, [ebx + device.tx_ring]
|
|
mov ecx, [ebx + device.cur_tx]
|
|
shl ecx, 4
|
|
add edi, ecx
|
|
|
|
test [edi + descriptor.status], TXCTL_OWN
|
|
jnz .overrun
|
|
; descriptor is free, use it
|
|
mov [edi + descriptor.virtual], esi
|
|
mov eax, esi
|
|
add eax, [eax + NET_BUFF.offset]
|
|
invoke GetPhysAddr
|
|
mov [edi + descriptor.base], eax
|
|
; set length
|
|
mov eax, [esi + NET_BUFF.length]
|
|
neg eax
|
|
mov [edi + descriptor.length], ax
|
|
; put to transfer queue
|
|
mov [edi + descriptor.status], TXCTL_OWN + TXCTL_STP + TXCTL_ENP
|
|
|
|
; trigger an immediate send
|
|
mov edx, [ebx + device.io_addr]
|
|
xor ecx, ecx ; CSR0
|
|
call [ebx + device.read_csr]
|
|
or eax, CSR_TX
|
|
call [ebx + device.write_csr]
|
|
|
|
; get next descriptor
|
|
inc [ebx + device.cur_tx]
|
|
and [ebx + device.cur_tx], TX_RING_SIZE - 1
|
|
|
|
; Update stats
|
|
inc [ebx + device.packets_tx]
|
|
mov eax, [esi + NET_BUFF.length]
|
|
add dword[ebx + device.bytes_tx], eax
|
|
adc dword[ebx + device.bytes_tx + 4], 0
|
|
|
|
spin_unlock_irqrestore
|
|
xor eax, eax
|
|
ret
|
|
|
|
.error:
|
|
DEBUGF 2, "TX packet error\n"
|
|
inc [ebx + device.packets_tx_err]
|
|
invoke NetFree, [bufferptr]
|
|
|
|
spin_unlock_irqrestore
|
|
or eax, -1
|
|
ret
|
|
|
|
.overrun:
|
|
DEBUGF 2, "TX overrun\n"
|
|
inc [ebx + device.packets_tx_ovr]
|
|
invoke NetFree, [bufferptr]
|
|
|
|
spin_unlock_irqrestore
|
|
or eax, -1
|
|
ret
|
|
|
|
endp
|
|
|
|
|
|
;;;;;;;;;;;;;;;;;;;;;;;
|
|
;; ;;
|
|
;; Interrupt handler ;;
|
|
;; ;;
|
|
;;;;;;;;;;;;;;;;;;;;;;;
|
|
|
|
align 4
|
|
int_handler:
|
|
|
|
push ebx esi edi
|
|
|
|
DEBUGF 1,"INT\n"
|
|
|
|
; find pointer of device wich made IRQ occur
|
|
|
|
mov ecx, [devices]
|
|
test ecx, ecx
|
|
jz .nothing
|
|
mov esi, device_list
|
|
.nextdevice:
|
|
mov ebx, [esi]
|
|
mov edx, [ebx + device.io_addr]
|
|
push ecx
|
|
xor ecx, ecx ; CSR0
|
|
call [ebx + device.read_csr] ; get IRQ reason
|
|
call [ebx + device.write_csr] ; write it back to ACK
|
|
pop ecx
|
|
test ax, CSR_RINT or CSR_TINT
|
|
jnz .got_it
|
|
.continue:
|
|
add esi, 4
|
|
dec ecx
|
|
jnz .nextdevice
|
|
.nothing:
|
|
pop edi esi ebx
|
|
xor eax, eax
|
|
|
|
ret
|
|
|
|
.got_it:
|
|
DEBUGF 1,"Device: %x status: %x\n", ebx, eax:4
|
|
|
|
push ax
|
|
test ax, CSR_RINT
|
|
jz .not_receive
|
|
|
|
push ebx
|
|
.rx_loop:
|
|
pop ebx
|
|
push ebx
|
|
mov eax, [ebx + device.cur_rx]
|
|
shl eax, 4
|
|
lea edi, [ebx + device.rx_ring]
|
|
add edi, eax ; edi now points to current rx ring entry
|
|
|
|
mov ax, [edi + descriptor.status]
|
|
DEBUGF 1,"RX packet status: %x\n", eax:4
|
|
|
|
test ax, RXSTAT_OWN ; If this bit is set, the controller OWN's the packet, if not, we do
|
|
jnz .rx_done
|
|
; Both Start of packet and End of packet bits should be set, we dont support multi frame packets
|
|
test ax, RXSTAT_ENP
|
|
jz .rx_drop
|
|
test ax, RXSTAT_STP
|
|
jz .rx_drop
|
|
|
|
movzx ecx, [edi + descriptor.msg_length] ; get packet length in ecx
|
|
sub ecx, 4 ; We dont need the CRC
|
|
DEBUGF 1,"Got %u bytes\n", ecx
|
|
|
|
; Set pointers for ETH_input
|
|
push .rx_loop ; return address
|
|
mov eax, [edi + descriptor.virtual]
|
|
push eax ; packet address
|
|
mov [eax + NET_BUFF.length], ecx
|
|
mov [eax + NET_BUFF.device], ebx
|
|
mov [eax + NET_BUFF.offset], NET_BUFF.data
|
|
|
|
; Update stats
|
|
add dword[ebx + device.bytes_rx], ecx
|
|
adc dword[ebx + device.bytes_rx + 4], 0
|
|
inc [ebx + device.packets_rx]
|
|
|
|
; now allocate a new buffer
|
|
invoke NetAlloc, PKT_BUF_SZ+NET_BUFF.data ; Allocate a buffer for the next packet
|
|
test eax, eax
|
|
jz .rx_overrun
|
|
mov [edi + descriptor.virtual], eax ; set virtual address
|
|
invoke GetPhysAddr
|
|
add eax, NET_BUFF.data
|
|
mov [edi + descriptor.base], eax ; and physical address
|
|
mov [edi + descriptor.status], RXSTAT_OWN ; give it back to PCnet controller
|
|
|
|
inc [ebx + device.cur_rx] ; set next receive descriptor
|
|
and [ebx + device.cur_rx], RX_RING_SIZE - 1
|
|
|
|
jmp [EthInput]
|
|
|
|
.rx_overrun:
|
|
add esp, 4+4
|
|
DEBUGF 2,"RX FIFO overrun\n"
|
|
inc [ebx + device.packets_rx_ovr]
|
|
jmp .rx_next
|
|
|
|
.rx_drop:
|
|
DEBUGF 2,"Dropping incoming packet\n"
|
|
inc [ebx + device.packets_rx_drop]
|
|
|
|
.rx_next:
|
|
mov [edi + descriptor.status], RXSTAT_OWN ; give it back to PCnet controller
|
|
|
|
inc [ebx + device.cur_rx] ; set next receive descriptor
|
|
and [ebx + device.cur_rx], RX_RING_SIZE - 1
|
|
jmp .rx_loop
|
|
|
|
.rx_done:
|
|
pop ebx
|
|
|
|
.not_receive:
|
|
pop ax
|
|
|
|
test ax, CSR_TINT
|
|
jz .not_transmit
|
|
|
|
.tx_loop:
|
|
lea edi, [ebx + device.tx_ring]
|
|
mov eax, [ebx + device.last_tx]
|
|
shl eax, 4
|
|
add edi, eax
|
|
|
|
test [edi + descriptor.status], TXCTL_OWN
|
|
jnz .not_transmit
|
|
|
|
mov eax, [edi + descriptor.virtual]
|
|
test eax, eax
|
|
jz .not_transmit
|
|
|
|
mov [edi + descriptor.virtual], 0
|
|
|
|
DEBUGF 1,"Removing packet %x from memory\n", eax
|
|
|
|
invoke NetFree, eax
|
|
|
|
inc [ebx + device.last_tx]
|
|
and [ebx + device.last_tx], TX_RING_SIZE - 1
|
|
jmp .tx_loop
|
|
|
|
.not_transmit:
|
|
pop edi esi ebx
|
|
xor eax, eax
|
|
inc eax
|
|
|
|
ret
|
|
|
|
|
|
|
|
|
|
;;;;;;;;;;;;;;;;;;;;;;;
|
|
;; ;;
|
|
;; Write MAC address ;;
|
|
;; ;;
|
|
;;;;;;;;;;;;;;;;;;;;;;;
|
|
|
|
align 4
|
|
write_mac: ; in: mac pushed onto stack (as 3 words)
|
|
|
|
DEBUGF 1,"Writing MAC: %x-%x-%x-%x-%x-%x\n",\
|
|
[esp+0]:2,[esp+1]:2,[esp+2]:2,[esp+3]:2,[esp+4]:2,[esp+5]:2
|
|
|
|
mov edx, [ebx + device.io_addr]
|
|
add dx, 2
|
|
xor eax, eax
|
|
|
|
mov ecx, CSR_PAR0
|
|
@@:
|
|
pop ax
|
|
call [ebx + device.write_csr]
|
|
inc ecx
|
|
cmp ecx, CSR_PAR2
|
|
jb @r
|
|
|
|
; Notice this procedure does not ret, but continues to read_mac instead.
|
|
|
|
;;;;;;;;;;;;;;;;;;;;;;
|
|
;; ;;
|
|
;; Read MAC address ;;
|
|
;; ;;
|
|
;;;;;;;;;;;;;;;;;;;;;;
|
|
align 4
|
|
read_mac:
|
|
DEBUGF 1,"Reading MAC\n"
|
|
|
|
mov edx, [ebx + device.io_addr]
|
|
lea edi, [ebx + device.mac]
|
|
in ax, dx
|
|
stosw
|
|
|
|
inc dx
|
|
inc dx
|
|
in ax, dx
|
|
stosw
|
|
|
|
inc dx
|
|
inc dx
|
|
in ax, dx
|
|
stosw
|
|
|
|
DEBUGF 1,"MAC = %x-%x-%x-%x-%x-%x\n",\
|
|
[ebx + device.mac+0]:2,[ebx + device.mac+1]:2,[ebx + device.mac+2]:2,\
|
|
[ebx + device.mac+3]:2,[ebx + device.mac+4]:2,[ebx + device.mac+5]:2
|
|
|
|
ret
|
|
|
|
align 4
|
|
switch_to_wio:
|
|
|
|
DEBUGF 1,"Switching to 16-bit mode\n"
|
|
|
|
mov [ebx + device.read_csr], wio_read_csr
|
|
mov [ebx + device.write_csr], wio_write_csr
|
|
mov [ebx + device.read_bcr], wio_read_bcr
|
|
mov [ebx + device.write_bcr], wio_write_bcr
|
|
mov [ebx + device.read_rap], wio_read_rap
|
|
mov [ebx + device.write_rap], wio_write_rap
|
|
mov [ebx + device.sw_reset], wio_reset
|
|
|
|
ret
|
|
|
|
align 4
|
|
switch_to_dwio:
|
|
|
|
DEBUGF 1,"Switching to 32-bit mode\n"
|
|
|
|
mov [ebx + device.read_csr], dwio_read_csr
|
|
mov [ebx + device.write_csr], dwio_write_csr
|
|
mov [ebx + device.read_bcr], dwio_read_bcr
|
|
mov [ebx + device.write_bcr], dwio_write_bcr
|
|
mov [ebx + device.read_rap], dwio_read_rap
|
|
mov [ebx + device.write_rap], dwio_write_rap
|
|
mov [ebx + device.sw_reset], dwio_reset
|
|
|
|
ret
|
|
|
|
|
|
; ecx - index
|
|
; return:
|
|
; eax - data
|
|
align 4
|
|
wio_read_csr:
|
|
|
|
add edx, WIO_RAP
|
|
mov ax, cx
|
|
out dx, ax
|
|
add edx, WIO_RDP - WIO_RAP
|
|
in ax, dx
|
|
and eax, 0xffff
|
|
sub edx, WIO_RDP
|
|
|
|
ret
|
|
|
|
|
|
; eax - data
|
|
; ecx - index
|
|
align 4
|
|
wio_write_csr:
|
|
|
|
add edx, WIO_RAP
|
|
xchg eax, ecx
|
|
out dx, ax
|
|
xchg eax, ecx
|
|
add edx, WIO_RDP - WIO_RAP
|
|
out dx, ax
|
|
sub edx, WIO_RDP
|
|
|
|
ret
|
|
|
|
|
|
; ecx - index
|
|
; return:
|
|
; eax - data
|
|
align 4
|
|
wio_read_bcr:
|
|
|
|
add edx, WIO_RAP
|
|
mov ax, cx
|
|
out dx, ax
|
|
add edx, WIO_BDP - WIO_RAP
|
|
in ax, dx
|
|
and eax, 0xffff
|
|
sub edx, WIO_BDP
|
|
|
|
ret
|
|
|
|
|
|
; eax - data
|
|
; ecx - index
|
|
align 4
|
|
wio_write_bcr:
|
|
|
|
add edx, WIO_RAP
|
|
xchg eax, ecx
|
|
out dx, ax
|
|
xchg eax, ecx
|
|
add edx, WIO_BDP - WIO_RAP
|
|
out dx, ax
|
|
sub edx, WIO_BDP
|
|
|
|
ret
|
|
|
|
align 4
|
|
wio_read_rap:
|
|
|
|
add edx, WIO_RAP
|
|
in ax, dx
|
|
and eax, 0xffff
|
|
sub edx, WIO_RAP
|
|
|
|
ret
|
|
|
|
; eax - val
|
|
align 4
|
|
wio_write_rap:
|
|
|
|
add edx, WIO_RAP
|
|
out dx, ax
|
|
sub edx, WIO_RAP
|
|
|
|
ret
|
|
|
|
align 4
|
|
wio_reset:
|
|
|
|
push eax
|
|
add edx, WIO_RESET
|
|
in ax, dx
|
|
pop eax
|
|
sub edx, WIO_RESET
|
|
|
|
ret
|
|
|
|
|
|
|
|
; ecx - index
|
|
; return:
|
|
; eax - data
|
|
align 4
|
|
dwio_read_csr:
|
|
|
|
add edx, DWIO_RAP
|
|
mov eax, ecx
|
|
out dx, eax
|
|
add edx, DWIO_RDP - DWIO_RAP
|
|
in eax, dx
|
|
and eax, 0xffff
|
|
sub edx, DWIO_RDP
|
|
|
|
ret
|
|
|
|
|
|
; ecx - index
|
|
; eax - data
|
|
align 4
|
|
dwio_write_csr:
|
|
|
|
add edx, DWIO_RAP
|
|
xchg eax, ecx
|
|
out dx, eax
|
|
add edx, DWIO_RDP - DWIO_RAP
|
|
xchg eax, ecx
|
|
out dx, eax
|
|
sub edx, DWIO_RDP
|
|
|
|
ret
|
|
|
|
; ecx - index
|
|
; return:
|
|
; eax - data
|
|
align 4
|
|
dwio_read_bcr:
|
|
|
|
add edx, DWIO_RAP
|
|
mov eax, ecx
|
|
out dx, eax
|
|
add edx, DWIO_BDP - DWIO_RAP
|
|
in eax, dx
|
|
and eax, 0xffff
|
|
sub edx, DWIO_BDP
|
|
|
|
ret
|
|
|
|
|
|
; ecx - index
|
|
; eax - data
|
|
align 4
|
|
dwio_write_bcr:
|
|
|
|
add edx, DWIO_RAP
|
|
xchg eax, ecx
|
|
out dx, eax
|
|
add edx, DWIO_BDP - DWIO_RAP
|
|
xchg eax, ecx
|
|
out dx, eax
|
|
sub edx, DWIO_BDP
|
|
|
|
ret
|
|
|
|
align 4
|
|
dwio_read_rap:
|
|
|
|
add edx, DWIO_RAP
|
|
in eax, dx
|
|
and eax, 0xffff
|
|
sub edx, DWIO_RAP
|
|
|
|
ret
|
|
|
|
|
|
; eax - val
|
|
align 4
|
|
dwio_write_rap:
|
|
|
|
add edx, DWIO_RAP
|
|
out dx, eax
|
|
sub edx, DWIO_RAP
|
|
|
|
ret
|
|
|
|
align 4
|
|
dwio_reset:
|
|
|
|
push eax
|
|
add edx, DWIO_RESET
|
|
in eax, dx
|
|
pop eax
|
|
sub edx, DWIO_RESET
|
|
|
|
ret
|
|
|
|
|
|
align 4
|
|
mdio_read:
|
|
|
|
and ecx, 0x1f
|
|
mov ax, [ebx + device.phy]
|
|
and ax, 0x1f
|
|
shl ax, 5
|
|
or ax, cx
|
|
|
|
mov ecx, BCR_MIIADDR
|
|
call [ebx + device.write_bcr]
|
|
|
|
mov ecx, BCR_MIIDATA
|
|
call [ebx + device.read_bcr]
|
|
|
|
ret
|
|
|
|
|
|
align 4
|
|
mdio_write:
|
|
|
|
push eax
|
|
and ecx, 0x1f
|
|
mov ax, [ebx + device.phy]
|
|
and ax, 0x1f
|
|
shl ax, 5
|
|
or ax, cx
|
|
|
|
mov ecx, BCR_MIIADDR
|
|
call [ebx + device.write_bcr]
|
|
|
|
pop eax
|
|
mov ecx, BCR_MIIDATA
|
|
call [ebx + device.write_bcr]
|
|
|
|
ret
|
|
|
|
|
|
|
|
|
|
proc check_media_mii stdcall dev:dword
|
|
|
|
spin_lock_irqsave
|
|
|
|
mov ebx, [dev]
|
|
mov edx, [ebx + device.io_addr]
|
|
|
|
mov ecx, MII_BMSR
|
|
call mdio_read
|
|
|
|
mov ecx, MII_BMSR
|
|
call mdio_read
|
|
|
|
mov ecx, eax
|
|
and eax, BMSR_LSTATUS
|
|
shr eax, 2
|
|
cmp eax, [ebx + device.state]
|
|
jne .changed
|
|
|
|
spin_unlock_irqrestore
|
|
ret
|
|
|
|
.changed:
|
|
test eax, eax
|
|
jz .update
|
|
|
|
test ecx, BMSR_ANEGCOMPLETE
|
|
jz .update
|
|
|
|
mov ecx, MII_ADVERTISE
|
|
call mdio_read
|
|
mov esi, eax
|
|
|
|
mov ecx, MII_LPA
|
|
call mdio_read
|
|
and eax, esi
|
|
|
|
test eax, LPA_100FULL
|
|
jz @f
|
|
mov eax, ETH_LINK_SPEED_100M or ETH_LINK_FULL_DUPLEX
|
|
jmp .update
|
|
@@:
|
|
|
|
test eax, LPA_100HALF
|
|
jz @f
|
|
mov eax, ETH_LINK_SPEED_100M
|
|
jmp .update
|
|
@@:
|
|
|
|
test eax, LPA_10FULL
|
|
jz @f
|
|
mov eax, ETH_LINK_SPEED_10M or ETH_LINK_FULL_DUPLEX
|
|
jmp .update
|
|
@@:
|
|
|
|
test eax, LPA_10HALF
|
|
jz @f
|
|
mov eax, ETH_LINK_SPEED_10M
|
|
jmp .update
|
|
@@:
|
|
|
|
mov eax, ETH_LINK_UNKNOWN
|
|
|
|
.update:
|
|
mov [ebx + device.state], eax
|
|
invoke NetLinkChanged
|
|
|
|
|
|
spin_unlock_irqrestore
|
|
ret
|
|
|
|
|
|
endp
|
|
|
|
|
|
; End of code
|
|
|
|
|
|
data fixups
|
|
end data
|
|
|
|
include '../peimport.inc'
|
|
|
|
my_service db 'PCNET32',0 ; max 16 chars include zero
|
|
|
|
device_l2 db "PCnet/PCI 79C970",0
|
|
device_l4 db "PCnet/PCI II 79C970A",0
|
|
device_l5 db "PCnet/FAST 79C971",0
|
|
device_l6 db "PCnet/FAST+ 79C972",0
|
|
device_l7 db "PCnet/FAST III 79C973",0
|
|
device_l8 db "PCnet/Home 79C978",0
|
|
device_l9 db "PCnet/FAST III 79C975",0
|
|
|
|
options_mapping:
|
|
dd PORT_ASEL ; 0 Auto-select
|
|
dd PORT_AUI ; 1 BNC/AUI
|
|
dd PORT_AUI ; 2 AUI/BNC
|
|
dd PORT_ASEL ; 3 not supported
|
|
dd PORT_10BT or PORT_FD ; 4 10baseT-FD
|
|
dd PORT_ASEL ; 5 not supported
|
|
dd PORT_ASEL ; 6 not supported
|
|
dd PORT_ASEL ; 7 not supported
|
|
dd PORT_ASEL ; 8 not supported
|
|
dd PORT_MII ; 9 MII 10baseT
|
|
dd PORT_MII or PORT_FD ; 10 MII 10baseT-FD
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dd PORT_MII ; 11 MII (autosel)
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dd PORT_10BT ; 12 10BaseT
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dd PORT_MII or PORT_100 ; 13 MII 100BaseTx
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dd PORT_MII or PORT_100 or PORT_FD ; 14 MII 100BaseTx-FD
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dd PORT_ASEL ; 15 not supported
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include_debug_strings ; All data wich FDO uses will be included here
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align 4
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devices dd 0
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device_list rd MAX_DEVICES ; This list contains all pointers to device structures the driver is handling
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