forked from KolibriOS/kolibrios
1556 lines
46 KiB
C
1556 lines
46 KiB
C
/*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Rafał Miłecki <zajec5@gmail.com>
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* Alex Deucher <alexdeucher@gmail.com>
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*/
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#include <drm/drmP.h>
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#include "radeon.h"
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#include "avivod.h"
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#include "atom.h"
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#define RADEON_IDLE_LOOP_MS 100
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#define RADEON_RECLOCK_DELAY_MS 200
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#define RADEON_WAIT_VBLANK_TIMEOUT 200
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static const char *radeon_pm_state_type_name[5] = {
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"",
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"Powersave",
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"Battery",
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"Balanced",
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"Performance",
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};
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static void radeon_dynpm_idle_work_handler(struct work_struct *work);
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static int radeon_debugfs_pm_init(struct radeon_device *rdev);
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static bool radeon_pm_in_vbl(struct radeon_device *rdev);
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static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
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static void radeon_pm_update_profile(struct radeon_device *rdev);
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static void radeon_pm_set_clocks(struct radeon_device *rdev);
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int radeon_pm_get_type_index(struct radeon_device *rdev,
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enum radeon_pm_state_type ps_type,
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int instance)
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{
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int i;
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int found_instance = -1;
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for (i = 0; i < rdev->pm.num_power_states; i++) {
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if (rdev->pm.power_state[i].type == ps_type) {
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found_instance++;
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if (found_instance == instance)
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return i;
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}
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}
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/* return default if no match */
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return rdev->pm.default_power_state_index;
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}
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void radeon_pm_acpi_event_handler(struct radeon_device *rdev)
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{
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if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
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mutex_lock(&rdev->pm.mutex);
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if (power_supply_is_system_supplied() > 0)
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rdev->pm.dpm.ac_power = true;
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else
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rdev->pm.dpm.ac_power = false;
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if (rdev->family == CHIP_ARUBA) {
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if (rdev->asic->dpm.enable_bapm)
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radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power);
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}
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mutex_unlock(&rdev->pm.mutex);
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} else if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
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if (rdev->pm.profile == PM_PROFILE_AUTO) {
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mutex_lock(&rdev->pm.mutex);
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radeon_pm_update_profile(rdev);
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radeon_pm_set_clocks(rdev);
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mutex_unlock(&rdev->pm.mutex);
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}
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}
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}
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static void radeon_pm_update_profile(struct radeon_device *rdev)
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{
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switch (rdev->pm.profile) {
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case PM_PROFILE_DEFAULT:
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rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
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break;
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case PM_PROFILE_AUTO:
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if (power_supply_is_system_supplied() > 0) {
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if (rdev->pm.active_crtc_count > 1)
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rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
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else
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rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
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} else {
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if (rdev->pm.active_crtc_count > 1)
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rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
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else
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rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
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}
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break;
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case PM_PROFILE_LOW:
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if (rdev->pm.active_crtc_count > 1)
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rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
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else
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rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
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break;
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case PM_PROFILE_MID:
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if (rdev->pm.active_crtc_count > 1)
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rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
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else
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rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
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break;
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case PM_PROFILE_HIGH:
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if (rdev->pm.active_crtc_count > 1)
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rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
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else
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rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
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break;
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}
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if (rdev->pm.active_crtc_count == 0) {
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rdev->pm.requested_power_state_index =
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rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
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rdev->pm.requested_clock_mode_index =
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rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
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} else {
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rdev->pm.requested_power_state_index =
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rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
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rdev->pm.requested_clock_mode_index =
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rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
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}
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}
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static void radeon_unmap_vram_bos(struct radeon_device *rdev)
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{
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struct radeon_bo *bo, *n;
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if (list_empty(&rdev->gem.objects))
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return;
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list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
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if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
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ttm_bo_unmap_virtual(&bo->tbo);
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}
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}
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static void radeon_sync_with_vblank(struct radeon_device *rdev)
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{
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if (rdev->pm.active_crtcs) {
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rdev->pm.vblank_sync = false;
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// wait_event_timeout(
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// rdev->irq.vblank_queue, rdev->pm.vblank_sync,
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// msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
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}
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}
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static void radeon_set_power_state(struct radeon_device *rdev)
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{
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u32 sclk, mclk;
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bool misc_after = false;
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if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
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(rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
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return;
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if (radeon_gui_idle(rdev)) {
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sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
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clock_info[rdev->pm.requested_clock_mode_index].sclk;
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if (sclk > rdev->pm.default_sclk)
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sclk = rdev->pm.default_sclk;
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/* starting with BTC, there is one state that is used for both
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* MH and SH. Difference is that we always use the high clock index for
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* mclk and vddci.
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*/
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if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&
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(rdev->family >= CHIP_BARTS) &&
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rdev->pm.active_crtc_count &&
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((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) ||
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(rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX)))
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mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
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clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk;
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else
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mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
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clock_info[rdev->pm.requested_clock_mode_index].mclk;
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if (mclk > rdev->pm.default_mclk)
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mclk = rdev->pm.default_mclk;
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/* upvolt before raising clocks, downvolt after lowering clocks */
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if (sclk < rdev->pm.current_sclk)
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misc_after = true;
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radeon_sync_with_vblank(rdev);
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if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
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if (!radeon_pm_in_vbl(rdev))
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return;
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}
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radeon_pm_prepare(rdev);
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if (!misc_after)
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/* voltage, pcie lanes, etc.*/
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radeon_pm_misc(rdev);
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/* set engine clock */
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if (sclk != rdev->pm.current_sclk) {
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radeon_pm_debug_check_in_vbl(rdev, false);
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radeon_set_engine_clock(rdev, sclk);
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radeon_pm_debug_check_in_vbl(rdev, true);
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rdev->pm.current_sclk = sclk;
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DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
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}
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/* set memory clock */
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if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {
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radeon_pm_debug_check_in_vbl(rdev, false);
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radeon_set_memory_clock(rdev, mclk);
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radeon_pm_debug_check_in_vbl(rdev, true);
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rdev->pm.current_mclk = mclk;
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DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
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}
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if (misc_after)
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/* voltage, pcie lanes, etc.*/
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radeon_pm_misc(rdev);
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radeon_pm_finish(rdev);
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rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
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rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
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} else
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DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
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}
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static void radeon_pm_set_clocks(struct radeon_device *rdev)
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{
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int i, r;
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/* no need to take locks, etc. if nothing's going to change */
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if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
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(rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
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return;
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mutex_lock(&rdev->ddev->struct_mutex);
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// down_write(&rdev->pm.mclk_lock);
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mutex_lock(&rdev->ring_lock);
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/* wait for the rings to drain */
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for (i = 0; i < RADEON_NUM_RINGS; i++) {
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struct radeon_ring *ring = &rdev->ring[i];
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if (!ring->ready) {
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continue;
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}
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r = radeon_fence_wait_empty(rdev, i);
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if (r) {
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/* needs a GPU reset dont reset here */
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mutex_unlock(&rdev->ring_lock);
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// up_write(&rdev->pm.mclk_lock);
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mutex_unlock(&rdev->ddev->struct_mutex);
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return;
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}
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}
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radeon_unmap_vram_bos(rdev);
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if (rdev->irq.installed) {
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for (i = 0; i < rdev->num_crtc; i++) {
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if (rdev->pm.active_crtcs & (1 << i)) {
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rdev->pm.req_vblank |= (1 << i);
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// drm_vblank_get(rdev->ddev, i);
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}
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}
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}
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radeon_set_power_state(rdev);
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if (rdev->irq.installed) {
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for (i = 0; i < rdev->num_crtc; i++) {
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if (rdev->pm.req_vblank & (1 << i)) {
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rdev->pm.req_vblank &= ~(1 << i);
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// drm_vblank_put(rdev->ddev, i);
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}
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}
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}
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/* update display watermarks based on new power state */
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radeon_update_bandwidth_info(rdev);
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if (rdev->pm.active_crtc_count)
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radeon_bandwidth_update(rdev);
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rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
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mutex_unlock(&rdev->ring_lock);
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// up_write(&rdev->pm.mclk_lock);
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mutex_unlock(&rdev->ddev->struct_mutex);
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}
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static void radeon_pm_print_states(struct radeon_device *rdev)
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{
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int i, j;
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struct radeon_power_state *power_state;
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struct radeon_pm_clock_info *clock_info;
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DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
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for (i = 0; i < rdev->pm.num_power_states; i++) {
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power_state = &rdev->pm.power_state[i];
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DRM_DEBUG_DRIVER("State %d: %s\n", i,
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radeon_pm_state_type_name[power_state->type]);
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if (i == rdev->pm.default_power_state_index)
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DRM_DEBUG_DRIVER("\tDefault");
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if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
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DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
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if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
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DRM_DEBUG_DRIVER("\tSingle display only\n");
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DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
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for (j = 0; j < power_state->num_clock_modes; j++) {
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clock_info = &(power_state->clock_info[j]);
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if (rdev->flags & RADEON_IS_IGP)
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DRM_DEBUG_DRIVER("\t\t%d e: %d\n",
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j,
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clock_info->sclk * 10);
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else
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DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n",
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j,
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clock_info->sclk * 10,
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clock_info->mclk * 10,
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clock_info->voltage.voltage);
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}
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}
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}
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static ssize_t radeon_get_pm_profile(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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struct drm_device *ddev = dev_get_drvdata(dev);
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struct radeon_device *rdev = ddev->dev_private;
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int cp = rdev->pm.profile;
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return snprintf(buf, PAGE_SIZE, "%s\n",
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(cp == PM_PROFILE_AUTO) ? "auto" :
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(cp == PM_PROFILE_LOW) ? "low" :
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(cp == PM_PROFILE_MID) ? "mid" :
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(cp == PM_PROFILE_HIGH) ? "high" : "default");
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}
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static ssize_t radeon_set_pm_profile(struct device *dev,
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struct device_attribute *attr,
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const char *buf,
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size_t count)
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{
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struct drm_device *ddev = dev_get_drvdata(dev);
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struct radeon_device *rdev = ddev->dev_private;
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/* Can't set profile when the card is off */
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if ((rdev->flags & RADEON_IS_PX) &&
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(ddev->switch_power_state != DRM_SWITCH_POWER_ON))
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return -EINVAL;
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mutex_lock(&rdev->pm.mutex);
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if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
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if (strncmp("default", buf, strlen("default")) == 0)
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rdev->pm.profile = PM_PROFILE_DEFAULT;
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else if (strncmp("auto", buf, strlen("auto")) == 0)
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rdev->pm.profile = PM_PROFILE_AUTO;
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else if (strncmp("low", buf, strlen("low")) == 0)
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rdev->pm.profile = PM_PROFILE_LOW;
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else if (strncmp("mid", buf, strlen("mid")) == 0)
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rdev->pm.profile = PM_PROFILE_MID;
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else if (strncmp("high", buf, strlen("high")) == 0)
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rdev->pm.profile = PM_PROFILE_HIGH;
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else {
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count = -EINVAL;
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goto fail;
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}
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radeon_pm_update_profile(rdev);
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radeon_pm_set_clocks(rdev);
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} else
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count = -EINVAL;
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fail:
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mutex_unlock(&rdev->pm.mutex);
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return count;
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}
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|
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static ssize_t radeon_get_pm_method(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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struct drm_device *ddev = dev_get_drvdata(dev);
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struct radeon_device *rdev = ddev->dev_private;
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int pm = rdev->pm.pm_method;
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return snprintf(buf, PAGE_SIZE, "%s\n",
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(pm == PM_METHOD_DYNPM) ? "dynpm" :
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(pm == PM_METHOD_PROFILE) ? "profile" : "dpm");
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}
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|
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static ssize_t radeon_set_pm_method(struct device *dev,
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struct device_attribute *attr,
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const char *buf,
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size_t count)
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{
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struct drm_device *ddev = dev_get_drvdata(dev);
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struct radeon_device *rdev = ddev->dev_private;
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/* Can't set method when the card is off */
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if ((rdev->flags & RADEON_IS_PX) &&
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(ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
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count = -EINVAL;
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goto fail;
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}
|
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|
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/* we don't support the legacy modes with dpm */
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if (rdev->pm.pm_method == PM_METHOD_DPM) {
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count = -EINVAL;
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goto fail;
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}
|
|
|
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if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
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mutex_lock(&rdev->pm.mutex);
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rdev->pm.pm_method = PM_METHOD_DYNPM;
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rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
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rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
|
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mutex_unlock(&rdev->pm.mutex);
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} else if (strncmp("profile", buf, strlen("profile")) == 0) {
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mutex_lock(&rdev->pm.mutex);
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/* disable dynpm */
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rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
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rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
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rdev->pm.pm_method = PM_METHOD_PROFILE;
|
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mutex_unlock(&rdev->pm.mutex);
|
|
// cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
|
|
} else {
|
|
count = -EINVAL;
|
|
goto fail;
|
|
}
|
|
radeon_pm_compute_clocks(rdev);
|
|
fail:
|
|
return count;
|
|
}
|
|
|
|
static ssize_t radeon_get_dpm_state(struct device *dev,
|
|
struct device_attribute *attr,
|
|
char *buf)
|
|
{
|
|
struct drm_device *ddev = dev_get_drvdata(dev);
|
|
struct radeon_device *rdev = ddev->dev_private;
|
|
enum radeon_pm_state_type pm = rdev->pm.dpm.user_state;
|
|
|
|
return snprintf(buf, PAGE_SIZE, "%s\n",
|
|
(pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
|
|
(pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
|
|
}
|
|
|
|
static ssize_t radeon_set_dpm_state(struct device *dev,
|
|
struct device_attribute *attr,
|
|
const char *buf,
|
|
size_t count)
|
|
{
|
|
struct drm_device *ddev = dev_get_drvdata(dev);
|
|
struct radeon_device *rdev = ddev->dev_private;
|
|
|
|
mutex_lock(&rdev->pm.mutex);
|
|
if (strncmp("battery", buf, strlen("battery")) == 0)
|
|
rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY;
|
|
else if (strncmp("balanced", buf, strlen("balanced")) == 0)
|
|
rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
|
|
else if (strncmp("performance", buf, strlen("performance")) == 0)
|
|
rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE;
|
|
else {
|
|
mutex_unlock(&rdev->pm.mutex);
|
|
count = -EINVAL;
|
|
goto fail;
|
|
}
|
|
mutex_unlock(&rdev->pm.mutex);
|
|
|
|
/* Can't set dpm state when the card is off */
|
|
if (!(rdev->flags & RADEON_IS_PX) ||
|
|
(ddev->switch_power_state == DRM_SWITCH_POWER_ON))
|
|
radeon_pm_compute_clocks(rdev);
|
|
|
|
fail:
|
|
return count;
|
|
}
|
|
|
|
static ssize_t radeon_get_dpm_forced_performance_level(struct device *dev,
|
|
struct device_attribute *attr,
|
|
char *buf)
|
|
{
|
|
struct drm_device *ddev = dev_get_drvdata(dev);
|
|
struct radeon_device *rdev = ddev->dev_private;
|
|
enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
|
|
|
|
if ((rdev->flags & RADEON_IS_PX) &&
|
|
(ddev->switch_power_state != DRM_SWITCH_POWER_ON))
|
|
return snprintf(buf, PAGE_SIZE, "off\n");
|
|
|
|
return snprintf(buf, PAGE_SIZE, "%s\n",
|
|
(level == RADEON_DPM_FORCED_LEVEL_AUTO) ? "auto" :
|
|
(level == RADEON_DPM_FORCED_LEVEL_LOW) ? "low" : "high");
|
|
}
|
|
|
|
static ssize_t radeon_set_dpm_forced_performance_level(struct device *dev,
|
|
struct device_attribute *attr,
|
|
const char *buf,
|
|
size_t count)
|
|
{
|
|
struct drm_device *ddev = dev_get_drvdata(dev);
|
|
struct radeon_device *rdev = ddev->dev_private;
|
|
enum radeon_dpm_forced_level level;
|
|
int ret = 0;
|
|
|
|
/* Can't force performance level when the card is off */
|
|
if ((rdev->flags & RADEON_IS_PX) &&
|
|
(ddev->switch_power_state != DRM_SWITCH_POWER_ON))
|
|
return -EINVAL;
|
|
|
|
mutex_lock(&rdev->pm.mutex);
|
|
if (strncmp("low", buf, strlen("low")) == 0) {
|
|
level = RADEON_DPM_FORCED_LEVEL_LOW;
|
|
} else if (strncmp("high", buf, strlen("high")) == 0) {
|
|
level = RADEON_DPM_FORCED_LEVEL_HIGH;
|
|
} else if (strncmp("auto", buf, strlen("auto")) == 0) {
|
|
level = RADEON_DPM_FORCED_LEVEL_AUTO;
|
|
} else {
|
|
count = -EINVAL;
|
|
goto fail;
|
|
}
|
|
if (rdev->asic->dpm.force_performance_level) {
|
|
if (rdev->pm.dpm.thermal_active) {
|
|
count = -EINVAL;
|
|
goto fail;
|
|
}
|
|
ret = radeon_dpm_force_performance_level(rdev, level);
|
|
if (ret)
|
|
count = -EINVAL;
|
|
}
|
|
fail:
|
|
mutex_unlock(&rdev->pm.mutex);
|
|
|
|
return count;
|
|
}
|
|
|
|
|
|
static ssize_t radeon_hwmon_show_temp(struct device *dev,
|
|
struct device_attribute *attr,
|
|
char *buf)
|
|
{
|
|
struct radeon_device *rdev = dev_get_drvdata(dev);
|
|
struct drm_device *ddev = rdev->ddev;
|
|
int temp;
|
|
|
|
/* Can't get temperature when the card is off */
|
|
if ((rdev->flags & RADEON_IS_PX) &&
|
|
(ddev->switch_power_state != DRM_SWITCH_POWER_ON))
|
|
return -EINVAL;
|
|
|
|
if (rdev->asic->pm.get_temperature)
|
|
temp = radeon_get_temperature(rdev);
|
|
else
|
|
temp = 0;
|
|
|
|
return snprintf(buf, PAGE_SIZE, "%d\n", temp);
|
|
}
|
|
|
|
static ssize_t radeon_hwmon_show_temp_thresh(struct device *dev,
|
|
struct device_attribute *attr,
|
|
char *buf)
|
|
{
|
|
struct radeon_device *rdev = dev_get_drvdata(dev);
|
|
// int hyst = to_sensor_dev_attr(attr)->index;
|
|
int temp;
|
|
|
|
// if (hyst)
|
|
// temp = rdev->pm.dpm.thermal.min_temp;
|
|
// else
|
|
temp = rdev->pm.dpm.thermal.max_temp;
|
|
|
|
return snprintf(buf, PAGE_SIZE, "%d\n", temp);
|
|
}
|
|
|
|
|
|
static struct attribute *hwmon_attributes[] = {
|
|
// &sensor_dev_attr_temp1_input.dev_attr.attr,
|
|
// &sensor_dev_attr_temp1_crit.dev_attr.attr,
|
|
// &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
|
|
NULL
|
|
};
|
|
|
|
|
|
|
|
static int radeon_hwmon_init(struct radeon_device *rdev)
|
|
{
|
|
int err = 0;
|
|
|
|
switch (rdev->pm.int_thermal_type) {
|
|
case THERMAL_TYPE_RV6XX:
|
|
case THERMAL_TYPE_RV770:
|
|
case THERMAL_TYPE_EVERGREEN:
|
|
case THERMAL_TYPE_NI:
|
|
case THERMAL_TYPE_SUMO:
|
|
case THERMAL_TYPE_SI:
|
|
case THERMAL_TYPE_CI:
|
|
case THERMAL_TYPE_KV:
|
|
if (rdev->asic->pm.get_temperature == NULL)
|
|
return err;
|
|
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return err;
|
|
}
|
|
|
|
static void radeon_hwmon_fini(struct radeon_device *rdev)
|
|
{
|
|
// if (rdev->pm.int_hwmon_dev)
|
|
// hwmon_device_unregister(rdev->pm.int_hwmon_dev);
|
|
}
|
|
|
|
static void radeon_dpm_thermal_work_handler(struct work_struct *work)
|
|
{
|
|
struct radeon_device *rdev =
|
|
container_of(work, struct radeon_device,
|
|
pm.dpm.thermal.work);
|
|
/* switch to the thermal state */
|
|
enum radeon_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
|
|
|
|
if (!rdev->pm.dpm_enabled)
|
|
return;
|
|
|
|
if (rdev->asic->pm.get_temperature) {
|
|
int temp = radeon_get_temperature(rdev);
|
|
|
|
if (temp < rdev->pm.dpm.thermal.min_temp)
|
|
/* switch back the user state */
|
|
dpm_state = rdev->pm.dpm.user_state;
|
|
} else {
|
|
if (rdev->pm.dpm.thermal.high_to_low)
|
|
/* switch back the user state */
|
|
dpm_state = rdev->pm.dpm.user_state;
|
|
}
|
|
mutex_lock(&rdev->pm.mutex);
|
|
if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
|
|
rdev->pm.dpm.thermal_active = true;
|
|
else
|
|
rdev->pm.dpm.thermal_active = false;
|
|
rdev->pm.dpm.state = dpm_state;
|
|
mutex_unlock(&rdev->pm.mutex);
|
|
|
|
radeon_pm_compute_clocks(rdev);
|
|
}
|
|
|
|
static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev,
|
|
enum radeon_pm_state_type dpm_state)
|
|
{
|
|
int i;
|
|
struct radeon_ps *ps;
|
|
u32 ui_class;
|
|
bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ?
|
|
true : false;
|
|
|
|
/* check if the vblank period is too short to adjust the mclk */
|
|
if (single_display && rdev->asic->dpm.vblank_too_short) {
|
|
if (radeon_dpm_vblank_too_short(rdev))
|
|
single_display = false;
|
|
}
|
|
|
|
/* certain older asics have a separare 3D performance state,
|
|
* so try that first if the user selected performance
|
|
*/
|
|
if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
|
|
dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
|
|
/* balanced states don't exist at the moment */
|
|
if (dpm_state == POWER_STATE_TYPE_BALANCED)
|
|
dpm_state = POWER_STATE_TYPE_PERFORMANCE;
|
|
|
|
restart_search:
|
|
/* Pick the best power state based on current conditions */
|
|
for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
|
|
ps = &rdev->pm.dpm.ps[i];
|
|
ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
|
|
switch (dpm_state) {
|
|
/* user states */
|
|
case POWER_STATE_TYPE_BATTERY:
|
|
if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
|
|
if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
|
|
if (single_display)
|
|
return ps;
|
|
} else
|
|
return ps;
|
|
}
|
|
break;
|
|
case POWER_STATE_TYPE_BALANCED:
|
|
if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
|
|
if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
|
|
if (single_display)
|
|
return ps;
|
|
} else
|
|
return ps;
|
|
}
|
|
break;
|
|
case POWER_STATE_TYPE_PERFORMANCE:
|
|
if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
|
|
if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
|
|
if (single_display)
|
|
return ps;
|
|
} else
|
|
return ps;
|
|
}
|
|
break;
|
|
/* internal states */
|
|
case POWER_STATE_TYPE_INTERNAL_UVD:
|
|
if (rdev->pm.dpm.uvd_ps)
|
|
return rdev->pm.dpm.uvd_ps;
|
|
else
|
|
break;
|
|
case POWER_STATE_TYPE_INTERNAL_UVD_SD:
|
|
if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
|
|
return ps;
|
|
break;
|
|
case POWER_STATE_TYPE_INTERNAL_UVD_HD:
|
|
if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
|
|
return ps;
|
|
break;
|
|
case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
|
|
if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
|
|
return ps;
|
|
break;
|
|
case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
|
|
if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
|
|
return ps;
|
|
break;
|
|
case POWER_STATE_TYPE_INTERNAL_BOOT:
|
|
return rdev->pm.dpm.boot_ps;
|
|
case POWER_STATE_TYPE_INTERNAL_THERMAL:
|
|
if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
|
|
return ps;
|
|
break;
|
|
case POWER_STATE_TYPE_INTERNAL_ACPI:
|
|
if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
|
|
return ps;
|
|
break;
|
|
case POWER_STATE_TYPE_INTERNAL_ULV:
|
|
if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
|
|
return ps;
|
|
break;
|
|
case POWER_STATE_TYPE_INTERNAL_3DPERF:
|
|
if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
|
|
return ps;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
/* use a fallback state if we didn't match */
|
|
switch (dpm_state) {
|
|
case POWER_STATE_TYPE_INTERNAL_UVD_SD:
|
|
dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
|
|
goto restart_search;
|
|
case POWER_STATE_TYPE_INTERNAL_UVD_HD:
|
|
case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
|
|
case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
|
|
if (rdev->pm.dpm.uvd_ps) {
|
|
return rdev->pm.dpm.uvd_ps;
|
|
} else {
|
|
dpm_state = POWER_STATE_TYPE_PERFORMANCE;
|
|
goto restart_search;
|
|
}
|
|
case POWER_STATE_TYPE_INTERNAL_THERMAL:
|
|
dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
|
|
goto restart_search;
|
|
case POWER_STATE_TYPE_INTERNAL_ACPI:
|
|
dpm_state = POWER_STATE_TYPE_BATTERY;
|
|
goto restart_search;
|
|
case POWER_STATE_TYPE_BATTERY:
|
|
case POWER_STATE_TYPE_BALANCED:
|
|
case POWER_STATE_TYPE_INTERNAL_3DPERF:
|
|
dpm_state = POWER_STATE_TYPE_PERFORMANCE;
|
|
goto restart_search;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return NULL;
|
|
}
|
|
|
|
static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev)
|
|
{
|
|
int i;
|
|
struct radeon_ps *ps;
|
|
enum radeon_pm_state_type dpm_state;
|
|
int ret;
|
|
|
|
/* if dpm init failed */
|
|
if (!rdev->pm.dpm_enabled)
|
|
return;
|
|
|
|
if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) {
|
|
/* add other state override checks here */
|
|
if ((!rdev->pm.dpm.thermal_active) &&
|
|
(!rdev->pm.dpm.uvd_active))
|
|
rdev->pm.dpm.state = rdev->pm.dpm.user_state;
|
|
}
|
|
dpm_state = rdev->pm.dpm.state;
|
|
|
|
ps = radeon_dpm_pick_power_state(rdev, dpm_state);
|
|
if (ps)
|
|
rdev->pm.dpm.requested_ps = ps;
|
|
else
|
|
return;
|
|
|
|
/* no need to reprogram if nothing changed unless we are on BTC+ */
|
|
if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) {
|
|
/* vce just modifies an existing state so force a change */
|
|
if (ps->vce_active != rdev->pm.dpm.vce_active)
|
|
goto force;
|
|
if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) {
|
|
/* for pre-BTC and APUs if the num crtcs changed but state is the same,
|
|
* all we need to do is update the display configuration.
|
|
*/
|
|
if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) {
|
|
/* update display watermarks based on new power state */
|
|
radeon_bandwidth_update(rdev);
|
|
/* update displays */
|
|
radeon_dpm_display_configuration_changed(rdev);
|
|
rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
|
|
rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
|
|
}
|
|
return;
|
|
} else {
|
|
/* for BTC+ if the num crtcs hasn't changed and state is the same,
|
|
* nothing to do, if the num crtcs is > 1 and state is the same,
|
|
* update display configuration.
|
|
*/
|
|
if (rdev->pm.dpm.new_active_crtcs ==
|
|
rdev->pm.dpm.current_active_crtcs) {
|
|
return;
|
|
} else {
|
|
if ((rdev->pm.dpm.current_active_crtc_count > 1) &&
|
|
(rdev->pm.dpm.new_active_crtc_count > 1)) {
|
|
/* update display watermarks based on new power state */
|
|
radeon_bandwidth_update(rdev);
|
|
/* update displays */
|
|
radeon_dpm_display_configuration_changed(rdev);
|
|
rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
|
|
rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
force:
|
|
if (radeon_dpm == 1) {
|
|
printk("switching from power state:\n");
|
|
radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps);
|
|
printk("switching to power state:\n");
|
|
radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps);
|
|
}
|
|
|
|
mutex_lock(&rdev->ddev->struct_mutex);
|
|
// down_write(&rdev->pm.mclk_lock);
|
|
mutex_lock(&rdev->ring_lock);
|
|
|
|
/* update whether vce is active */
|
|
ps->vce_active = rdev->pm.dpm.vce_active;
|
|
|
|
ret = radeon_dpm_pre_set_power_state(rdev);
|
|
if (ret)
|
|
goto done;
|
|
|
|
/* update display watermarks based on new power state */
|
|
radeon_bandwidth_update(rdev);
|
|
/* update displays */
|
|
radeon_dpm_display_configuration_changed(rdev);
|
|
|
|
rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
|
|
rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
|
|
|
|
/* wait for the rings to drain */
|
|
for (i = 0; i < RADEON_NUM_RINGS; i++) {
|
|
struct radeon_ring *ring = &rdev->ring[i];
|
|
if (ring->ready)
|
|
radeon_fence_wait_empty(rdev, i);
|
|
}
|
|
|
|
/* program the new power state */
|
|
radeon_dpm_set_power_state(rdev);
|
|
|
|
/* update current power state */
|
|
rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps;
|
|
|
|
radeon_dpm_post_set_power_state(rdev);
|
|
|
|
if (rdev->asic->dpm.force_performance_level) {
|
|
if (rdev->pm.dpm.thermal_active) {
|
|
enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
|
|
/* force low perf level for thermal */
|
|
radeon_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_LOW);
|
|
/* save the user's level */
|
|
rdev->pm.dpm.forced_level = level;
|
|
} else {
|
|
/* otherwise, user selected level */
|
|
radeon_dpm_force_performance_level(rdev, rdev->pm.dpm.forced_level);
|
|
}
|
|
}
|
|
|
|
done:
|
|
mutex_unlock(&rdev->ring_lock);
|
|
// up_write(&rdev->pm.mclk_lock);
|
|
mutex_unlock(&rdev->ddev->struct_mutex);
|
|
}
|
|
|
|
void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable)
|
|
{
|
|
enum radeon_pm_state_type dpm_state;
|
|
|
|
if (rdev->asic->dpm.powergate_uvd) {
|
|
mutex_lock(&rdev->pm.mutex);
|
|
/* don't powergate anything if we
|
|
have active but pause streams */
|
|
enable |= rdev->pm.dpm.sd > 0;
|
|
enable |= rdev->pm.dpm.hd > 0;
|
|
/* enable/disable UVD */
|
|
radeon_dpm_powergate_uvd(rdev, !enable);
|
|
mutex_unlock(&rdev->pm.mutex);
|
|
} else {
|
|
if (enable) {
|
|
mutex_lock(&rdev->pm.mutex);
|
|
rdev->pm.dpm.uvd_active = true;
|
|
/* disable this for now */
|
|
#if 0
|
|
if ((rdev->pm.dpm.sd == 1) && (rdev->pm.dpm.hd == 0))
|
|
dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_SD;
|
|
else if ((rdev->pm.dpm.sd == 2) && (rdev->pm.dpm.hd == 0))
|
|
dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
|
|
else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 1))
|
|
dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
|
|
else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 2))
|
|
dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD2;
|
|
else
|
|
#endif
|
|
dpm_state = POWER_STATE_TYPE_INTERNAL_UVD;
|
|
rdev->pm.dpm.state = dpm_state;
|
|
mutex_unlock(&rdev->pm.mutex);
|
|
} else {
|
|
mutex_lock(&rdev->pm.mutex);
|
|
rdev->pm.dpm.uvd_active = false;
|
|
mutex_unlock(&rdev->pm.mutex);
|
|
}
|
|
|
|
radeon_pm_compute_clocks(rdev);
|
|
}
|
|
}
|
|
|
|
void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable)
|
|
{
|
|
if (enable) {
|
|
mutex_lock(&rdev->pm.mutex);
|
|
rdev->pm.dpm.vce_active = true;
|
|
/* XXX select vce level based on ring/task */
|
|
rdev->pm.dpm.vce_level = RADEON_VCE_LEVEL_AC_ALL;
|
|
mutex_unlock(&rdev->pm.mutex);
|
|
} else {
|
|
mutex_lock(&rdev->pm.mutex);
|
|
rdev->pm.dpm.vce_active = false;
|
|
mutex_unlock(&rdev->pm.mutex);
|
|
}
|
|
|
|
radeon_pm_compute_clocks(rdev);
|
|
}
|
|
|
|
static void radeon_pm_suspend_old(struct radeon_device *rdev)
|
|
{
|
|
mutex_lock(&rdev->pm.mutex);
|
|
if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
|
|
if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
|
|
rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
|
|
}
|
|
mutex_unlock(&rdev->pm.mutex);
|
|
|
|
}
|
|
|
|
static void radeon_pm_suspend_dpm(struct radeon_device *rdev)
|
|
{
|
|
mutex_lock(&rdev->pm.mutex);
|
|
/* disable dpm */
|
|
radeon_dpm_disable(rdev);
|
|
/* reset the power state */
|
|
rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
|
|
rdev->pm.dpm_enabled = false;
|
|
mutex_unlock(&rdev->pm.mutex);
|
|
}
|
|
|
|
void radeon_pm_suspend(struct radeon_device *rdev)
|
|
{
|
|
if (rdev->pm.pm_method == PM_METHOD_DPM)
|
|
radeon_pm_suspend_dpm(rdev);
|
|
else
|
|
radeon_pm_suspend_old(rdev);
|
|
}
|
|
|
|
static void radeon_pm_resume_old(struct radeon_device *rdev)
|
|
{
|
|
/* set up the default clocks if the MC ucode is loaded */
|
|
if ((rdev->family >= CHIP_BARTS) &&
|
|
(rdev->family <= CHIP_CAYMAN) &&
|
|
rdev->mc_fw) {
|
|
if (rdev->pm.default_vddc)
|
|
radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
|
|
SET_VOLTAGE_TYPE_ASIC_VDDC);
|
|
if (rdev->pm.default_vddci)
|
|
radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
|
|
SET_VOLTAGE_TYPE_ASIC_VDDCI);
|
|
if (rdev->pm.default_sclk)
|
|
radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
|
|
if (rdev->pm.default_mclk)
|
|
radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
|
|
}
|
|
/* asic init will reset the default power state */
|
|
mutex_lock(&rdev->pm.mutex);
|
|
rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
|
|
rdev->pm.current_clock_mode_index = 0;
|
|
rdev->pm.current_sclk = rdev->pm.default_sclk;
|
|
rdev->pm.current_mclk = rdev->pm.default_mclk;
|
|
if (rdev->pm.power_state) {
|
|
rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
|
|
rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
|
|
}
|
|
if (rdev->pm.pm_method == PM_METHOD_DYNPM
|
|
&& rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
|
|
rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
|
|
// schedule_delayed_work(&rdev->pm.dynpm_idle_work,
|
|
// msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
|
|
}
|
|
mutex_unlock(&rdev->pm.mutex);
|
|
radeon_pm_compute_clocks(rdev);
|
|
}
|
|
|
|
static void radeon_pm_resume_dpm(struct radeon_device *rdev)
|
|
{
|
|
int ret;
|
|
|
|
/* asic init will reset to the boot state */
|
|
mutex_lock(&rdev->pm.mutex);
|
|
rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
|
|
radeon_dpm_setup_asic(rdev);
|
|
ret = radeon_dpm_enable(rdev);
|
|
mutex_unlock(&rdev->pm.mutex);
|
|
if (ret)
|
|
goto dpm_resume_fail;
|
|
rdev->pm.dpm_enabled = true;
|
|
return;
|
|
|
|
dpm_resume_fail:
|
|
DRM_ERROR("radeon: dpm resume failed\n");
|
|
if ((rdev->family >= CHIP_BARTS) &&
|
|
(rdev->family <= CHIP_CAYMAN) &&
|
|
rdev->mc_fw) {
|
|
if (rdev->pm.default_vddc)
|
|
radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
|
|
SET_VOLTAGE_TYPE_ASIC_VDDC);
|
|
if (rdev->pm.default_vddci)
|
|
radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
|
|
SET_VOLTAGE_TYPE_ASIC_VDDCI);
|
|
if (rdev->pm.default_sclk)
|
|
radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
|
|
if (rdev->pm.default_mclk)
|
|
radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
|
|
}
|
|
}
|
|
|
|
void radeon_pm_resume(struct radeon_device *rdev)
|
|
{
|
|
if (rdev->pm.pm_method == PM_METHOD_DPM)
|
|
radeon_pm_resume_dpm(rdev);
|
|
else
|
|
radeon_pm_resume_old(rdev);
|
|
}
|
|
|
|
static int radeon_pm_init_old(struct radeon_device *rdev)
|
|
{
|
|
int ret;
|
|
|
|
rdev->pm.profile = PM_PROFILE_DEFAULT;
|
|
rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
|
|
rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
|
|
rdev->pm.dynpm_can_upclock = true;
|
|
rdev->pm.dynpm_can_downclock = true;
|
|
rdev->pm.default_sclk = rdev->clock.default_sclk;
|
|
rdev->pm.default_mclk = rdev->clock.default_mclk;
|
|
rdev->pm.current_sclk = rdev->clock.default_sclk;
|
|
rdev->pm.current_mclk = rdev->clock.default_mclk;
|
|
rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
|
|
|
|
if (rdev->bios) {
|
|
if (rdev->is_atom_bios)
|
|
radeon_atombios_get_power_modes(rdev);
|
|
else
|
|
radeon_combios_get_power_modes(rdev);
|
|
radeon_pm_print_states(rdev);
|
|
radeon_pm_init_profile(rdev);
|
|
/* set up the default clocks if the MC ucode is loaded */
|
|
if ((rdev->family >= CHIP_BARTS) &&
|
|
(rdev->family <= CHIP_CAYMAN) &&
|
|
rdev->mc_fw) {
|
|
if (rdev->pm.default_vddc)
|
|
radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
|
|
SET_VOLTAGE_TYPE_ASIC_VDDC);
|
|
if (rdev->pm.default_vddci)
|
|
radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
|
|
SET_VOLTAGE_TYPE_ASIC_VDDCI);
|
|
if (rdev->pm.default_sclk)
|
|
radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
|
|
if (rdev->pm.default_mclk)
|
|
radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
|
|
}
|
|
}
|
|
|
|
/* set up the internal thermal sensor if applicable */
|
|
ret = radeon_hwmon_init(rdev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
// INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
|
|
|
|
if (rdev->pm.num_power_states > 1) {
|
|
/* where's the best place to put these? */
|
|
|
|
|
|
DRM_INFO("radeon: power management initialized\n");
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void radeon_dpm_print_power_states(struct radeon_device *rdev)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
|
|
printk("== power state %d ==\n", i);
|
|
radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]);
|
|
}
|
|
}
|
|
|
|
static int radeon_pm_init_dpm(struct radeon_device *rdev)
|
|
{
|
|
int ret;
|
|
|
|
/* default to balanced state */
|
|
rdev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
|
|
rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
|
|
rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO;
|
|
rdev->pm.default_sclk = rdev->clock.default_sclk;
|
|
rdev->pm.default_mclk = rdev->clock.default_mclk;
|
|
rdev->pm.current_sclk = rdev->clock.default_sclk;
|
|
rdev->pm.current_mclk = rdev->clock.default_mclk;
|
|
rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
|
|
|
|
if (rdev->bios && rdev->is_atom_bios)
|
|
radeon_atombios_get_power_modes(rdev);
|
|
else
|
|
return -EINVAL;
|
|
|
|
/* set up the internal thermal sensor if applicable */
|
|
ret = radeon_hwmon_init(rdev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler);
|
|
mutex_lock(&rdev->pm.mutex);
|
|
radeon_dpm_init(rdev);
|
|
rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
|
|
if (radeon_dpm == 1)
|
|
radeon_dpm_print_power_states(rdev);
|
|
radeon_dpm_setup_asic(rdev);
|
|
ret = radeon_dpm_enable(rdev);
|
|
mutex_unlock(&rdev->pm.mutex);
|
|
if (ret)
|
|
goto dpm_failed;
|
|
rdev->pm.dpm_enabled = true;
|
|
|
|
DRM_INFO("radeon: dpm initialized\n");
|
|
|
|
return 0;
|
|
|
|
dpm_failed:
|
|
rdev->pm.dpm_enabled = false;
|
|
if ((rdev->family >= CHIP_BARTS) &&
|
|
(rdev->family <= CHIP_CAYMAN) &&
|
|
rdev->mc_fw) {
|
|
if (rdev->pm.default_vddc)
|
|
radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
|
|
SET_VOLTAGE_TYPE_ASIC_VDDC);
|
|
if (rdev->pm.default_vddci)
|
|
radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
|
|
SET_VOLTAGE_TYPE_ASIC_VDDCI);
|
|
if (rdev->pm.default_sclk)
|
|
radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
|
|
if (rdev->pm.default_mclk)
|
|
radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
|
|
}
|
|
DRM_ERROR("radeon: dpm initialization failed\n");
|
|
return ret;
|
|
}
|
|
|
|
int radeon_pm_init(struct radeon_device *rdev)
|
|
{
|
|
/* enable dpm on rv6xx+ */
|
|
switch (rdev->family) {
|
|
case CHIP_RV610:
|
|
case CHIP_RV630:
|
|
case CHIP_RV620:
|
|
case CHIP_RV635:
|
|
case CHIP_RV670:
|
|
case CHIP_RS780:
|
|
case CHIP_RS880:
|
|
case CHIP_RV770:
|
|
/* DPM requires the RLC, RV770+ dGPU requires SMC */
|
|
if (!rdev->rlc_fw)
|
|
rdev->pm.pm_method = PM_METHOD_PROFILE;
|
|
else if ((rdev->family >= CHIP_RV770) &&
|
|
(!(rdev->flags & RADEON_IS_IGP)) &&
|
|
(!rdev->smc_fw))
|
|
rdev->pm.pm_method = PM_METHOD_PROFILE;
|
|
else if (radeon_dpm == 1)
|
|
rdev->pm.pm_method = PM_METHOD_DPM;
|
|
else
|
|
rdev->pm.pm_method = PM_METHOD_PROFILE;
|
|
break;
|
|
case CHIP_RV730:
|
|
case CHIP_RV710:
|
|
case CHIP_RV740:
|
|
case CHIP_CEDAR:
|
|
case CHIP_REDWOOD:
|
|
case CHIP_JUNIPER:
|
|
case CHIP_CYPRESS:
|
|
case CHIP_HEMLOCK:
|
|
case CHIP_PALM:
|
|
case CHIP_SUMO:
|
|
case CHIP_SUMO2:
|
|
case CHIP_BARTS:
|
|
case CHIP_TURKS:
|
|
case CHIP_CAICOS:
|
|
case CHIP_CAYMAN:
|
|
case CHIP_ARUBA:
|
|
case CHIP_TAHITI:
|
|
case CHIP_PITCAIRN:
|
|
case CHIP_VERDE:
|
|
case CHIP_OLAND:
|
|
case CHIP_HAINAN:
|
|
case CHIP_BONAIRE:
|
|
case CHIP_KABINI:
|
|
case CHIP_KAVERI:
|
|
case CHIP_HAWAII:
|
|
case CHIP_MULLINS:
|
|
/* DPM requires the RLC, RV770+ dGPU requires SMC */
|
|
if (!rdev->rlc_fw)
|
|
rdev->pm.pm_method = PM_METHOD_PROFILE;
|
|
else if ((rdev->family >= CHIP_RV770) &&
|
|
(!(rdev->flags & RADEON_IS_IGP)) &&
|
|
(!rdev->smc_fw))
|
|
rdev->pm.pm_method = PM_METHOD_PROFILE;
|
|
else if (radeon_dpm == 0)
|
|
rdev->pm.pm_method = PM_METHOD_PROFILE;
|
|
else
|
|
rdev->pm.pm_method = PM_METHOD_DPM;
|
|
break;
|
|
default:
|
|
/* default to profile method */
|
|
rdev->pm.pm_method = PM_METHOD_PROFILE;
|
|
break;
|
|
}
|
|
|
|
if (rdev->pm.pm_method == PM_METHOD_DPM)
|
|
return radeon_pm_init_dpm(rdev);
|
|
else
|
|
return radeon_pm_init_old(rdev);
|
|
}
|
|
|
|
int radeon_pm_late_init(struct radeon_device *rdev)
|
|
{
|
|
int ret = 0;
|
|
|
|
if (rdev->pm.pm_method == PM_METHOD_DPM) {
|
|
mutex_lock(&rdev->pm.mutex);
|
|
ret = radeon_dpm_late_enable(rdev);
|
|
mutex_unlock(&rdev->pm.mutex);
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
static void radeon_pm_fini_old(struct radeon_device *rdev)
|
|
{
|
|
if (rdev->pm.num_power_states > 1) {
|
|
mutex_lock(&rdev->pm.mutex);
|
|
if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
|
|
rdev->pm.profile = PM_PROFILE_DEFAULT;
|
|
radeon_pm_update_profile(rdev);
|
|
radeon_pm_set_clocks(rdev);
|
|
} else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
|
|
/* reset default clocks */
|
|
rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
|
|
rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
|
|
radeon_pm_set_clocks(rdev);
|
|
}
|
|
mutex_unlock(&rdev->pm.mutex);
|
|
|
|
// cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
|
|
|
|
}
|
|
|
|
radeon_hwmon_fini(rdev);
|
|
kfree(rdev->pm.power_state);
|
|
}
|
|
|
|
static void radeon_pm_fini_dpm(struct radeon_device *rdev)
|
|
{
|
|
if (rdev->pm.num_power_states > 1) {
|
|
mutex_lock(&rdev->pm.mutex);
|
|
radeon_dpm_disable(rdev);
|
|
mutex_unlock(&rdev->pm.mutex);
|
|
}
|
|
radeon_dpm_fini(rdev);
|
|
|
|
radeon_hwmon_fini(rdev);
|
|
kfree(rdev->pm.power_state);
|
|
}
|
|
|
|
void radeon_pm_fini(struct radeon_device *rdev)
|
|
{
|
|
if (rdev->pm.pm_method == PM_METHOD_DPM)
|
|
radeon_pm_fini_dpm(rdev);
|
|
else
|
|
radeon_pm_fini_old(rdev);
|
|
}
|
|
|
|
static void radeon_pm_compute_clocks_old(struct radeon_device *rdev)
|
|
{
|
|
struct drm_device *ddev = rdev->ddev;
|
|
struct drm_crtc *crtc;
|
|
struct radeon_crtc *radeon_crtc;
|
|
|
|
if (rdev->pm.num_power_states < 2)
|
|
return;
|
|
|
|
mutex_lock(&rdev->pm.mutex);
|
|
|
|
rdev->pm.active_crtcs = 0;
|
|
rdev->pm.active_crtc_count = 0;
|
|
if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
|
|
list_for_each_entry(crtc,
|
|
&ddev->mode_config.crtc_list, head) {
|
|
radeon_crtc = to_radeon_crtc(crtc);
|
|
if (radeon_crtc->enabled) {
|
|
rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
|
|
rdev->pm.active_crtc_count++;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
|
|
radeon_pm_update_profile(rdev);
|
|
radeon_pm_set_clocks(rdev);
|
|
} else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
|
|
if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
|
|
if (rdev->pm.active_crtc_count > 1) {
|
|
if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
|
|
// cancel_delayed_work(&rdev->pm.dynpm_idle_work);
|
|
|
|
rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
|
|
rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
|
|
radeon_pm_get_dynpm_state(rdev);
|
|
radeon_pm_set_clocks(rdev);
|
|
|
|
DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
|
|
}
|
|
} else if (rdev->pm.active_crtc_count == 1) {
|
|
/* TODO: Increase clocks if needed for current mode */
|
|
|
|
if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
|
|
rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
|
|
rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
|
|
radeon_pm_get_dynpm_state(rdev);
|
|
radeon_pm_set_clocks(rdev);
|
|
|
|
// schedule_delayed_work(&rdev->pm.dynpm_idle_work,
|
|
// msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
|
|
} else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
|
|
rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
|
|
// schedule_delayed_work(&rdev->pm.dynpm_idle_work,
|
|
// msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
|
|
DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
|
|
}
|
|
} else { /* count == 0 */
|
|
if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
|
|
// cancel_delayed_work(&rdev->pm.dynpm_idle_work);
|
|
|
|
rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
|
|
rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
|
|
radeon_pm_get_dynpm_state(rdev);
|
|
radeon_pm_set_clocks(rdev);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
mutex_unlock(&rdev->pm.mutex);
|
|
}
|
|
|
|
static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev)
|
|
{
|
|
struct drm_device *ddev = rdev->ddev;
|
|
struct drm_crtc *crtc;
|
|
struct radeon_crtc *radeon_crtc;
|
|
|
|
if (!rdev->pm.dpm_enabled)
|
|
return;
|
|
|
|
mutex_lock(&rdev->pm.mutex);
|
|
|
|
/* update active crtc counts */
|
|
rdev->pm.dpm.new_active_crtcs = 0;
|
|
rdev->pm.dpm.new_active_crtc_count = 0;
|
|
if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
|
|
list_for_each_entry(crtc,
|
|
&ddev->mode_config.crtc_list, head) {
|
|
radeon_crtc = to_radeon_crtc(crtc);
|
|
if (crtc->enabled) {
|
|
rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id);
|
|
rdev->pm.dpm.new_active_crtc_count++;
|
|
}
|
|
}
|
|
}
|
|
|
|
/* update battery/ac status */
|
|
if (power_supply_is_system_supplied() > 0)
|
|
rdev->pm.dpm.ac_power = true;
|
|
else
|
|
rdev->pm.dpm.ac_power = false;
|
|
|
|
radeon_dpm_change_power_state_locked(rdev);
|
|
|
|
mutex_unlock(&rdev->pm.mutex);
|
|
|
|
}
|
|
|
|
void radeon_pm_compute_clocks(struct radeon_device *rdev)
|
|
{
|
|
if (rdev->pm.pm_method == PM_METHOD_DPM)
|
|
radeon_pm_compute_clocks_dpm(rdev);
|
|
else
|
|
radeon_pm_compute_clocks_old(rdev);
|
|
}
|
|
|
|
static bool radeon_pm_in_vbl(struct radeon_device *rdev)
|
|
{
|
|
int crtc, vpos, hpos, vbl_status;
|
|
bool in_vbl = true;
|
|
|
|
/* Iterate over all active crtc's. All crtc's must be in vblank,
|
|
* otherwise return in_vbl == false.
|
|
*/
|
|
for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
|
|
if (rdev->pm.active_crtcs & (1 << crtc)) {
|
|
vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, 0, &vpos, &hpos, NULL, NULL);
|
|
if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
|
|
!(vbl_status & DRM_SCANOUTPOS_INVBL))
|
|
in_vbl = false;
|
|
}
|
|
}
|
|
|
|
return in_vbl;
|
|
}
|
|
|
|
static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
|
|
{
|
|
u32 stat_crtc = 0;
|
|
bool in_vbl = radeon_pm_in_vbl(rdev);
|
|
|
|
if (in_vbl == false)
|
|
DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
|
|
finish ? "exit" : "entry");
|
|
return in_vbl;
|
|
}
|
|
|
|
|
|
/*
|
|
* Debugfs info
|
|
*/
|
|
#if defined(CONFIG_DEBUG_FS)
|
|
|
|
static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
|
|
{
|
|
struct drm_info_node *node = (struct drm_info_node *) m->private;
|
|
struct drm_device *dev = node->minor->dev;
|
|
struct radeon_device *rdev = dev->dev_private;
|
|
struct drm_device *ddev = rdev->ddev;
|
|
|
|
if ((rdev->flags & RADEON_IS_PX) &&
|
|
(ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
|
|
seq_printf(m, "PX asic powered off\n");
|
|
} else if (rdev->pm.dpm_enabled) {
|
|
mutex_lock(&rdev->pm.mutex);
|
|
if (rdev->asic->dpm.debugfs_print_current_performance_level)
|
|
radeon_dpm_debugfs_print_current_performance_level(rdev, m);
|
|
else
|
|
seq_printf(m, "Debugfs support not implemented for this asic\n");
|
|
mutex_unlock(&rdev->pm.mutex);
|
|
} else {
|
|
seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
|
|
/* radeon_get_engine_clock is not reliable on APUs so just print the current clock */
|
|
if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP))
|
|
seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk);
|
|
else
|
|
seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
|
|
seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
|
|
if (rdev->asic->pm.get_memory_clock)
|
|
seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
|
|
if (rdev->pm.current_vddc)
|
|
seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
|
|
if (rdev->asic->pm.get_pcie_lanes)
|
|
seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct drm_info_list radeon_pm_info_list[] = {
|
|
{"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
|
|
};
|
|
#endif
|
|
|
|
static int radeon_debugfs_pm_init(struct radeon_device *rdev)
|
|
{
|
|
#if defined(CONFIG_DEBUG_FS)
|
|
return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
|
|
#else
|
|
return 0;
|
|
#endif
|
|
}
|