;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** ;***** Created: 2005-01-11 10:30 ******* Source: ATmega169.xml *********** ;************************************************************************* ;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y ;* ;* Number : AVR000 ;* File Name : "m169def.inc" ;* Title : Register/Bit Definitions for the ATmega169 ;* Date : 2005-01-11 ;* Version : 2.14 ;* Support E-mail : avr@atmel.com ;* Target MCU : ATmega169 ;* ;* DESCRIPTION ;* When including this file in the assembly program file, all I/O register ;* names and I/O register bit names appearing in the data book can be used. ;* In addition, the six registers forming the three data pointers X, Y and ;* Z have been assigned names XL - ZH. Highest RAM address for Internal ;* SRAM is also defined ;* ;* The Register names are represented by their hexadecimal address. ;* ;* The Register Bit names are represented by their bit number (0-7). ;* ;* Please observe the difference in using the bit names with instructions ;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" ;* (skip if bit in register set/cleared). The following example illustrates ;* this: ;* ;* in r16,PORTB ;read PORTB latch ;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) ;* out PORTB,r16 ;output to PORTB ;* ;* in r16,TIFR ;read the Timer Interrupt Flag Register ;* sbrc r16,TOV0 ;test the overflow flag (use bit#) ;* rjmp TOV0_is_set ;jump if set ;* ... ;otherwise do something else ;************************************************************************* #ifndef _M169DEF_INC_ #define _M169DEF_INC_ #pragma partinc 0 ; ***** SPECIFY DEVICE *************************************************** .device ATmega169 #pragma AVRPART ADMIN PART_NAME ATmega169 .equ SIGNATURE_000 = 0x1e .equ SIGNATURE_001 = 0x94 .equ SIGNATURE_002 = 0x05 #pragma AVRPART CORE CORE_VERSION V2E ; ***** I/O REGISTER DEFINITIONS ***************************************** ; NOTE: ; Definitions marked "MEMORY MAPPED"are extended I/O ports ; and cannot be used with IN/OUT instructions .equ LCDDR18 = 0xfe ; MEMORY MAPPED .equ LCDDR17 = 0xfd ; MEMORY MAPPED .equ LCDDR16 = 0xfc ; MEMORY MAPPED .equ LCDDR15 = 0xfb ; MEMORY MAPPED .equ LCDDR13 = 0xf9 ; MEMORY MAPPED .equ LCDDR12 = 0xf8 ; MEMORY MAPPED .equ LCDDR11 = 0xf7 ; MEMORY MAPPED .equ LCDDR10 = 0xf6 ; MEMORY MAPPED .equ LCDDR8 = 0xf4 ; MEMORY MAPPED .equ LCDDR7 = 0xf3 ; MEMORY MAPPED .equ LCDDR6 = 0xf2 ; MEMORY MAPPED .equ LCDDR5 = 0xf1 ; MEMORY MAPPED .equ LCDDR3 = 0xef ; MEMORY MAPPED .equ LCDDR2 = 0xee ; MEMORY MAPPED .equ LCDDR1 = 0xed ; MEMORY MAPPED .equ LCDDR0 = 0xec ; MEMORY MAPPED .equ LCDCCR = 0xe7 ; MEMORY MAPPED .equ LCDFRR = 0xe6 ; MEMORY MAPPED .equ LCDCRB = 0xe5 ; MEMORY MAPPED .equ LCDCRA = 0xe4 ; MEMORY MAPPED .equ UDR = 0xc6 ; MEMORY MAPPED .equ UBRRH = 0xc5 ; MEMORY MAPPED .equ UBRRL = 0xc4 ; MEMORY MAPPED .equ UCSRC = 0xc2 ; MEMORY MAPPED .equ UCSRB = 0xc1 ; MEMORY MAPPED .equ UCSRA = 0xc0 ; MEMORY MAPPED .equ USIDR = 0xba ; MEMORY MAPPED .equ USISR = 0xb9 ; MEMORY MAPPED .equ USICR = 0xb8 ; MEMORY MAPPED .equ ASSR = 0xb6 ; MEMORY MAPPED .equ OCR2A = 0xb3 ; MEMORY MAPPED .equ TCNT2 = 0xb2 ; MEMORY MAPPED .equ TCCR2B = 0xb1 ; MEMORY MAPPED .equ TCCR2A = 0xb0 ; MEMORY MAPPED .equ OCR1BH = 0x8b ; MEMORY MAPPED .equ OCR1BL = 0x8a ; MEMORY MAPPED .equ OCR1AH = 0x89 ; MEMORY MAPPED .equ OCR1AL = 0x88 ; MEMORY MAPPED .equ ICR1H = 0x87 ; MEMORY MAPPED .equ ICR1L = 0x86 ; MEMORY MAPPED .equ TCNT1H = 0x85 ; MEMORY MAPPED .equ TCNT1L = 0x84 ; MEMORY MAPPED .equ TCCR1C = 0x82 ; MEMORY MAPPED .equ TCCR1B = 0x81 ; MEMORY MAPPED .equ TCCR1A = 0x80 ; MEMORY MAPPED .equ DIDR1 = 0x7f ; MEMORY MAPPED .equ DIDR0 = 0x7e ; MEMORY MAPPED .equ ADMUX = 0x7c ; MEMORY MAPPED .equ ADCSRB = 0x7b ; MEMORY MAPPED .equ ADCSRA = 0x7a ; MEMORY MAPPED .equ ADCH = 0x79 ; MEMORY MAPPED .equ ADCL = 0x78 ; MEMORY MAPPED .equ TIMSK2 = 0x70 ; MEMORY MAPPED .equ TIMSK1 = 0x6f ; MEMORY MAPPED .equ TIMSK0 = 0x6e ; MEMORY MAPPED .equ PCMSK1 = 0x6c ; MEMORY MAPPED .equ PCMSK0 = 0x6b ; MEMORY MAPPED .equ EICRA = 0x69 ; MEMORY MAPPED .equ OSCCAL = 0x66 ; MEMORY MAPPED .equ PRR = 0x64 ; MEMORY MAPPED .equ CLKPR = 0x61 ; MEMORY MAPPED .equ WDTCR = 0x60 ; MEMORY MAPPED .equ SREG = 0x3f .equ SPH = 0x3e .equ SPL = 0x3d .equ SPMCSR = 0x37 .equ MCUCR = 0x35 .equ MCUSR = 0x34 .equ SMCR = 0x33 .equ OCDR = 0x31 .equ ACSR = 0x30 .equ SPDR = 0x2e .equ SPSR = 0x2d .equ SPCR = 0x2c .equ GPIOR2 = 0x2b .equ GPIOR1 = 0x2a .equ OCR0A = 0x27 .equ TCNT0 = 0x26 .equ TCCR0A = 0x24 .equ GTCCR = 0x23 .equ EEARH = 0x22 .equ EEARL = 0x21 .equ EEDR = 0x20 .equ EECR = 0x1f .equ GPIOR0 = 0x1e .equ EIMSK = 0x1d .equ EIFR = 0x1c .equ TIFR2 = 0x17 .equ TIFR1 = 0x16 .equ TIFR0 = 0x15 .equ PORTG = 0x14 .equ DDRG = 0x13 .equ PING = 0x12 .equ PORTF = 0x11 .equ DDRF = 0x10 .equ PINF = 0x0f .equ PORTE = 0x0e .equ DDRE = 0x0d .equ PINE = 0x0c .equ PORTD = 0x0b .equ DDRD = 0x0a .equ PIND = 0x09 .equ PORTC = 0x08 .equ DDRC = 0x07 .equ PINC = 0x06 .equ PORTB = 0x05 .equ DDRB = 0x04 .equ PINB = 0x03 .equ PORTA = 0x02 .equ DDRA = 0x01 .equ PINA = 0x00 ; ***** BIT DEFINITIONS ************************************************** ; ***** TIMER_COUNTER_0 ************** ; TCCR0A - Timer/Counter0 Control Register .equ CS00 = 0 ; Clock Select 1 .equ CS01 = 1 ; Clock Select 1 .equ CS02 = 2 ; Clock Select 2 .equ WGM01 = 3 ; Waveform Generation Mode 1 .equ COM0A0 = 4 ; Compare match Output Mode 0 .equ COM0A1 = 5 ; Compare Match Output Mode 1 .equ WGM00 = 6 ; Waveform Generation Mode 0 .equ FOC0A = 7 ; Force Output Compare ; TCNT0 - Timer/Counter0 .equ TCNT0_0 = 0 ; .equ TCNT0_1 = 1 ; .equ TCNT0_2 = 2 ; .equ TCNT0_3 = 3 ; .equ TCNT0_4 = 4 ; .equ TCNT0_5 = 5 ; .equ TCNT0_6 = 6 ; .equ TCNT0_7 = 7 ; ; OCR0A - Timer/Counter0 Output Compare Register .equ OCR0A0 = 0 ; .equ OCR0A1 = 1 ; .equ OCR0A2 = 2 ; .equ OCR0A3 = 3 ; .equ OCR0A4 = 4 ; .equ OCR0A5 = 5 ; .equ OCR0A6 = 6 ; .equ OCR0A7 = 7 ; ; TIMSK0 - Timer/Counter0 Interrupt Mask Register .equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable .equ OCIE0A = 1 ; Timer/Counter0 Output Compare Match Interrupt Enable ; TIFR0 - Timer/Counter0 Interrupt Flag register .equ TOV0 = 0 ; Timer/Counter0 Overflow Flag .equ OCF0A = 1 ; Timer/Counter0 Output Compare Flag 0 ; GTCCR - General Timer/Control Register .equ PSR310 = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0 .equ PSR10 = PSR310 ; For compatibility .equ PSR0 = PSR310 ; For compatibility .equ PSR1 = PSR310 ; For compatibility .equ PSR3 = PSR310 ; For compatibility .equ TSM = 7 ; Timer/Counter Synchronization Mode ; ***** TIMER_COUNTER_1 ************** ; TIMSK1 - Timer/Counter1 Interrupt Mask Register .equ TOIE1 = 0 ; Timer/Counter1 Overflow Interrupt Enable .equ OCIE1A = 1 ; Timer/Counter1 Output Compare A Match Interrupt Enable .equ OCIE1B = 2 ; Timer/Counter1 Output Compare B Match Interrupt Enable .equ ICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable ; TIFR1 - Timer/Counter1 Interrupt Flag register .equ TOV1 = 0 ; Timer/Counter1 Overflow Flag .equ OCF1A = 1 ; Output Compare Flag 1A .equ OCF1B = 2 ; Output Compare Flag 1B .equ ICF1 = 5 ; Input Capture Flag 1 ; TCCR1A - Timer/Counter1 Control Register A .equ WGM10 = 0 ; Waveform Generation Mode .equ WGM11 = 1 ; Waveform Generation Mode .equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0 .equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 .equ COM1A0 = 6 ; Compare Output Mode 1A, bit 0 .equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 ; TCCR1B - Timer/Counter1 Control Register B .equ CS10 = 0 ; Prescaler source of Timer/Counter 1 .equ CS11 = 1 ; Prescaler source of Timer/Counter 1 .equ CS12 = 2 ; Prescaler source of Timer/Counter 1 .equ WGM12 = 3 ; Waveform Generation Mode .equ WGM13 = 4 ; Waveform Generation Mode .equ ICES1 = 6 ; Input Capture 1 Edge Select .equ ICNC1 = 7 ; Input Capture 1 Noise Canceler ; TCCR1C - Timer/Counter 1 Control Register C .equ FOC1B = 6 ; Force Output Compare 1B .equ FOC1A = 7 ; Force Output Compare 1A ; ***** TIMER_COUNTER_2 ************** ; TIMSK2 - Timer/Counter2 Interrupt Mask register .equ TOIE2 = 0 ; Timer/Counter2 Overflow Interrupt Enable .equ OCIE2A = 1 ; Timer/Counter2 Output Compare Match Interrupt Enable ; TIFR2 - Timer/Counter2 Interrupt Flag Register .equ TOV2 = 0 ; Timer/Counter2 Overflow Flag .equ OCF2A = 1 ; Timer/Counter2 Output Compare Flag 2 ; TCCR2A - Timer/Counter2 Control Register .equ CS20 = 0 ; Clock Select bit 0 .equ CS21 = 1 ; Clock Select bit 1 .equ CS22 = 2 ; Clock Select bit 2 .equ WGM21 = 3 ; Waveform Generation Mode .equ COM2A0 = 4 ; Compare Output Mode bit 0 .equ COM2A1 = 5 ; Compare Output Mode bit 1 .equ WGM20 = 6 ; Waveform Generation Mode .equ FOC2A = 7 ; Force Output Compare A ; TCNT2 - Timer/Counter2 .equ TCNT2_0 = 0 ; Timer/Counter 2 bit 0 .equ TCNT2_1 = 1 ; Timer/Counter 2 bit 1 .equ TCNT2_2 = 2 ; Timer/Counter 2 bit 2 .equ TCNT2_3 = 3 ; Timer/Counter 2 bit 3 .equ TCNT2_4 = 4 ; Timer/Counter 2 bit 4 .equ TCNT2_5 = 5 ; Timer/Counter 2 bit 5 .equ TCNT2_6 = 6 ; Timer/Counter 2 bit 6 .equ TCNT2_7 = 7 ; Timer/Counter 2 bit 7 ; OCR2A - Timer/Counter2 Output Compare Register .equ OCR2A0 = 0 ; Timer/Counter2 Output Compare Register Bit 0 .equ OCR2A1 = 1 ; Timer/Counter2 Output Compare Register Bit 1 .equ OCR2A2 = 2 ; Timer/Counter2 Output Compare Register Bit 2 .equ OCR2A3 = 3 ; Timer/Counter2 Output Compare Register Bit 3 .equ OCR2A4 = 4 ; Timer/Counter2 Output Compare Register Bit 4 .equ OCR2A5 = 5 ; Timer/Counter2 Output Compare Register Bit 5 .equ OCR2A6 = 6 ; Timer/Counter2 Output Compare Register Bit 6 .equ OCR2A7 = 7 ; Timer/Counter2 Output Compare Register Bit 7 ; GTCCR - General Timer/Counter Control Register .equ PSR2 = 1 ; Prescaler Reset Timer/Counter2 ; ASSR - Asynchronous Status Register .equ TCR2UB = 0 ; TCR2UB: Timer/Counter Control Register2 Update Busy .equ OCR2UB = 1 ; Output Compare Register2 Update Busy .equ TCN2UB = 2 ; TCN2UB: Timer/Counter2 Update Busy .equ AS2 = 3 ; AS2: Asynchronous Timer/Counter2 .equ EXCLK = 4 ; Enable External Clock Interrupt ; ***** WATCHDOG ********************* ; WDTCR - Watchdog Timer Control Register .equ WDTCSR = WDTCR ; For compatibility .equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 .equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 .equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 .equ WDE = 3 ; Watch Dog Enable .equ WDCE = 4 ; Watchdog Change Enable .equ WDTOE = WDCE ; For compatibility ; ***** EEPROM *********************** ; EEDR - EEPROM Data Register .equ EEDR0 = 0 ; EEPROM Data Register bit 0 .equ EEDR1 = 1 ; EEPROM Data Register bit 1 .equ EEDR2 = 2 ; EEPROM Data Register bit 2 .equ EEDR3 = 3 ; EEPROM Data Register bit 3 .equ EEDR4 = 4 ; EEPROM Data Register bit 4 .equ EEDR5 = 5 ; EEPROM Data Register bit 5 .equ EEDR6 = 6 ; EEPROM Data Register bit 6 .equ EEDR7 = 7 ; EEPROM Data Register bit 7 ; EECR - EEPROM Control Register .equ EERE = 0 ; EEPROM Read Enable .equ EEWE = 1 ; EEPROM Write Enable .equ EEMWE = 2 ; EEPROM Master Write Enable .equ EEWEE = EEMWE ; For compatibility .equ EERIE = 3 ; EEPROM Ready Interrupt Enable ; ***** SPI ************************** ; SPDR - SPI Data Register .equ SPDR0 = 0 ; SPI Data Register bit 0 .equ SPDR1 = 1 ; SPI Data Register bit 1 .equ SPDR2 = 2 ; SPI Data Register bit 2 .equ SPDR3 = 3 ; SPI Data Register bit 3 .equ SPDR4 = 4 ; SPI Data Register bit 4 .equ SPDR5 = 5 ; SPI Data Register bit 5 .equ SPDR6 = 6 ; SPI Data Register bit 6 .equ SPDR7 = 7 ; SPI Data Register bit 7 ; SPSR - SPI Status Register .equ SPI2X = 0 ; Double SPI Speed Bit .equ WCOL = 6 ; Write Collision Flag .equ SPIF = 7 ; SPI Interrupt Flag ; SPCR - SPI Control Register .equ SPR0 = 0 ; SPI Clock Rate Select 0 .equ SPR1 = 1 ; SPI Clock Rate Select 1 .equ CPHA = 2 ; Clock Phase .equ CPOL = 3 ; Clock polarity .equ MSTR = 4 ; Master/Slave Select .equ DORD = 5 ; Data Order .equ SPE = 6 ; SPI Enable .equ SPIE = 7 ; SPI Interrupt Enable ; ***** PORTA ************************ ; PORTA - Port A Data Register .equ PORTA0 = 0 ; Port A Data Register bit 0 .equ PA0 = 0 ; For compatibility .equ PORTA1 = 1 ; Port A Data Register bit 1 .equ PA1 = 1 ; For compatibility .equ PORTA2 = 2 ; Port A Data Register bit 2 .equ PA2 = 2 ; For compatibility .equ PORTA3 = 3 ; Port A Data Register bit 3 .equ PA3 = 3 ; For compatibility .equ PORTA4 = 4 ; Port A Data Register bit 4 .equ PA4 = 4 ; For compatibility .equ PORTA5 = 5 ; Port A Data Register bit 5 .equ PA5 = 5 ; For compatibility .equ PORTA6 = 6 ; Port A Data Register bit 6 .equ PA6 = 6 ; For compatibility .equ PORTA7 = 7 ; Port A Data Register bit 7 .equ PA7 = 7 ; For compatibility ; DDRA - Port A Data Direction Register .equ DDA0 = 0 ; Data Direction Register, Port A, bit 0 .equ DDA1 = 1 ; Data Direction Register, Port A, bit 1 .equ DDA2 = 2 ; Data Direction Register, Port A, bit 2 .equ DDA3 = 3 ; Data Direction Register, Port A, bit 3 .equ DDA4 = 4 ; Data Direction Register, Port A, bit 4 .equ DDA5 = 5 ; Data Direction Register, Port A, bit 5 .equ DDA6 = 6 ; Data Direction Register, Port A, bit 6 .equ DDA7 = 7 ; Data Direction Register, Port A, bit 7 ; PINA - Port A Input Pins .equ PINA0 = 0 ; Input Pins, Port A bit 0 .equ PINA1 = 1 ; Input Pins, Port A bit 1 .equ PINA2 = 2 ; Input Pins, Port A bit 2 .equ PINA3 = 3 ; Input Pins, Port A bit 3 .equ PINA4 = 4 ; Input Pins, Port A bit 4 .equ PINA5 = 5 ; Input Pins, Port A bit 5 .equ PINA6 = 6 ; Input Pins, Port A bit 6 .equ PINA7 = 7 ; Input Pins, Port A bit 7 ; ***** PORTB ************************ ; PORTB - Port B Data Register .equ PORTB0 = 0 ; Port B Data Register bit 0 .equ PB0 = 0 ; For compatibility .equ PORTB1 = 1 ; Port B Data Register bit 1 .equ PB1 = 1 ; For compatibility .equ PORTB2 = 2 ; Port B Data Register bit 2 .equ PB2 = 2 ; For compatibility .equ PORTB3 = 3 ; Port B Data Register bit 3 .equ PB3 = 3 ; For compatibility .equ PORTB4 = 4 ; Port B Data Register bit 4 .equ PB4 = 4 ; For compatibility .equ PORTB5 = 5 ; Port B Data Register bit 5 .equ PB5 = 5 ; For compatibility .equ PORTB6 = 6 ; Port B Data Register bit 6 .equ PB6 = 6 ; For compatibility .equ PORTB7 = 7 ; Port B Data Register bit 7 .equ PB7 = 7 ; For compatibility ; DDRB - Port B Data Direction Register .equ DDB0 = 0 ; Port B Data Direction Register bit 0 .equ DDB1 = 1 ; Port B Data Direction Register bit 1 .equ DDB2 = 2 ; Port B Data Direction Register bit 2 .equ DDB3 = 3 ; Port B Data Direction Register bit 3 .equ DDB4 = 4 ; Port B Data Direction Register bit 4 .equ DDB5 = 5 ; Port B Data Direction Register bit 5 .equ DDB6 = 6 ; Port B Data Direction Register bit 6 .equ DDB7 = 7 ; Port B Data Direction Register bit 7 ; PINB - Port B Input Pins .equ PINB0 = 0 ; Port B Input Pins bit 0 .equ PINB1 = 1 ; Port B Input Pins bit 1 .equ PINB2 = 2 ; Port B Input Pins bit 2 .equ PINB3 = 3 ; Port B Input Pins bit 3 .equ PINB4 = 4 ; Port B Input Pins bit 4 .equ PINB5 = 5 ; Port B Input Pins bit 5 .equ PINB6 = 6 ; Port B Input Pins bit 6 .equ PINB7 = 7 ; Port B Input Pins bit 7 ; ***** PORTC ************************ ; PORTC - Port C Data Register .equ PORTC0 = 0 ; Port C Data Register bit 0 .equ PC0 = 0 ; For compatibility .equ PORTC1 = 1 ; Port C Data Register bit 1 .equ PC1 = 1 ; For compatibility .equ PORTC2 = 2 ; Port C Data Register bit 2 .equ PC2 = 2 ; For compatibility .equ PORTC3 = 3 ; Port C Data Register bit 3 .equ PC3 = 3 ; For compatibility .equ PORTC4 = 4 ; Port C Data Register bit 4 .equ PC4 = 4 ; For compatibility .equ PORTC5 = 5 ; Port C Data Register bit 5 .equ PC5 = 5 ; For compatibility .equ PORTC6 = 6 ; Port C Data Register bit 6 .equ PC6 = 6 ; For compatibility .equ PORTC7 = 7 ; Port C Data Register bit 7 .equ PC7 = 7 ; For compatibility ; DDRC - Port C Data Direction Register .equ DDC0 = 0 ; Port C Data Direction Register bit 0 .equ DDC1 = 1 ; Port C Data Direction Register bit 1 .equ DDC2 = 2 ; Port C Data Direction Register bit 2 .equ DDC3 = 3 ; Port C Data Direction Register bit 3 .equ DDC4 = 4 ; Port C Data Direction Register bit 4 .equ DDC5 = 5 ; Port C Data Direction Register bit 5 .equ DDC6 = 6 ; Port C Data Direction Register bit 6 .equ DDC7 = 7 ; Port C Data Direction Register bit 7 ; PINC - Port C Input Pins .equ PINC0 = 0 ; Port C Input Pins bit 0 .equ PINC1 = 1 ; Port C Input Pins bit 1 .equ PINC2 = 2 ; Port C Input Pins bit 2 .equ PINC3 = 3 ; Port C Input Pins bit 3 .equ PINC4 = 4 ; Port C Input Pins bit 4 .equ PINC5 = 5 ; Port C Input Pins bit 5 .equ PINC6 = 6 ; Port C Input Pins bit 6 .equ PINC7 = 7 ; Port C Input Pins bit 7 ; ***** PORTD ************************ ; PORTD - Port D Data Register .equ PORTD0 = 0 ; Port D Data Register bit 0 .equ PD0 = 0 ; For compatibility .equ PORTD1 = 1 ; Port D Data Register bit 1 .equ PD1 = 1 ; For compatibility .equ PORTD2 = 2 ; Port D Data Register bit 2 .equ PD2 = 2 ; For compatibility .equ PORTD3 = 3 ; Port D Data Register bit 3 .equ PD3 = 3 ; For compatibility .equ PORTD4 = 4 ; Port D Data Register bit 4 .equ PD4 = 4 ; For compatibility .equ PORTD5 = 5 ; Port D Data Register bit 5 .equ PD5 = 5 ; For compatibility .equ PORTD6 = 6 ; Port D Data Register bit 6 .equ PD6 = 6 ; For compatibility .equ PORTD7 = 7 ; Port D Data Register bit 7 .equ PD7 = 7 ; For compatibility ; DDRD - Port D Data Direction Register .equ DDD0 = 0 ; Port D Data Direction Register bit 0 .equ DDD1 = 1 ; Port D Data Direction Register bit 1 .equ DDD2 = 2 ; Port D Data Direction Register bit 2 .equ DDD3 = 3 ; Port D Data Direction Register bit 3 .equ DDD4 = 4 ; Port D Data Direction Register bit 4 .equ DDD5 = 5 ; Port D Data Direction Register bit 5 .equ DDD6 = 6 ; Port D Data Direction Register bit 6 .equ DDD7 = 7 ; Port D Data Direction Register bit 7 ; PIND - Port D Input Pins .equ PIND0 = 0 ; Port D Input Pins bit 0 .equ PIND1 = 1 ; Port D Input Pins bit 1 .equ PIND2 = 2 ; Port D Input Pins bit 2 .equ PIND3 = 3 ; Port D Input Pins bit 3 .equ PIND4 = 4 ; Port D Input Pins bit 4 .equ PIND5 = 5 ; Port D Input Pins bit 5 .equ PIND6 = 6 ; Port D Input Pins bit 6 .equ PIND7 = 7 ; Port D Input Pins bit 7 ; ***** ANALOG_COMPARATOR ************ ; ADCSRB - ADC Control and Status Register B .equ ACME = 6 ; Analog Comparator Multiplexer Enable ; ACSR - Analog Comparator Control And Status Register .equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 .equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 .equ ACIC = 2 ; Analog Comparator Input Capture Enable .equ ACIE = 3 ; Analog Comparator Interrupt Enable .equ ACI = 4 ; Analog Comparator Interrupt Flag .equ ACO = 5 ; Analog Compare Output .equ ACBG = 6 ; Analog Comparator Bandgap Select .equ ACD = 7 ; Analog Comparator Disable ; DIDR1 - Digital Input Disable Register 1 .equ AIN0D = 0 ; AIN0 Digital Input Disable .equ AIN1D = 1 ; AIN1 Digital Input Disable ; ***** PORTE ************************ ; PORTE - Data Register, Port E .equ PORTE0 = 0 ; .equ PE0 = 0 ; For compatibility .equ PORTE1 = 1 ; .equ PE1 = 1 ; For compatibility .equ PORTE2 = 2 ; .equ PE2 = 2 ; For compatibility .equ PORTE3 = 3 ; .equ PE3 = 3 ; For compatibility .equ PORTE4 = 4 ; .equ PE4 = 4 ; For compatibility .equ PORTE5 = 5 ; .equ PE5 = 5 ; For compatibility .equ PORTE6 = 6 ; .equ PE6 = 6 ; For compatibility .equ PORTE7 = 7 ; .equ PE7 = 7 ; For compatibility ; DDRE - Data Direction Register, Port E .equ DDE0 = 0 ; .equ DDE1 = 1 ; .equ DDE2 = 2 ; .equ DDE3 = 3 ; .equ DDE4 = 4 ; .equ DDE5 = 5 ; .equ DDE6 = 6 ; .equ DDE7 = 7 ; ; PINE - Input Pins, Port E .equ PINE0 = 0 ; .equ PINE1 = 1 ; .equ PINE2 = 2 ; .equ PINE3 = 3 ; .equ PINE4 = 4 ; .equ PINE5 = 5 ; .equ PINE6 = 6 ; .equ PINE7 = 7 ; ; ***** PORTF ************************ ; PORTF - Data Register, Port F .equ PORTF0 = 0 ; .equ PF0 = 0 ; For compatibility .equ PORTF1 = 1 ; .equ PF1 = 1 ; For compatibility .equ PORTF2 = 2 ; .equ PF2 = 2 ; For compatibility .equ PORTF3 = 3 ; .equ PF3 = 3 ; For compatibility .equ PORTF4 = 4 ; .equ PF4 = 4 ; For compatibility .equ PORTF5 = 5 ; .equ PF5 = 5 ; For compatibility .equ PORTF6 = 6 ; .equ PF6 = 6 ; For compatibility .equ PORTF7 = 7 ; .equ PF7 = 7 ; For compatibility ; DDRF - Data Direction Register, Port F .equ DDF0 = 0 ; .equ DDF1 = 1 ; .equ DDF2 = 2 ; .equ DDF3 = 3 ; .equ DDF4 = 4 ; .equ DDF5 = 5 ; .equ DDF6 = 6 ; .equ DDF7 = 7 ; ; PINF - Input Pins, Port F .equ PINF0 = 0 ; .equ PINF1 = 1 ; .equ PINF2 = 2 ; .equ PINF3 = 3 ; .equ PINF4 = 4 ; .equ PINF5 = 5 ; .equ PINF6 = 6 ; .equ PINF7 = 7 ; ; ***** PORTG ************************ ; PORTG - Port G Data Register .equ PORTG0 = 0 ; .equ PG0 = 0 ; For compatibility .equ PORTG1 = 1 ; .equ PG1 = 1 ; For compatibility .equ PORTG2 = 2 ; .equ PG2 = 2 ; For compatibility .equ PORTG3 = 3 ; .equ PG3 = 3 ; For compatibility .equ PORTG4 = 4 ; .equ PG4 = 4 ; For compatibility ; DDRG - Port G Data Direction Register .equ DDG0 = 0 ; .equ DDG1 = 1 ; .equ DDG2 = 2 ; .equ DDG3 = 3 ; .equ DDG4 = 4 ; ; PING - Port G Input Pins .equ PING0 = 0 ; .equ PING1 = 1 ; .equ PING2 = 2 ; .equ PING3 = 3 ; .equ PING4 = 4 ; .equ PING5 = 5 ; ; ***** JTAG ************************* ; OCDR - On-Chip Debug Related Register in I/O Memory .equ OCDR0 = 0 ; On-Chip Debug Register Bit 0 .equ OCDR1 = 1 ; On-Chip Debug Register Bit 1 .equ OCDR2 = 2 ; On-Chip Debug Register Bit 2 .equ OCDR3 = 3 ; On-Chip Debug Register Bit 3 .equ OCDR4 = 4 ; On-Chip Debug Register Bit 4 .equ OCDR5 = 5 ; On-Chip Debug Register Bit 5 .equ OCDR6 = 6 ; On-Chip Debug Register Bit 6 .equ OCDR7 = 7 ; On-Chip Debug Register Bit 7 .equ IDRD = OCDR7 ; For compatibility ; MCUCR - MCU Control Register .equ JTD = 7 ; JTAG Interface Disable ; MCUSR - MCU Status Register .equ JTRF = 4 ; JTAG Reset Flag ; ***** MISC ************************* ; LCDCRA - LCD Control Register A .equ LCDBL = 0 ; LCD Blanking .equ LCDIE = 3 ; LCD Interrupt Enable .equ LCDIF = 4 ; LCD Interrupt Flag .equ LCDAB = 6 ; LCD A or B waveform .equ LCDEN = 7 ; LCD Enable ; LCDCRB - LCD Control and Status Register B .equ LCDPM0 = 0 ; LCD Port Mask 0 .equ LCDPM1 = 1 ; LCD Port Mask 1 .equ LCDPM2 = 2 ; LCD Port Mask 2 .equ LCDMUX0 = 4 ; LCD Mux Select 0 .equ LCDMUX1 = 5 ; LCD Mux Select 1 .equ LCD2B = 6 ; LCD 1/2 Bias Select .equ LCDCS = 7 ; LCD CLock Select ; LCDFRR - LCD Frame Rate Register .equ LCDCD0 = 0 ; LCD Clock Divider 0 .equ LCDCD1 = 1 ; LCD Clock Divider 1 .equ LCDCD2 = 2 ; LCD Clock Divider 2 .equ LCDPS0 = 4 ; LCD Prescaler Select 0 .equ LCDPS1 = 5 ; LCD Prescaler Select 1 .equ LCDPS2 = 6 ; LCD Prescaler Select 2 ; LCDCCR - LCD Contrast Control Register .equ LCDCC0 = 0 ; LCD Contrast Control 0 .equ LCDCC1 = 1 ; LCD Contrast Control 1 .equ LCDCC2 = 2 ; LCD Contrast Control 2 .equ LCDCC3 = 3 ; LCD Contrast Control 3 .equ LCDDC0 = 5 ; LCD Display Configuration Bit 0 .equ LCDDC1 = 6 ; LCD Display Configuration Bit 1 .equ LCDDC2 = 7 ; LCD Display Configuration Bit 2 ; LCDDR18 - LCD Data Register 18 .equ SEG324 = 0 ; ; LCDDR17 - LCD Data Register 17 .equ SEG316 = 0 ; .equ SEG317 = 1 ; .equ SEG318 = 2 ; .equ SEG319 = 3 ; .equ SEG320 = 4 ; .equ SEG321 = 5 ; .equ SEG322 = 6 ; .equ SEG323 = 7 ; ; LCDDR16 - LCD Data Register 16 .equ SEG308 = 0 ; .equ SEG309 = 1 ; .equ SEG310 = 2 ; .equ SEG311 = 3 ; .equ SEG312 = 4 ; .equ SEG313 = 5 ; .equ SEG314 = 6 ; .equ SEG315 = 7 ; ; LCDDR15 - LCD Data Register 15 .equ SEG300 = 0 ; .equ SEG301 = 1 ; .equ SEG302 = 2 ; .equ SEG303 = 3 ; .equ SEG304 = 4 ; .equ SEG305 = 5 ; .equ SEG306 = 6 ; .equ SEG307 = 7 ; ; LCDDR13 - LCD Data Register 13 .equ SEG224 = 0 ; ; LCDDR12 - LCD Data Register 12 .equ SEG216 = 0 ; .equ SEG217 = 1 ; .equ SEG218 = 2 ; .equ SEG219 = 3 ; .equ SEG220 = 4 ; .equ SEG221 = 5 ; .equ SEG222 = 6 ; .equ SEG223 = 7 ; ; LCDDR11 - LCD Data Register 11 .equ SEG208 = 0 ; .equ SEG209 = 1 ; .equ SEG210 = 2 ; .equ SEG211 = 3 ; .equ SEG212 = 4 ; .equ SEG213 = 5 ; .equ SEG214 = 6 ; .equ SEG215 = 7 ; ; LCDDR10 - LCD Data Register 10 .equ SEG200 = 0 ; .equ SEG201 = 1 ; .equ SEG202 = 2 ; .equ SEG203 = 3 ; .equ SEG204 = 4 ; .equ SEG205 = 5 ; .equ SEG206 = 6 ; .equ SEG207 = 7 ; ; LCDDR8 - LCD Data Register 8 .equ SEG124 = 0 ; ; LCDDR7 - LCD Data Register 7 .equ SEG116 = 0 ; .equ SEG117 = 1 ; .equ SEG118 = 2 ; .equ SEG119 = 3 ; .equ SEG120 = 4 ; .equ SEG121 = 5 ; .equ SEG122 = 6 ; .equ SEG123 = 7 ; ; LCDDR6 - LCD Data Register 6 .equ SEG108 = 0 ; .equ SEG109 = 1 ; .equ SEG110 = 2 ; .equ SEG111 = 3 ; .equ SEG112 = 4 ; .equ SEG113 = 5 ; .equ SEG114 = 6 ; .equ SEG115 = 7 ; ; LCDDR5 - LCD Data Register 5 .equ SEG100 = 0 ; .equ SEG101 = 1 ; .equ SEG102 = 2 ; .equ SEG103 = 3 ; .equ SEG104 = 4 ; .equ SEG105 = 5 ; .equ SEG106 = 6 ; .equ SEG107 = 7 ; ; LCDDR3 - LCD Data Register 3 .equ SEG024 = 0 ; ; LCDDR2 - LCD Data Register 2 .equ SEG016 = 0 ; .equ SEG017 = 1 ; .equ SEG018 = 2 ; .equ SEG019 = 3 ; .equ SEG020 = 4 ; .equ SEG021 = 5 ; .equ SEG022 = 6 ; .equ SEG023 = 7 ; ; LCDDR1 - LCD Data Register 1 .equ SEG008 = 0 ; .equ SEG009 = 1 ; .equ SEG010 = 2 ; .equ SEG011 = 3 ; .equ SEG012 = 4 ; .equ SEG013 = 5 ; .equ SEG014 = 6 ; .equ SEG015 = 7 ; ; LCDDR0 - LCD Data Register 0 .equ SEG000 = 0 ; .equ SEG001 = 1 ; .equ SEG002 = 2 ; .equ SEG003 = 3 ; .equ SEG004 = 4 ; .equ SEG005 = 5 ; .equ SEG006 = 6 ; .equ SEG007 = 7 ; ; ***** EXTERNAL_INTERRUPT *********** ; EICRA - External Interrupt Control Register .equ ISC00 = 0 ; External Interrupt Sense Control 0 Bit 0 .equ ISC01 = 1 ; External Interrupt Sense Control 0 Bit 1 ; EIMSK - External Interrupt Mask Register .equ INT0 = 0 ; External Interrupt Request 0 Enable .equ PCIE0 = 6 ; Pin Change Interrupt Enable 0 .equ PCIE1 = 7 ; Pin Change Interrupt Enable 1 ; EIFR - External Interrupt Flag Register .equ INTF0 = 0 ; External Interrupt Flag 0 .equ PCIF0 = 6 ; Pin Change Interrupt Flag 0 .equ PCIF1 = 7 ; Pin Change Interrupt Flag 1 ; PCMSK1 - Pin Change Mask Register 1 .equ PCINT8 = 0 ; Pin Change Enable Mask 8 .equ PCINT9 = 1 ; Pin Change Enable Mask 9 .equ PCINT10 = 2 ; Pin Change Enable Mask 10 .equ PCINT11 = 3 ; Pin Change Enable Mask 11 .equ PCINT12 = 4 ; Pin Change Enable Mask 12 .equ PCINT13 = 5 ; Pin Change Enable Mask 13 .equ PCINT14 = 6 ; Pin Change Enable Mask 14 .equ PCINT15 = 7 ; Pin Change Enable Mask 15 ; PCMSK0 - Pin Change Mask Register 0 .equ PCINT0 = 0 ; Pin Change Enable Mask 0 .equ PCINT1 = 1 ; Pin Change Enable Mask 1 .equ PCINT2 = 2 ; Pin Change Enable Mask 2 .equ PCINT3 = 3 ; Pin Change Enable Mask 3 .equ PCINT4 = 4 ; Pin Change Enable Mask 4 .equ PCINT5 = 5 ; Pin Change Enable Mask 5 .equ PCINT6 = 6 ; Pin Change Enable Mask 6 .equ PCINT7 = 7 ; Pin Change Enable Mask 7 ; ***** CPU ************************** ; SREG - Status Register .equ SREG_C = 0 ; Carry Flag .equ SREG_Z = 1 ; Zero Flag .equ SREG_N = 2 ; Negative Flag .equ SREG_V = 3 ; Two's Complement Overflow Flag .equ SREG_S = 4 ; Sign Bit .equ SREG_H = 5 ; Half Carry Flag .equ SREG_T = 6 ; Bit Copy Storage .equ SREG_I = 7 ; Global Interrupt Enable ; MCUCR - MCU Control Register .equ IVCE = 0 ; Interrupt Vector Change Enable .equ IVSEL = 1 ; Interrupt Vector Select .equ PUD = 4 ; Pull-up disable ; MCUSR - MCU Status Register .equ PORF = 0 ; Power-on reset flag .equ EXTRF = 1 ; External Reset Flag .equ BORF = 2 ; Brown-out Reset Flag .equ WDRF = 3 ; Watchdog Reset Flag ;.equ JTRF = 4 ; JTAG Reset Flag ; OSCCAL - Oscillator Calibration Value .equ CAL0 = 0 ; Oscillator Calibration Value Bit0 .equ CAL1 = 1 ; Oscillator Calibration Value Bit1 .equ CAL2 = 2 ; Oscillator Calibration Value Bit2 .equ CAL3 = 3 ; Oscillator Calibration Value Bit3 .equ CAL4 = 4 ; Oscillator Calibration Value Bit4 .equ CAL5 = 5 ; Oscillator Calibration Value Bit5 .equ CAL6 = 6 ; Oscillator Calibration Value Bit6 .equ CAL7 = 7 ; Oscillator Calibration Value Bit7 ; CLKPR - Clock Prescale Register .equ CLKPS0 = 0 ; Clock Prescaler Select Bit 0 .equ CLKPS1 = 1 ; Clock Prescaler Select Bit 1 .equ CLKPS2 = 2 ; Clock Prescaler Select Bit 2 .equ CLKPS3 = 3 ; Clock Prescaler Select Bit 3 .equ CLKPCE = 7 ; Clock Prescaler Change Enable ; PRR - Power Reduction Register .equ PRADC = 0 ; Power Reduction ADC .equ PRUSART0 = 1 ; Power Reduction USART .equ PRSPI = 2 ; Power Reduction Serial Peripheral Interface .equ PRTIM1 = 3 ; Power Reduction Timer/Counter1 .equ PRLCD = 4 ; Power Reduction LCD ; SMCR - Sleep Mode Control Register .equ SE = 0 ; Sleep Enable .equ SM0 = 1 ; Sleep Mode Select bit 0 .equ SM1 = 2 ; Sleep Mode Select bit 1 .equ SM2 = 3 ; Sleep Mode Select bit 2 ; GPIOR2 - General Purpose IO Register 2 .equ GPIOR20 = 0 ; General Purpose IO Register 2 bit 0 .equ GPIOR21 = 1 ; General Purpose IO Register 2 bit 1 .equ GPIOR22 = 2 ; General Purpose IO Register 2 bit 2 .equ GPIOR23 = 3 ; General Purpose IO Register 2 bit 3 .equ GPIOR24 = 4 ; General Purpose IO Register 2 bit 4 .equ GPIOR25 = 5 ; General Purpose IO Register 2 bit 5 .equ GPIOR26 = 6 ; General Purpose IO Register 2 bit 6 .equ GPIOR27 = 7 ; General Purpose IO Register 2 bit 7 ; GPIOR1 - General Purpose IO Register 1 .equ GPIOR10 = 0 ; General Purpose IO Register 1 bit 0 .equ GPIOR11 = 1 ; General Purpose IO Register 1 bit 1 .equ GPIOR12 = 2 ; General Purpose IO Register 1 bit 2 .equ GPIOR13 = 3 ; General Purpose IO Register 1 bit 3 .equ GPIOR14 = 4 ; General Purpose IO Register 1 bit 4 .equ GPIOR15 = 5 ; General Purpose IO Register 1 bit 5 .equ GPIOR16 = 6 ; General Purpose IO Register 1 bit 6 .equ GPIOR17 = 7 ; General Purpose IO Register 1 bit 7 ; GPIOR0 - General Purpose IO Register 0 .equ GPIOR00 = 0 ; General Purpose IO Register 0 bit 0 .equ GPIOR01 = 1 ; General Purpose IO Register 0 bit 1 .equ GPIOR02 = 2 ; General Purpose IO Register 0 bit 2 .equ GPIOR03 = 3 ; General Purpose IO Register 0 bit 3 .equ GPIOR04 = 4 ; General Purpose IO Register 0 bit 4 .equ GPIOR05 = 5 ; General Purpose IO Register 0 bit 5 .equ GPIOR06 = 6 ; General Purpose IO Register 0 bit 6 .equ GPIOR07 = 7 ; General Purpose IO Register 0 bit 7 ; ***** USI ************************** ; USIDR - USI Data Register .equ USIDR0 = 0 ; USI Data Register bit 0 .equ USIDR1 = 1 ; USI Data Register bit 1 .equ USIDR2 = 2 ; USI Data Register bit 2 .equ USIDR3 = 3 ; USI Data Register bit 3 .equ USIDR4 = 4 ; USI Data Register bit 4 .equ USIDR5 = 5 ; USI Data Register bit 5 .equ USIDR6 = 6 ; USI Data Register bit 6 .equ USIDR7 = 7 ; USI Data Register bit 7 ; USISR - USI Status Register .equ USICNT0 = 0 ; USI Counter Value Bit 0 .equ USICNT1 = 1 ; USI Counter Value Bit 1 .equ USICNT2 = 2 ; USI Counter Value Bit 2 .equ USICNT3 = 3 ; USI Counter Value Bit 3 .equ USIDC = 4 ; Data Output Collision .equ USIPF = 5 ; Stop Condition Flag .equ USIOIF = 6 ; Counter Overflow Interrupt Flag .equ USISIF = 7 ; Start Condition Interrupt Flag ; USICR - USI Control Register .equ USITC = 0 ; Toggle Clock Port Pin .equ USICLK = 1 ; Clock Strobe .equ USICS0 = 2 ; USI Clock Source Select Bit 0 .equ USICS1 = 3 ; USI Clock Source Select Bit 1 .equ USIWM0 = 4 ; USI Wire Mode Bit 0 .equ USIWM1 = 5 ; USI Wire Mode Bit 1 .equ USIOIE = 6 ; Counter Overflow Interrupt Enable .equ USISIE = 7 ; Start Condition Interrupt Enable ; ***** AD_CONVERTER ***************** ; ADMUX - The ADC multiplexer Selection Register .equ MUX0 = 0 ; Analog Channel and Gain Selection Bits .equ MUX1 = 1 ; Analog Channel and Gain Selection Bits .equ MUX2 = 2 ; Analog Channel and Gain Selection Bits .equ MUX3 = 3 ; Analog Channel and Gain Selection Bits .equ MUX4 = 4 ; Analog Channel and Gain Selection Bits .equ ADLAR = 5 ; Left Adjust Result .equ REFS0 = 6 ; Reference Selection Bit 0 .equ REFS1 = 7 ; Reference Selection Bit 1 ; ADCSRA - The ADC Control and Status register .equ ADPS0 = 0 ; ADC Prescaler Select Bits .equ ADPS1 = 1 ; ADC Prescaler Select Bits .equ ADPS2 = 2 ; ADC Prescaler Select Bits .equ ADIE = 3 ; ADC Interrupt Enable .equ ADIF = 4 ; ADC Interrupt Flag .equ ADATE = 5 ; ADC Auto Trigger Enable .equ ADSC = 6 ; ADC Start Conversion .equ ADEN = 7 ; ADC Enable ; ADCH - ADC Data Register High Byte .equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0 .equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1 .equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2 .equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3 .equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4 .equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5 .equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6 .equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7 ; ADCL - ADC Data Register Low Byte .equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0 .equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1 .equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2 .equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3 .equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4 .equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5 .equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6 .equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7 ; ADCSRB - ADC Control and Status Register B .equ ADTS0 = 0 ; ADC Auto Trigger Source 0 .equ ADTS1 = 1 ; ADC Auto Trigger Source 1 .equ ADTS2 = 2 ; ADC Auto Trigger Source 2 ; DIDR0 - Digital Input Disable Register 0 .equ ADC0D = 0 ; ADC0 Digital input Disable .equ ADC1D = 1 ; ADC1 Digital input Disable .equ ADC2D = 2 ; ADC2 Digital input Disable .equ ADC3D = 3 ; ADC3 Digital input Disable .equ ADC4D = 4 ; ADC4 Digital input Disable .equ ADC5D = 5 ; ADC5 Digital input Disable .equ ADC6D = 6 ; ADC6 Digital input Disable .equ ADC7D = 7 ; ADC7 Digital input Disable ; ***** BOOT_LOAD ******************** ; SPMCSR - Store Program Memory Control Register .equ SPMCR = SPMCSR ; For compatibility .equ SPMEN = 0 ; Store Program Memory Enable .equ PGERS = 1 ; Page Erase .equ PGWRT = 2 ; Page Write .equ BLBSET = 3 ; Boot Lock Bit Set .equ RWWSRE = 4 ; Read While Write section read enable .equ ASRE = RWWSRE ; For compatibility .equ RWWSB = 6 ; Read While Write Section Busy .equ ASB = RWWSB ; For compatibility .equ SPMIE = 7 ; SPM Interrupt Enable ; ***** USART0 *********************** ; UDR - USART I/O Data Register .equ UDR0 = UDR ; For compatibility .equ UDR00 = 0 ; USART I/O Data Register bit 0 .equ UDR01 = 1 ; USART I/O Data Register bit 1 .equ UDR02 = 2 ; USART I/O Data Register bit 2 .equ UDR03 = 3 ; USART I/O Data Register bit 3 .equ UDR04 = 4 ; USART I/O Data Register bit 4 .equ UDR05 = 5 ; USART I/O Data Register bit 5 .equ UDR06 = 6 ; USART I/O Data Register bit 6 .equ UDR07 = 7 ; USART I/O Data Register bit 7 ; UCSRA - USART Control and Status Register A .equ UCSR0A = UCSRA ; For compatibility .equ USR = UCSRA ; For compatibility .equ MPCM = 0 ; Multi-processor Communication Mode .equ MPCM0 = MPCM ; For compatibility .equ U2X = 1 ; Double the USART Transmission Speed .equ U2X0 = U2X ; For compatibility .equ UPE = 2 ; USART Parity Error .equ UPE0 = UPE ; For compatibility .equ DOR = 3 ; Data OverRun .equ DOR0 = DOR ; For compatibility .equ FE = 4 ; Framing Error .equ FE0 = FE ; For compatibility .equ UDRE = 5 ; USART Data Register Empty .equ UDRE0 = UDRE ; For compatibility .equ TXC = 6 ; USART Transmit Complete .equ TXC0 = TXC ; For compatibility .equ RXC = 7 ; USART Receive Complete .equ RXC0 = RXC ; For compatibility ; UCSRB - USART Control and Status Register B .equ UCSR0B = UCSRB ; For compatibility .equ UCR = UCSRB ; For compatibility .equ TXB8 = 0 ; Transmit Data Bit 8 .equ TXB80 = TXB8 ; For compatibility .equ RXB8 = 1 ; Receive Data Bit 8 .equ RXB80 = RXB8 ; For compatibility .equ UCSZ2 = 2 ; Character Size .equ UCSZ02 = UCSZ2 ; For compatibility .equ TXEN = 3 ; Transmitter Enable .equ TXEN0 = TXEN ; For compatibility .equ RXEN = 4 ; Receiver Enable .equ RXEN0 = RXEN ; For compatibility .equ UDRIE = 5 ; USART Data Register Empty Interrupt Enable .equ UDRIE0 = UDRIE ; For compatibility .equ TXCIE = 6 ; TX Complete Interrupt Enable .equ TXCIE0 = TXCIE ; For compatibility .equ RXCIE = 7 ; RX Complete Interrupt Enable .equ RXCIE0 = RXCIE ; For compatibility ; UCSRC - USART Control and Status Register C .equ UCSR0C = UCSRC ; For compatibility .equ UCPOL = 0 ; Clock Polarity .equ UCPOL0 = UCPOL ; For compatibility .equ UCSZ0 = 1 ; Character Size .equ UCSZ00 = UCSZ0 ; For compatibility .equ UCSZ1 = 2 ; Character Size .equ UCSZ01 = UCSZ1 ; For compatibility .equ USBS = 3 ; Stop Bit Select .equ USBS0 = USBS ; For compatibility .equ UPM0 = 4 ; Parity Mode Bit 0 .equ UPM00 = UPM0 ; For compatibility .equ UPM1 = 5 ; Parity Mode Bit 1 .equ UPM01 = UPM1 ; For compatibility .equ UMSEL = 6 ; USART Mode Select .equ UMSEL0 = UMSEL ; For compatibility .equ UBRR0H = UBRRH ; For compatibility .equ UBRR0L = UBRRL ; For compatibility .equ UBRR0 = UBRRL ; For compatibility .equ UBRR = UBRRL ; For compatibility ; ***** LOCKSBITS ******************************************************** .equ LB1 = 0 ; Lock bit .equ LB2 = 1 ; Lock bit .equ BLB01 = 2 ; Boot Lock bit .equ BLB02 = 3 ; Boot Lock bit .equ BLB11 = 4 ; Boot lock bit .equ BLB12 = 5 ; Boot lock bit ; ***** FUSES ************************************************************ ; LOW fuse bits .equ CKSEL0 = 0 ; Select Clock Source .equ CKSEL1 = 1 ; Select Clock Source .equ CKSEL2 = 2 ; Select Clock Source .equ CKSEL3 = 3 ; Select Clock Source .equ SUT0 = 4 ; Select start-up time .equ SUT1 = 5 ; Select start-up time .equ CKOUT = 6 ; Oscillator options .equ CLKDIV8 = 7 ; Divide clock by 8 ; HIGH fuse bits .equ BOOTRST = 0 ; Select Reset Vector .equ BOOTSZ0 = 1 ; Select Boot Size .equ BOOTSZ1 = 2 ; Select Boot Size .equ EESAVE = 3 ; EEPROM memory is preserved through chip erase .equ WDTON = 4 ; Watchdog timer always on .equ SPIEN = 5 ; Enable Serial programming and Data Downloading .equ JTAGEN = 6 ; Enable JTAG .equ OCDEN = 7 ; Enable OCD ; EXTENDED fuse bits .equ RESERVED = 0 ; Reserved for future use .equ BODLEVEL0 = 1 ; Brown-out Detector trigger level .equ BODLEVEL1 = 2 ; Brown-out Detector trigger level .equ BODLEVEL2 = 3 ; Brown out detector trigger level ; ***** CPU REGISTER DEFINITIONS ***************************************** .def XH = r27 .def XL = r26 .def YH = r29 .def YL = r28 .def ZH = r31 .def ZL = r30 ; ***** DATA MEMORY DECLARATIONS ***************************************** .equ FLASHEND = 0x1fff ; Note: Word address .equ IOEND = 0x00ff .equ SRAM_START = 0x0100 .equ SRAM_SIZE = 1024 .equ RAMEND = 0x04ff .equ XRAMEND = 0x0000 .equ E2END = 0x01ff .equ EEPROMEND = 0x01ff .equ EEADRBITS = 9 #pragma AVRPART MEMORY PROG_FLASH 16384 #pragma AVRPART MEMORY EEPROM 512 #pragma AVRPART MEMORY INT_SRAM SIZE 1024 #pragma AVRPART MEMORY INT_SRAM START_ADDR 0x100 ; ***** BOOTLOADER DECLARATIONS ****************************************** .equ NRWW_START_ADDR = 0x1c00 .equ NRWW_STOP_ADDR = 0x1fff .equ RWW_START_ADDR = 0x0 .equ RWW_STOP_ADDR = 0x1bff .equ PAGESIZE = 64 .equ FIRSTBOOTSTART = 0x1f80 .equ SECONDBOOTSTART = 0x1f00 .equ THIRDBOOTSTART = 0x1e00 .equ FOURTHBOOTSTART = 0x1c00 .equ SMALLBOOTSTART = FIRSTBOOTSTART .equ LARGEBOOTSTART = FOURTHBOOTSTART ; ***** INTERRUPT VECTORS ************************************************ .equ INT0addr = 0x0002 ; External Interrupt Request 0 .equ PCI0addr = 0x0004 ; Pin Change Interrupt Request 0 .equ PCI1addr = 0x0006 ; Pin Change Interrupt Request 1 .equ OC2addr = 0x0008 ; Timer/Counter2 Compare Match .equ OVF2addr = 0x000a ; Timer/Counter2 Overflow .equ ICP1addr = 0x000c ; Timer/Counter1 Capture Event .equ OC1Aaddr = 0x000e ; Timer/Counter1 Compare Match A .equ OC1Baddr = 0x0010 ; Timer/Counter Compare Match B .equ OVF1addr = 0x0012 ; Timer/Counter1 Overflow .equ OC0addr = 0x0014 ; Timer/Counter0 Compare Match .equ OVF0addr = 0x0016 ; Timer/Counter0 Overflow .equ SPIaddr = 0x0018 ; SPI Serial Transfer Complete .equ URXC0addr = 0x001a ; USART0, Rx Complete .equ URXCaddr = 0x001a ; For compatibility .equ UDRE0addr = 0x001c ; USART0 Data register Empty .equ UDREaddr = 0x001c ; For compatibility .equ UTXC0addr = 0x001e ; USART0, Tx Complete .equ UTXCaddr = 0x001e ; For compatibility .equ USI_STARTaddr = 0x0020 ; USI Start Condition .equ USI_OVFaddr = 0x0022 ; USI Overflow .equ ACIaddr = 0x0024 ; Analog Comparator .equ ADCCaddr = 0x0026 ; ADC Conversion Complete .equ ERDYaddr = 0x0028 ; EEPROM Ready .equ SPMRaddr = 0x002a ; Store Program Memory Read .equ LCDSFaddr = 0x002c ; LCD Start of Frame .equ INT_VECTORS_SIZE = 46 ; size in words #endif /* _M169DEF_INC_ */ ; ***** END OF FILE ******************************************************