forked from KolibriOS/kolibrios
289 lines
10 KiB
C
289 lines
10 KiB
C
/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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* IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Qu Pengfei <Pengfei.Qu@intel.com>
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*
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*/
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#ifndef GEN9_MFC_H
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#define GEN9_MFC_H
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#include <drm.h>
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#include <i915_drm.h>
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#include <intel_bufmgr.h>
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#include "i965_gpe_utils.h"
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struct encode_state;
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#define MAX_HCP_REFERENCE_SURFACES 8
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#define NUM_HCP_CURRENT_COLLOCATED_MV_TEMPORAL_BUFFERS 9
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#define INTRA_MB_FLAG_MASK 0x00002000
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/* The space required for slice header SLICE_STATE + header.
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* Is it enough? */
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#define SLICE_HEADER 80
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/* the space required for slice tail. */
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#define SLICE_TAIL 16
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#define __SOFTWARE__ 0
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#define HCP_BATCHBUFFER_HEVC_INTRA 0
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#define HCP_BATCHBUFFER_HEVC_INTER 1
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#define NUM_HCP_KERNEL 2
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#define BIND_IDX_VME_OUTPUT 0
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#define BIND_IDX_HCP_SLICE_HEADER 1
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#define BIND_IDX_HCP_BATCHBUFFER 2
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#define CMD_LEN_IN_OWORD 4
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struct gen9_hcpe_context {
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struct {
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unsigned int width;
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unsigned int height;
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unsigned int w_pitch;
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unsigned int h_pitch;
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} surface_state;
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//HCP_PIPE_BUF_ADDR_STATE
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struct {
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dri_bo *bo;
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} deblocking_filter_line_buffer; //OUTPUT: reconstructed picture with deblocked
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struct {
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dri_bo *bo;
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} deblocking_filter_tile_line_buffer; //OUTPUT: reconstructed picture with deblocked
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struct {
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dri_bo *bo;
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} deblocking_filter_tile_column_buffer; //OUTPUT: reconstructed picture with deblocked
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struct {
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dri_bo *bo;
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} uncompressed_picture_source; //INPUT: original compressed image
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struct {
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dri_bo *bo;
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} metadata_line_buffer; //INTERNAL:metadata
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struct {
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dri_bo *bo;
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} metadata_tile_line_buffer; //INTERNAL:metadata
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struct {
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dri_bo *bo;
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} metadata_tile_column_buffer; //INTERNAL:metadata
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struct {
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dri_bo *bo;
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} sao_line_buffer; //INTERNAL:SAO not used in skylake
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struct {
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dri_bo *bo;
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} sao_tile_line_buffer; //INTERNAL:SAO not used in skylake
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struct {
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dri_bo *bo;
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} sao_tile_column_buffer; //INTERNAL:SAO not used in skylake
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struct {
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dri_bo *bo;
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} current_collocated_mv_temporal_buffer[NUM_HCP_CURRENT_COLLOCATED_MV_TEMPORAL_BUFFERS]; //
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struct {
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dri_bo *bo;
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} reference_surfaces[MAX_HCP_REFERENCE_SURFACES]; //INTERNAL: refrence surfaces
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//HCP_IND_OBJ_BASE_ADDR_STATE
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struct {
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dri_bo *bo;
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} hcp_indirect_cu_object; //INPUT: the cu' mv info
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struct {
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dri_bo *bo;
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int offset;
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int end_offset;
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} hcp_indirect_pak_bse_object; //OUTPUT: the compressed bitstream
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//Bit rate tracking context
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struct {
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unsigned int QpPrimeY;
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unsigned int MaxQpNegModifier;
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unsigned int MaxQpPosModifier;
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unsigned char MaxSizeInWord;
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unsigned char TargetSizeInWord;
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unsigned char Correct[6];
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unsigned char GrowInit;
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unsigned char GrowResistance;
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unsigned char ShrinkInit;
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unsigned char ShrinkResistance;
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unsigned int target_mb_size;
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unsigned int target_frame_size;
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} bit_rate_control_context[3]; //INTERNAL: for I, P, B frames
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struct {
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int mode;
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int gop_nums[3];
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int target_frame_size[3]; // I,P,B
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double bits_per_frame;
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double qpf_rounding_accumulator;
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double saved_bps;
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double saved_fps;
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int saved_intra_period;
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int saved_ip_period;
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int saved_idr_period;
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} brc;
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struct {
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double current_buffer_fullness;
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double target_buffer_fullness;
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double buffer_capacity;
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unsigned int buffer_size;
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unsigned int violation_noted;
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} hrd;
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//HRD control context
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struct {
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int i_bit_rate_value; // scale?
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int i_cpb_size_value; // scale?
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int i_initial_cpb_removal_delay;
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int i_cpb_removal_delay;
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int i_frame_number;
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int i_initial_cpb_removal_delay_length;
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int i_cpb_removal_delay_length;
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int i_dpb_output_delay_length;
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} vui_hrd;
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// picture width and height
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struct {
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uint16_t picture_width_in_samples;
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uint16_t picture_height_in_samples;
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uint16_t picture_width_in_ctbs;
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uint16_t picture_height_in_ctbs;
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uint16_t picture_width_in_min_cb_minus1;
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uint16_t picture_height_in_min_cb_minus1;
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uint16_t picture_width_in_mbs; /* to use on skylake */
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uint16_t picture_height_in_mbs;/* to sue on skylake */
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uint8_t ctb_size;
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uint8_t min_cb_size;
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} pic_size;
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VAQMatrixBufferHEVC iq_matrix_hevc;
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struct i965_gpe_context gpe_context;
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struct i965_buffer_surface hcp_batchbuffer_surface;
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struct intel_batchbuffer *aux_batchbuffer;
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struct i965_buffer_surface aux_batchbuffer_surface;
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void (*pipe_mode_select)(VADriverContextP ctx,
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int standard_select,
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struct intel_encoder_context *encoder_context);
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void (*set_surface_state)(VADriverContextP ctx, struct encode_state *encode_state,
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struct intel_encoder_context *encoder_context);
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void (*ind_obj_base_addr_state)(VADriverContextP ctx,
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struct intel_encoder_context *encoder_context);
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void (*fqm_state)(VADriverContextP ctx,
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struct intel_encoder_context *encoder_context);
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void (*qm_state)(VADriverContextP ctx,
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struct intel_encoder_context *encoder_context);
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void (*pic_state)(VADriverContextP ctx,
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struct encode_state *encode_state,
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struct intel_encoder_context *encoder_context);
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void (*insert_object)(VADriverContextP ctx,
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struct intel_encoder_context *encoder_context,
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unsigned int *insert_data,
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int lenght_in_dws, int data_bits_in_last_dw,
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int skip_emul_byte_count,
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int is_last_header, int is_end_of_slice,
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int emulation_flag,
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struct intel_batchbuffer *batch);
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void (*buffer_suface_setup)(VADriverContextP ctx,
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struct i965_gpe_context *gpe_context,
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struct i965_buffer_surface *buffer_surface,
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unsigned long binding_table_offset,
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unsigned long surface_state_offset);
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};
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VAStatus gen9_hcpe_pipeline(VADriverContextP ctx,
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VAProfile profile,
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struct encode_state *encode_state,
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struct intel_encoder_context *encoder_context);
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/* HEVC BRC */
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extern int intel_hcpe_update_hrd(struct encode_state *encode_state,
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struct gen9_hcpe_context *hcpe_context,
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int frame_bits);
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extern int intel_hcpe_brc_postpack(struct encode_state *encode_state,
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struct gen9_hcpe_context *hcpe_context,
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int frame_bits);
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extern void intel_hcpe_hrd_context_update(struct encode_state *encode_state,
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struct gen9_hcpe_context *hcpe_context);
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extern int intel_hcpe_interlace_check(VADriverContextP ctx,
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struct encode_state *encode_state,
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struct intel_encoder_context *encoder_context);
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extern void intel_hcpe_brc_prepare(struct encode_state *encode_state,
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struct intel_encoder_context *encoder_context);
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/* HEVC HCP pipeline */
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extern void intel_hcpe_hevc_pipeline_header_programing(VADriverContextP ctx,
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struct encode_state *encode_state,
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struct intel_encoder_context *encoder_context,
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struct intel_batchbuffer *slice_batch);
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extern VAStatus intel_hcpe_hevc_prepare(VADriverContextP ctx,
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struct encode_state *encode_state,
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struct intel_encoder_context *encoder_context);
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extern void
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intel_hcpe_hevc_ref_idx_state(VADriverContextP ctx,
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struct encode_state *encode_state,
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struct intel_encoder_context *encoder_context);
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extern void
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intel_hevc_slice_insert_packed_data(VADriverContextP ctx,
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struct encode_state *encode_state,
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struct intel_encoder_context *encoder_context,
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int slice_index,
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struct intel_batchbuffer *slice_batch);
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extern
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Bool gen9_hcpe_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context);
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void gen9_hcpe_context_destroy(void *context);
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#endif /* GEN9_MFC_H */
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