forked from KolibriOS/kolibrios
244 lines
6.3 KiB
C
244 lines
6.3 KiB
C
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#include <stdint.h>
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#include <drm/drmP.h>
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#include <drm.h>
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#include <drm_mm.h>
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#include "radeon_drm.h"
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#include "radeon.h"
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#include "radeon_object.h"
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#define CURSOR_WIDTH 64
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#define CURSOR_HEIGHT 64
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typedef struct tag_object kobj_t;
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typedef struct tag_display display_t;
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struct tag_object
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{
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uint32_t magic;
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void *destroy;
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kobj_t *fd;
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kobj_t *bk;
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uint32_t pid;
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};
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typedef struct
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{
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kobj_t header;
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uint32_t *data;
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uint32_t hot_x;
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uint32_t hot_y;
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struct list_head list;
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struct radeon_object *robj;
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}cursor_t;
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struct tag_display
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{
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int x;
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int y;
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int width;
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int height;
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int bpp;
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int vrefresh;
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int pitch;
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int lfb;
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struct drm_device *ddev;
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struct drm_crtc *crtc;
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struct list_head cursors;
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cursor_t *cursor;
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int (*init_cursor)(cursor_t*);
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cursor_t* (*select_cursor)(display_t*, cursor_t*);
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void (*show_cursor)(int show);
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void (*move_cursor)(int x, int y);
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};
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display_t *rdisplay;
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int init_cursor(cursor_t *cursor)
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{
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struct radeon_device *rdev;
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uint32_t *bits;
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uint32_t *src;
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int i,j;
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int r;
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rdev = (struct radeon_device *)rdisplay->ddev->dev_private;
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r = radeon_object_create(rdev, NULL, CURSOR_WIDTH*CURSOR_HEIGHT*4,
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false,
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RADEON_GEM_DOMAIN_VRAM,
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false, &cursor->robj);
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if (unlikely(r != 0))
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return r;
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radeon_object_pin(cursor->robj, RADEON_GEM_DOMAIN_VRAM, NULL);
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r = radeon_object_kmap(cursor->robj, &bits);
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if (r) {
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DRM_ERROR("radeon: failed to map cursor (%d).\n", r);
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return r;
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};
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src = cursor->data;
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for(i = 0; i < 32; i++)
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{
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for(j = 0; j < 32; j++)
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*bits++ = *src++;
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for(j = 0; j < CURSOR_WIDTH-32; j++)
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*bits++ = 0;
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}
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for(i = 0; i < CURSOR_WIDTH*(CURSOR_HEIGHT-32); i++)
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*bits++ = 0;
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radeon_object_kunmap(cursor->robj);
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return 0;
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};
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int init_display(struct radeon_device *rdev)
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{
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cursor_t *cursor;
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// rdisplay = get_display();
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rdisplay->ddev = rdev->ddev;
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list_for_each_entry(cursor, &rdisplay->cursors, list)
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{
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init_cursor(cursor);
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};
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return 1;
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};
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static void radeon_lock_cursor(struct drm_crtc *crtc, bool lock)
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{
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struct radeon_device *rdev = crtc->dev->dev_private;
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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uint32_t cur_lock;
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if (ASIC_IS_AVIVO(rdev)) {
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cur_lock = RREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset);
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if (lock)
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cur_lock |= AVIVO_D1CURSOR_UPDATE_LOCK;
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else
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cur_lock &= ~AVIVO_D1CURSOR_UPDATE_LOCK;
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WREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock);
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} else {
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cur_lock = RREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset);
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if (lock)
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cur_lock |= RADEON_CUR_LOCK;
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else
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cur_lock &= ~RADEON_CUR_LOCK;
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WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, cur_lock);
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}
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}
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cursor_t* select_cursor(display_t *display, cursor_t *cursor)
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{
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struct radeon_device *rdev;
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struct radeon_crtc *radeon_crtc;
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cursor_t *old;
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uint32_t gpu_addr;
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rdev = (struct radeon_device *)rdisplay->ddev->dev_private;
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radeon_crtc = to_radeon_crtc(rdisplay->crtc);
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old = display->cursor;
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display->cursor = cursor;
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gpu_addr = cursor->robj->gpu_addr;
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if (ASIC_IS_AVIVO(rdev))
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WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, gpu_addr);
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else {
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radeon_crtc->legacy_cursor_offset = gpu_addr - radeon_crtc->legacy_display_base_addr;
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/* offset is from DISP(2)_BASE_ADDRESS */
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WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, radeon_crtc->legacy_cursor_offset);
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}
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return old;
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};
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int radeon_cursor_move(display_t *display, int x, int y)
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{
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struct drm_crtc *crtc = rdisplay->crtc;
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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struct radeon_device *rdev = crtc->dev->dev_private;
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int hot_x = rdisplay->cursor->hot_x - 1;
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int hot_y = rdisplay->cursor->hot_y - 1;
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radeon_lock_cursor(crtc, true);
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if (ASIC_IS_AVIVO(rdev))
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{
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int w = 32;
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int i = 0;
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struct drm_crtc *crtc_p;
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/* avivo cursor are offset into the total surface */
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x += crtc->x;
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y += crtc->y;
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// DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
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#if 0
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/* avivo cursor image can't end on 128 pixel boundry or
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* go past the end of the frame if both crtcs are enabled
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*/
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list_for_each_entry(crtc_p, &crtc->dev->mode_config.crtc_list, head) {
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if (crtc_p->enabled)
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i++;
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}
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if (i > 1) {
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int cursor_end, frame_end;
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cursor_end = x + w;
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frame_end = crtc->x + crtc->mode.crtc_hdisplay;
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if (cursor_end >= frame_end) {
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w = w - (cursor_end - frame_end);
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if (!(frame_end & 0x7f))
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w--;
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} else {
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if (!(cursor_end & 0x7f))
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w--;
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}
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if (w <= 0)
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w = 1;
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}
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#endif
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WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset,
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(x << 16) | y);
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WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset,
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(hot_x << 16) | hot_y-1);
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WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset,
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((w - 1) << 16) | 31);
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} else {
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if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)
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y *= 2;
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WREG32(RADEON_CUR_HORZ_VERT_OFF + radeon_crtc->crtc_offset,
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(RADEON_CUR_LOCK | (hot_x << 16) | (hot_y << 16)));
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WREG32(RADEON_CUR_HORZ_VERT_POSN + radeon_crtc->crtc_offset,
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(RADEON_CUR_LOCK | (x << 16) | y));
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/* offset is from DISP(2)_BASE_ADDRESS */
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WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset,
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(radeon_crtc->legacy_cursor_offset + (hot_y * 256)));
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}
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radeon_lock_cursor(crtc, false);
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return 0;
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}
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