From 298c1a755bf5f02158405bd688a74fc9ca9ec468 Mon Sep 17 00:00:00 2001
From: "Artem Jerdev (art_zh)" <artem@jerdev.co.uk>
Date: Mon, 17 May 2010 10:14:12 +0000
Subject: [PATCH] PCIexpress: extended configurator

git-svn-id: svn://kolibrios.org@1463 a494cfbc-eb01-0410-851d-a64ba20cac60
---
 kernel/trunk/bus/pci/PCIe.inc | 109 ++++++++++++++++++++++++++++++++++
 1 file changed, 109 insertions(+)
 create mode 100644 kernel/trunk/bus/pci/PCIe.inc

diff --git a/kernel/trunk/bus/pci/PCIe.inc b/kernel/trunk/bus/pci/PCIe.inc
new file mode 100644
index 0000000000..cd2cc9083b
--- /dev/null
+++ b/kernel/trunk/bus/pci/PCIe.inc
@@ -0,0 +1,109 @@
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;                                                              ;;
+;; Copyright (C) 2010 KolibriOS team.     All rights reserved.  ;;
+;; Distributed under terms of the GNU General Public License    ;;
+;;                                                              ;;
+;;                                                              ;;
+;;  PCIe.INC                                                    ;;
+;;                                                              ;;
+;;  Extended PCI express services                               ;;
+;;                                                              ;;
+;;  Author:                                                     ;;
+;;  	            art_zh  <artem@jerdev.co.uk>                ;;
+;;                                                              ;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+$Revision: 1463 $
+
+;***************************************************************************
+;   Function
+;      pci_ext_config:
+;
+;   Description
+;       PCIe extended (memory-mapped) config space detection
+;
+;   WARNINGs: 
+;	1) Very Experimental! 
+;	2) direct HT-detection (no ACPI or BIOS service used)
+;	3) Only AMD/HT processors currently supported 
+;
+;***************************************************************************
+
+PCIe_CONFIG_SPACE	equ	0xF0000000	; to be moved to const.inc
+mmio_pcie_cfg_addr	dd  	0x0		; not defined by default
+mmio_pcie_cfg_lim	dd	0x0		; each bus needs 1Mb 
+
+
+align 4
+
+pci_ext_config:
+
+	push	ebx
+	mov	bx, 0xC184		; dev = 24, fn = 01, reg = 84h
+
+.check_HT_mmio:
+	mov	cx, bx
+	mov	ax, 0x0002		; bus = 0, 1dword to read
+	call 	pci_read_reg
+	mov	bx, cx
+	sub	bl, 4
+	and 	al, 0x80		; check the NP bit
+	jz	.not_pcie_cfg
+	shl	eax, 8			; bus:[27..20], dev:[19:15] 
+	or	eax, 0x00007FFC		; fun:[14..12], reg:[11:2] 
+	mov	[mmio_pcie_cfg_lim], eax
+	mov	cl, bl
+	mov	ax, 0x0002		; bus = 0, 1dword to read
+	call 	pci_read_reg
+	mov	bx, cx
+	test	al, 0x03		; MMIO Base RW enabled?
+	jz	.not_pcie_cfg
+	test	al, 0x0C		; MMIO Base locked?
+	jnz	.not_pcie_cfg
+	xor	al, al
+	shl	eax, 8
+;	test	eax, 0x000F0000		; MMIO Base must be bus0-aligned
+;	jnz	.not_pcie_cfg
+	mov	[mmio_pcie_cfg_addr], eax
+	add	eax, 0x000FFFFC
+	sub	eax,[mmio_pcie_cfg_lim]	; MMIO must cover at least one bus
+	ja	.not_pcie_cfg
+
+;	-- it looks like a true PCIe config space; 
+	mov 	eax,[mmio_pcie_cfg_addr]	; physical address
+	or	eax, (PG_SHARED + PG_LARGE + PG_USER)
+	mov	ebx, PCIe_CONFIG_SPACE		; linear address
+	mov	ecx, ebx
+	shr	ebx, 20		
+	add	ebx, sys_pgdir			; PgDir entry @
+@@:
+	mov	dword[ebx], eax			; map 4 buses
+	invlpg	[ecx]
+	cmp	bl, 4
+	jz	.pcie_cfg_mapped		; fix it later
+	add	bl, 4				; next PgDir entry
+	add	eax, 0x400000			; eax += 4M
+	add	ecx, 0x400000
+	jmp	@b	
+
+.pcie_cfg_mapped:
+	
+;	-- glad to have the extended PCIe config field found
+	mov	esi, boot_pcie_ok
+	pop	ebx
+	call	boot_log
+	ret	; <<<<<<<<<<< OK >>>>>>>>>>>
+	
+.not_pcie_cfg:
+
+	xor	eax, eax
+	mov	[mmio_pcie_cfg_addr], eax
+	mov	[mmio_pcie_cfg_lim],  eax
+	add	bl, 12
+	cmp	bl, 0xC0		; MMIO regs lay below this offset
+	jb	.check_HT_mmio
+	mov	esi, boot_pcie_fail
+	pop	ebx
+	call	boot_log
+	ret	; <<<<<<<<< FAILURE >>>>>>>>>
+