kolibrios-nvme-driver/drivers/nvme/nvme.asm

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;                                                                 ;;
;; Copyright (C) KolibriOS team 2004-2024. All rights reserved.    ;;
;; Distributed under terms of the GNU General Public License       ;;
;;                                                                 ;;
;;          GNU GENERAL PUBLIC LICENSE                             ;;
;;             Version 2, June 1991                                ;;
;;                                                                 ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

format PE DLL native
entry START

API_VERSION     equ 0  ;debug
SRV_GETVERSION  equ 0
__DEBUG__ = 1
__DEBUG_LEVEL__ = 1
DRIVER_VERSION = 1
DBG_INFO = 1

section ".flat" code readable writable executable
include "../proc32.inc"
include "../struct.inc"
include "../macros.inc"
include "../fdo.inc"
include "../pci.inc"
include "../peimport.inc"
include "nvme.inc"
include "macros.inc"

proc START c, reason:dword

        cmp     [reason], DRV_ENTRY
        jne     .err

.entry:
		DEBUGF  DBG_INFO, "Detecting NVMe hardware...\n"
        call    detect_nvme
		test 	eax, eax
        jz      .err
		mov 	eax, dword [p_nvme_devices]
		test 	eax, eax
		jz 		.err
		xor 	ecx, ecx

.loop:
		mov 	ebx, dword [p_nvme_devices]
		stdcall device_is_compat, ebx
		test 	eax, eax
		jz 		@f
		stdcall nvme_init, ebx

@@:
		inc 	ecx
		cmp 	ecx, dword [pcidevs_len]
		jne 	.loop
        invoke  RegService, my_service, service_proc
        ret

.err:
		call    nvme_cleanup
        xor     eax, eax
        ret

endp

proc service_proc stdcall, ioctl:dword

        mov     ebx, [ioctl]
        mov     eax, [ebx+IOCTL.io_code]
        cmp     eax, SRV_GETVERSION
        jne     @F

        mov     eax, [ebx+IOCTL.output]
        cmp     [ebx+IOCTL.out_size], 4
        jne     @F
        mov     dword [eax], API_VERSION
        xor     eax, eax
        ret
@@:
        or      eax, -1
        ret

endp

proc memset stdcall, p_data:dword, val:byte, sz:dword

		push    ebx ecx edx
		mov 	edx, [sz]
		mov     bl, [val]
		xor     ecx, ecx 
@@:
		mov     byte [p_data + ecx], bl
		inc     ecx
		cmp     ecx, edx
		jne     @b
		pop     edx ecx ebx
		ret

endp

; Submit a Command in the Admin Submission Queue
proc submit_asq stdcall, p_sq:dword

		xor 	eax, eax
		ret

endp

proc nvme_identify stdcall, nsid:dword, dptr:dword, cns:byte

		sub     esp, sizeof.SQ_ENTRY
		stdcall memset, esp, 0, sizeof.SQ_ENTRY

		mov     eax, dword [nsid]
		mov     dword [esp + SQ_ENTRY.nsid], eax
		mov     eax, dword [dptr]
		mov     dword [esp + SQ_ENTRY.dptr], eax
		mov     dword [esp + SQ_ENTRY.cdw0], ADM_CMD_IDENTIFY ; TODO: setting CID to 0 for now but later on keep a unique list of identifiers
		mov     al, byte [cns]
		mov     byte [esp + SQ_ENTRY.cdw10], al
		stdcall submit_asq, esp

		add     esp, sizeof.SQ_ENTRY
		xor     eax, eax
		ret

endp

proc detect_nvme

        invoke  GetPCIList
		mov 	edx, eax

.check_dev:
		mov 	ebx, dword [eax + PCIDEV.class]
		and		ebx, 0x00ffff00 ; retrieve class/subclass code only
		cmp 	ebx, 0x00010800 ; Mass Storage Controller - Non-Volatile Memory Controller
		je		.found_dev

.next_dev:
		mov		eax, dword [eax + PCIDEV.fd]
		cmp		eax, edx
		jne 	.check_dev
		jmp 	.exit_success

.found_dev:
		push    edx eax
		PDEBUGF DBG_INFO, "PCI(%u.%u.%u): Detected NVMe device...\n", byte [eax + PCIDEV.bus], byte [eax + PCIDEV.devfn]
		cmp 	dword [pcidevs_len], TOTAL_PCIDEVS
		jne 	@f
		pop 	eax edx
		jmp 	.exit_success

@@:
		inc 	dword [pcidevs_len]
		mov     ebx, dword [p_nvme_devices]
		test    ebx, ebx
		jnz		@f
		invoke  KernelAlloc, sizeof.pcidev
		test 	eax, eax
		jz 		.err_no_mem
		mov     dword [p_nvme_devices], eax 
		DEBUGF  DBG_INFO, "(NVMe) Allocated pcidev struct at 0x%x\n", [p_nvme_devices]

@@:
		mov 	ecx, dword [pcidevs_len]
		dec 	ecx
		pop		eax
		mov 	ebx, dword [p_nvme_devices]

		movzx 	edx, byte [eax + PCIDEV.bus]
		mov 	byte [ebx + pcidev.bus], dl
		movzx 	edx, byte [eax + PCIDEV.devfn]
		mov 	byte [ebx + pcidev.devfn], dl

		pop 	edx
		jmp		.next_dev

.err_no_mem:
		pop     eax edx
		xor 	eax, eax
		ret

.exit_success:
		xor 	eax, eax
		inc 	eax
		ret

endp

proc device_is_compat stdcall, pci:dword

		push  	 ebx
		mov 	 ebx, [pci]
		invoke   PciRead32, dword [ebx + pcidev.bus], dword [ebx + pcidev.devfn], PCI_header00.base_addr_0
		and      eax, 0xfffffff0
		test     eax, eax
		jz       .failure

		invoke   MapIoMem, eax, sizeof.NVME_MMIO, PG_SW+PG_NOCACHE
		test     eax, eax
		jz       .failure
		DEBUGF   DBG_INFO, "(NVMe) MMIO allocated at: 0x%x\n", eax
		mov 	 ebx, [pci]
		mov 	 dword [ebx + pcidev.mmio_ptr], eax
		mov 	 eax, dword [eax + NVME_MMIO.VS]
		DEBUGF   DBG_INFO, "(NVMe) Controller version: 0x%x\n", eax
		pop 	 ebx
		xor 	 eax, eax
		inc 	 eax
		ret

.failure:
		PDEBUGF  DBG_INFO, "PCI(%u.%u.%u): something went wrong checking NVMe device compatibility\n", byte [ebx + pcidev.bus], byte [ebx + pcidev.devfn]
		pop 	 ebx
		xor      eax, eax
		ret
	
endp

; nvme_init: Initializes the NVMe controller 
proc nvme_init stdcall, pci:dword

		push 	 ebx
		mov 	 eax, dword [pci]
		mov      eax, dword [eax + pcidev.mmio_ptr]

		if __DEBUG__
			mov    ebx, dword [eax + NVME_MMIO.CAP]
			DEBUGF DBG_INFO, "(NVMe) CAP (0-31): 0x%x\n", ebx
			mov    ebx, dword [eax + NVME_MMIO.CAP + 4]
			DEBUGF DBG_INFO, "(NVMe) CAP (32-63): 0x%x\n", ebx
		end if

		mov      ebx, dword [eax + NVME_MMIO.CAP]
		test     ebx, CAP_CQR
		jz       .cqr_not_req

.cqr_not_req:
		; For some reason, bit 7 (No I/O command set supported) is also set to 1 despite bit 0 (NVM command set)
	    ; being set to 1.. so I am not sure if bit 7 should be checked at all.. investigate later.
		mov      ebx, dword [eax + NVME_MMIO.CAP + 4]
		test 	 ebx, CAP_CSS_NVM_CMDSET
		jz       .exit_fail

		; Reset controller
		stdcall nvme_controller_reset, [pci]

        xor     eax, eax
        inc     eax
		pop     ebx
        ret

.exit_fail:
		PDEBUGF DBG_INFO, "PCI(%u.%u.%u): failed to initialize NVMe controller\n", byte [pci + pcidev.bus], byte [pci + pcidev.devfn]
		xor 	eax, eax
		pop     ebx
		ret

endp

proc nvme_controller_reset stdcall, pci:dword

		DEBUGF  DBG_INFO, "(NVMe) Resetting Controller...\n"
		push 	ebx
		mov 	ebx, dword [pci]
		mov 	ebx, dword [ebx + pcidev.mmio_ptr]
		mov 	eax, dword [ebx + NVME_MMIO.CC]
		and 	eax, 0xfffffffe ; CC.EN = 0
		mov 	dword [ebx + NVME_MMIO.CC], eax
		stdcall nvme_wait, [pci]

; Wait for controller to be brought to idle state, CSTS.RDY should be cleared to 0 when this happens
.wait:
		mov 	eax, dword [ebx + NVME_MMIO.CSTS]
		test    eax, CSTS_RDY
		jnz 	.wait
		DEBUGF  DBG_INFO, "(NVMe) Successfully reset controller...\n"
		pop 	ebx
		ret

endp

; Should be called only after the value of CC.EN has changed
proc nvme_wait stdcall, pci:dword

		mov 	eax, [pci]
		mov 	eax, [eax + pcidev.mmio_ptr]
		mov 	eax, dword [eax + NVME_MMIO.CAP]
		and 	eax, CAP_TO
		shr 	eax, 24
		mov 	esi, eax
		imul 	esi, 50
		invoke  Sleep
		ret

endp

proc nvme_cleanup

		DEBUGF  DBG_INFO, "(NVMe): Cleaning up...\n"
		push 	ecx
		mov 	eax, dword [p_nvme_devices]
		mov 	ecx, eax
		test 	eax, eax
		jnz 	.loop
		ret

.loop:
		;invoke  KernelFree, dword [p_nvme_devices + ecx * sizeof.pcidev + pcidev.ident_ptr]
		dec 	ecx
		test 	ecx, ecx
		jnz 	.loop
		invoke  KernelFree, dword [p_nvme_devices]
		pop 	ecx
		ret

endp

;all initialized data place here
align 4
		p_nvme_devices dd 0
		pcidevs_len  dd 0
		my_service   db "NVMe",0  ;max 16 chars include zero
		if __DEBUG__
		include_debug_strings
		end if

align 4
data fixups
end data