blit into pixmap
git-svn-id: svn://kolibrios.org@815 a494cfbc-eb01-0410-851d-a64ba20cac60
This commit is contained in:
parent
c1fce6235d
commit
0c807b742c
@ -4,6 +4,8 @@
|
||||
#define LINE_2P 3
|
||||
#define BLIT 4
|
||||
#define COMPIZ 5
|
||||
#define PIXMAP 6
|
||||
#define PIXBLIT 7
|
||||
|
||||
typedef unsigned int color_t;
|
||||
|
||||
@ -49,6 +51,29 @@ typedef struct
|
||||
u32 color;
|
||||
}line2p_t;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
u32_t pixmap;
|
||||
u32_t format;
|
||||
u32_t width;
|
||||
u32_t height;
|
||||
u32_t pitch;
|
||||
}new_pixmap_t;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
pixmap_t *dstpix;
|
||||
int dst_x;
|
||||
int dst_y;
|
||||
|
||||
pixmap_t *srcpix;
|
||||
int src_x;
|
||||
int src_y;
|
||||
int w;
|
||||
int h;
|
||||
}pixblit_t;
|
||||
|
||||
|
||||
int LineClip( int *x1, int *y1, int *x2, int *y2 );
|
||||
int BlockClip( int *x1, int *y1, int *x2, int* y2);
|
||||
|
||||
@ -59,9 +84,11 @@ int Line2P(line2p_t *draw);
|
||||
|
||||
int Blit(blit_t *blit);
|
||||
|
||||
|
||||
int RadeonComposite( blit_t *blit);
|
||||
|
||||
int CreatePixmap(new_pixmap_t *io);
|
||||
|
||||
int PixBlit(pixblit_t* blit);
|
||||
|
||||
# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
|
||||
# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
|
||||
|
@ -227,3 +227,114 @@ int Line2P(line2p_t *draw)
|
||||
};
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
int CreatePixmap(new_pixmap_t *io)
|
||||
{
|
||||
|
||||
pixmap_t *pixmap;
|
||||
|
||||
u32_t pitch;
|
||||
void *raw;
|
||||
|
||||
if( (io->width == 0) || (io->width > 2048)||
|
||||
(io->height == 0)|| (io->height > 2048))
|
||||
{
|
||||
dbgprintf("Invalid pixmap size w:%d h:%d\n", io->width,io->height);
|
||||
return 0;
|
||||
|
||||
};
|
||||
|
||||
pitch = ((io->width+15)&~15)*4;
|
||||
dbgprintf("pitch = %d\n", pitch);
|
||||
|
||||
raw = rhd_mem_alloc(&rhd,RHD_MEM_FB,pitch*io->height) ;
|
||||
if (! raw)
|
||||
{
|
||||
dbgprintf("Not enough memory for pixmap\n");
|
||||
return 0;
|
||||
};
|
||||
|
||||
pixmap = malloc(sizeof(pixmap_t));
|
||||
if(!pixmap)
|
||||
{
|
||||
rhd_mem_free(&rhd, RHD_MEM_FB,raw);
|
||||
return 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
io->pixmap = (u32_t)pixmap;
|
||||
io->format = PICT_a8r8g8b8;
|
||||
io->pitch = pitch;
|
||||
|
||||
pixmap->width = io->width;
|
||||
pixmap->height = io->height;
|
||||
pixmap->format = PICT_a8r8g8b8;
|
||||
pixmap->pitch = pitch;
|
||||
pixmap->offset = (u32_t)raw-rhd.FbBase+rhd.FbIntAddress;
|
||||
pixmap->pitch_offset = ((pitch/64)<<22)| (pixmap->offset>>10);
|
||||
pixmap->raw = raw;
|
||||
|
||||
dbgprintf("pixmap.pitch_offset: %x\n", pixmap->pitch_offset);
|
||||
dbgprintf("width: %d height: %d\n",pixmap->width,pixmap->height );
|
||||
dbgprintf("pixmap.offset: %x\n", pixmap->offset);
|
||||
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
|
||||
int PixBlit(pixblit_t *blit)
|
||||
{
|
||||
|
||||
u32 *ring, write;
|
||||
int w, h;
|
||||
u32 ifl;
|
||||
int x0, y0;
|
||||
|
||||
pixmap_t *srcpixmap;
|
||||
pixmap_t *dstpixmap;
|
||||
|
||||
dbgprintf("Pixblit src: %x dst: %x\n",blit->srcpix, blit->dstpix);
|
||||
|
||||
dstpixmap = (blit->dstpix == (void*)-1) ? &scr_pixmap : blit->dstpix ;
|
||||
srcpixmap = (blit->srcpix == (void*)-1) ? &scr_pixmap : blit->srcpix ;
|
||||
|
||||
dbgprintf("srcpixmap: %x dstpixmap: %x\n",srcpixmap, dstpixmap);
|
||||
|
||||
dbgprintf("dst.width: %d dst.height: %d\n", dstpixmap->width,dstpixmap->height);
|
||||
dbgprintf("src.width: %d src.height: %d\n", srcpixmap->width,srcpixmap->height);
|
||||
dbgprintf("srcpitch: %x dstpitch: %x\n",
|
||||
srcpixmap->pitch_offset,dstpixmap->pitch_offset);
|
||||
|
||||
ifl = safe_cli();
|
||||
|
||||
|
||||
BEGIN_RING();
|
||||
OUT_RING(CP_PACKET3(RADEON_CNTL_BITBLT, 5));
|
||||
|
||||
OUT_RING(RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
|
||||
RADEON_GMC_DST_PITCH_OFFSET_CNTL |
|
||||
RADEON_GMC_BRUSH_NONE |
|
||||
RADEON_GMC_DST_32BPP |
|
||||
RADEON_GMC_SRC_DATATYPE_COLOR |
|
||||
RADEON_DP_SRC_SOURCE_MEMORY |
|
||||
(1 << 28)+(1 << 30) | R5XX_ROP3_S);
|
||||
|
||||
OUT_RING(srcpixmap->pitch_offset);
|
||||
OUT_RING(dstpixmap->pitch_offset);
|
||||
|
||||
// x0 = blit->src_x;
|
||||
// y0 = blit->src_y;
|
||||
// w = blit->w;
|
||||
// h = blit->h;
|
||||
|
||||
OUT_RING((blit->src_x<<16)|blit->src_y);
|
||||
OUT_RING((blit->dst_x<<16)|blit->dst_y);
|
||||
OUT_RING((blit->w<<16)|blit->h);
|
||||
COMMIT_RING();
|
||||
|
||||
safe_sti(ifl);
|
||||
return 0;
|
||||
}
|
||||
|
@ -7,8 +7,11 @@
|
||||
|
||||
RHD_t rhd;
|
||||
|
||||
pixmap_t scr_pixmap;
|
||||
|
||||
static clip_t clip;
|
||||
|
||||
|
||||
void STDCALL (*SelectHwCursor)(cursor_t*)__asm__("SelectHwCursor");
|
||||
void STDCALL (*SetHwCursor)(cursor_t*,int x,int y)__asm__("SetHwCursor");
|
||||
void STDCALL (*HwCursorRestore)(int x, int y)__asm("HwCursorRestore");
|
||||
@ -161,6 +164,15 @@ int _stdcall srv_2d(ioctl_t *io)
|
||||
return RadeonComposite((blit_t*)inp);
|
||||
break;
|
||||
|
||||
case PIXMAP:
|
||||
if(io->inp_size==5)
|
||||
return CreatePixmap((new_pixmap_t*)inp);
|
||||
break;
|
||||
|
||||
case PIXBLIT:
|
||||
if(io->inp_size==8)
|
||||
return PixBlit((pixblit_t*)inp);
|
||||
break;
|
||||
|
||||
default:
|
||||
return ERR_PARAM;
|
||||
|
@ -175,6 +175,19 @@ typedef struct
|
||||
int ymax;
|
||||
}clip_t, *PTRclip;
|
||||
|
||||
|
||||
typedef struct
|
||||
{
|
||||
u32_t width;
|
||||
u32_t height;
|
||||
u32_t format;
|
||||
u32_t pitch;
|
||||
u32_t offset;
|
||||
u32_t pitch_offset;
|
||||
u32_t *raw;
|
||||
}pixmap_t;
|
||||
|
||||
|
||||
typedef struct {
|
||||
int token; /* id of the token */
|
||||
const char * name; /* token name */
|
||||
|
@ -384,6 +384,16 @@ void R5xx2DInit()
|
||||
|
||||
dbgprintf("dst_pitch_offset %x \n", rhd.dst_pitch_offset);
|
||||
|
||||
|
||||
scr_pixmap.width = rhd.displayWidth;
|
||||
scr_pixmap.height = rhd.displayHeight;
|
||||
scr_pixmap.format = PICT_a8r8g8b8;
|
||||
scr_pixmap.pitch = rhd.displayWidth * 4;
|
||||
scr_pixmap.offset = rhd.FbIntAddress;
|
||||
scr_pixmap.pitch_offset = rhd.dst_pitch_offset;
|
||||
scr_pixmap.raw = (void*)rhd.FbBase;
|
||||
|
||||
|
||||
MASKREG(R5XX_GB_TILE_CONFIG, 0, R5XX_ENABLE_TILING);
|
||||
OUTREG (R5XX_WAIT_UNTIL, R5XX_WAIT_2D_IDLECLEAN | R5XX_WAIT_3D_IDLECLEAN);
|
||||
MASKREG(R5XX_DST_PIPE_CONFIG, R5XX_PIPE_AUTO_CONFIG, R5XX_PIPE_AUTO_CONFIG);
|
||||
|
Loading…
Reference in New Issue
Block a user