KolibriOS/kolibrios
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pcie gart. Btw device can blit directly from system memory without gart, agp, etc. At least two chip.

Browse Source 
git-svn-id: svn://kolibrios.org@1026 a494cfbc-eb01-0410-851d-a64ba20cac60
This commit is contained in:
Sergey Semyonov (Serge) 2009-02-08 18:41:45 +00:00
parent cefa38b9f8
commit 6f9d9ccc76
13 changed files with 627 additions and 652 deletions
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30
programs/system/drivers/ati2d/accel_2d.h
View File

@ -40,28 +40,28 @@ int BlockClip( clip_t *clip, int *x1, int *y1, int *x2, int* y2 );
typedef struct
{
unsigned width;
unsigned height;
u32_t format;
u32_t flags;
unsigned pitch;
unsigned width;
unsigned height;
u32_t format;
u32_t flags;
size_t pitch;
void *mapped;
u32_t handle;
}pixmap_t;
typedef struct
{
unsigned width;
unsigned height;
u32_t format;
u32_t flags;
unsigned pitch;
unsigned width;
unsigned height;
u32_t format;
u32_t flags;
size_t pitch;
void *mapped;
unsigned pitch_offset;
void *local;
addr_t local;
}local_pixmap_t;
#define PX_MEM_SYSTEM 0
@ -70,8 +70,7 @@ typedef struct
#define PX_MEM_MASK 3
#define PX_LOCK 1
#define PX_LOCK 1
typedef struct
{
@ -142,6 +141,9 @@ typedef struct
}io_blit_t;
static addr_t bind_pixmap(local_pixmap_t *pixmap);
int CreatePixmap(pixmap_t *io);
int DestroyPixmap(pixmap_t *io);

148
programs/system/drivers/ati2d/accel_2d.inc
View File

@ -572,42 +572,50 @@ int FillRect(io_fill_t *fill)
static int blit_host(u32_t dstpitch, int dstx, int dsty,
u32_t src, int srcx, int srcy,
int w, int h, int srcpitch)
int w, int h, int srcpitch, Bool trans, color_t key)
{
u32_t ifl;
u32_t dp_cntl;
color_t *src_addr;
ifl = safe_cli();
#if R300_PIO
R5xxFIFOWait(5);
OUTREG(R5XX_DP_GUI_MASTER_CNTL,
RADEON_GMC_DST_PITCH_OFFSET_CNTL |
// RADEON_GMC_DST_CLIPPING |
dp_cntl = RADEON_GMC_DST_PITCH_OFFSET_CNTL |
RADEON_GMC_BRUSH_NONE |
RADEON_GMC_DST_32BPP |
RADEON_GMC_SRC_DATATYPE_COLOR |
RADEON_DP_SRC_SOURCE_HOST_DATA |
// RADEON_GMC_BYTE_MSB_TO_LSB |
R5XX_GMC_CLR_CMP_CNTL_DIS |
R5XX_GMC_WR_MSK_DIS |
R5XX_ROP3_S
);
R5XX_ROP3_S;
if( trans == FALSE )
{
dp_cntl|= R5XX_GMC_CLR_CMP_CNTL_DIS;
R5xxFIFOWait(5);
}
else
R5xxFIFOWait(8);
OUTREG(R5XX_DP_GUI_MASTER_CNTL, dp_cntl);
OUTREG(R5XX_DP_CNTL, R5XX_DST_X_LEFT_TO_RIGHT |
R5XX_DST_Y_TOP_TO_BOTTOM);
OUTREG(R5XX_DST_PITCH_OFFSET, dstpitch);
// OUTREG(RADEON_SC_TOP_LEFT, (y << 16) | ((x+skipleft) & 0xffff));
// OUTREG(RADEON_SC_BOTTOM_RIGHT, ((y+h) << 16) | ((x+w) & 0xffff));
if( trans )
{
OUTREG(R5XX_CLR_CMP_CLR_SRC, key);
OUTREG(R5XX_CLR_CMP_MASK, R5XX_CLR_CMP_MSK);
OUTREG(R5XX_CLR_CMP_CNTL, R5XX_SRC_CMP_EQ_COLOR |
R5XX_CLR_CMP_SRC_SOURCE);
};
OUTREG(RADEON_DST_Y_X, (dsty << 16) | (dstx & 0xffff));
OUTREG(RADEON_DST_HEIGHT_WIDTH, (h << 16) | w);
src_addr = &((color_t*)src)[srcpitch*srcy/4+srcx];
while ( h-- )
@ -664,18 +672,11 @@ int Blit(io_blit_t *blit)
local_pixmap_t *srcpixmap;
local_pixmap_t *dstpixmap;
//dbgprintf("Pixblit src: %x dst: %x\n",blit->srcpix, blit->dstpix);
u32_t srcpitchoffset;
dstpixmap = (blit->dstpix == (void*)-1) ? &scr_pixmap : blit->dstpix ;
srcpixmap = (blit->srcpix == (void*)-1) ? &scr_pixmap : blit->srcpix ;
//dbgprintf("srcpixmap: %x dstpixmap: %x\n",srcpixmap, dstpixmap);
//dbgprintf("dst.width: %d dst.height: %d\n", dstpixmap->width,dstpixmap->height);
//dbgprintf("src.width: %d src.height: %d\n", srcpixmap->width,srcpixmap->height);
//dbgprintf("srcpitch: %x dstpitch: %x\n",
// srcpixmap->pitch_offset,dstpixmap->pitch_offset);
src_clip.xmin = 0;
src_clip.ymin = 0;
src_clip.xmax = srcpixmap->width-1;
@ -692,14 +693,21 @@ int Blit(io_blit_t *blit)
{
u32_t *ring, write;
u32_t ifl;
/*
if( (srcpixmap->flags & PX_MEM_MASK)==PX_MEM_SYSTEM)
return blit_host(dstpixmap->pitch_offset,
blit->dst_x, blit->dst_y,
srcpixmap->mapped,
blit->src_x, blit->src_y,
blit->w, blit->h,
srcpixmap->pitch);
srcpixmap->pitch,
FALSE, 0 );
*/
if( (srcpixmap->flags & PX_MEM_MASK)==PX_MEM_SYSTEM)
srcpitchoffset = bind_pixmap(srcpixmap);
else
srcpitchoffset = srcpixmap->pitch_offset;
ifl = safe_cli();
@ -722,7 +730,7 @@ int Blit(io_blit_t *blit)
OUTREG(R5XX_DP_CNTL, R5XX_DST_X_LEFT_TO_RIGHT | R5XX_DST_Y_TOP_TO_BOTTOM);
OUTREG(R5XX_DST_PITCH_OFFSET, dstpixmap->pitch_offset);
OUTREG(R5XX_SRC_PITCH_OFFSET, srcpixmap->pitch_offset);
OUTREG(R5XX_SRC_PITCH_OFFSET, srcpitchoffset);
OUTREG(R5XX_SRC_Y_X,(blit->src_y<<16)|blit->src_x);
OUTREG(R5XX_DST_Y_X,(blit->dst_y<<16)|blit->dst_x);
@ -744,7 +752,7 @@ int Blit(io_blit_t *blit)
R5XX_ROP3_S
);
OUT_RING(srcpixmap->pitch_offset);
OUT_RING(srcpitchoffset);
OUT_RING(dstpixmap->pitch_offset);
OUT_RING((blit->src_x<<16)|blit->src_y);
@ -754,11 +762,15 @@ int Blit(io_blit_t *blit)
#endif
safe_sti(ifl);
if( (srcpixmap->flags & PX_MEM_MASK)==PX_MEM_SYSTEM)
R5xx2DIdleLocal();
};
return ERR_OK;
};
int BlitTransparent(io_blit_t *blit)
{
clip_t src_clip, dst_clip;
@ -766,6 +778,8 @@ int BlitTransparent(io_blit_t *blit)
local_pixmap_t *srcpixmap;
local_pixmap_t *dstpixmap;
u32_t srcpitchoffset;
// dbgprintf("Transblit src: %x dst: %x\n",blit->srcpix, blit->dstpix);
dstpixmap = (blit->dstpix == (void*)-1) ? &scr_pixmap : blit->dstpix ;
@ -792,8 +806,13 @@ int BlitTransparent(io_blit_t *blit)
&blit->w, &blit->h) )
{
u32_t *ring, write;
u32_t ifl;
u32_t ifl;
if( (srcpixmap->flags & PX_MEM_MASK)==PX_MEM_SYSTEM)
srcpitchoffset = bind_pixmap(srcpixmap);
else
srcpitchoffset = srcpixmap->pitch_offset;
ifl = safe_cli();
@ -819,7 +838,7 @@ int BlitTransparent(io_blit_t *blit)
OUTREG(R5XX_CLR_CMP_CNTL, R5XX_SRC_CMP_EQ_COLOR | R5XX_CLR_CMP_SRC_SOURCE);
OUTREG(R5XX_DST_PITCH_OFFSET, dstpixmap->pitch_offset);
OUTREG(R5XX_SRC_PITCH_OFFSET, srcpixmap->pitch_offset);
OUTREG(R5XX_SRC_PITCH_OFFSET, srcpitchoffset);
OUTREG(R5XX_SRC_Y_X,(blit->src_y<<16)|blit->src_x);
OUTREG(R5XX_DST_Y_X,(blit->dst_y<<16)|blit->dst_x);
@ -841,7 +860,7 @@ int BlitTransparent(io_blit_t *blit)
R5XX_ROP3_S
);
OUT_RING(srcpixmap->pitch_offset);
OUT_RING(srcpitchoffset);
OUT_RING(dstpixmap->pitch_offset);
OUT_RING(R5XX_CLR_CMP_SRC_SOURCE | R5XX_SRC_CMP_EQ_COLOR);
@ -857,78 +876,13 @@ int BlitTransparent(io_blit_t *blit)
#endif
safe_sti(ifl);
if( (srcpixmap->flags & PX_MEM_MASK)==PX_MEM_SYSTEM)
R5xx2DIdleLocal();
};
return ERR_OK;
}
#if 0
int LockPixmap(userpixmap_t *io)
{
pixmap_t *pixmap;
size_t size;
void *usermap;
dbgprintf("Lock pixmap %x\n", io->pixmap);
if(io->pixmap == (pixmap_t*)-1)
return ERR_PARAM;
else
pixmap = io->pixmap;
if( (pixmap->flags & 1) == PX_LOCK )
return ERR_PARAM;
size = (pixmap->pitch*pixmap->width+4095) & ~ 4095;
if (usermap = UserAlloc(size))
{
CommitPages(usermap, ((u32_t)pixmap->raw+rhd.PhisBase)|7|(1<<9), size);
pixmap->flags |= PX_LOCK;
pixmap->usermap = usermap;
io->usermap = usermap;
io->pitch = pixmap->pitch;
dbgprintf("map at %x\n", io->usermap);
return ERR_OK;
}
else
return ERR_PARAM;
};
int UnlockPixmap(userpixmap_t *io)
{
pixmap_t *pixmap;
size_t size;
dbgprintf("Unlock pixmap %x\n", io->pixmap);
if(io->pixmap == (pixmap_t*)-1)
return ERR_PARAM;
else
pixmap = io->pixmap;
if( (pixmap->flags & 1) != PX_LOCK )
return ERR_PARAM;
/* Sanity checks */
if( (pixmap->usermap == 0)||
((u32_t)pixmap->usermap >= 0x80000000) ||
((u32_t)pixmap->usermap & 4095)
)
return ERR_PARAM;
size = (pixmap->pitch*pixmap->width+4095) & ~ 4095;
UnmapPages(pixmap->usermap, size);
UserFree(pixmap->usermap);
pixmap->usermap = NULL;
pixmap->flags &= ~PX_LOCK;
io->usermap = NULL;
io->pitch = 0;
return ERR_OK;
};
#endif

128
programs/system/drivers/ati2d/ati2d.c
View File

@ -20,7 +20,8 @@
#include "radeon_reg.h"
#include "ati2d.h"
#include "atihw.h"
#include "accel_2d.h"
RHD_t rhd __attribute__ ((aligned (128))); /* reduce cache lock */
@ -29,7 +30,6 @@ static clip_t clip;
static local_pixmap_t scr_pixmap;
int Init3DEngine(RHDPtr info);
int __stdcall srv_2d(ioctl_t *io);
@ -43,7 +43,7 @@ u32_t __stdcall drvEntry(int action)
if(action != 1)
return 0;
if(!dbg_open("/rd/1/drivers/ati2d.log"))
if(!dbg_open("/bd0/2/ati2d.log"))
{
printf("Can't open /rd/1/drivers/ati2d.log\nExit\n");
return 0;
@ -63,14 +63,14 @@ u32_t __stdcall drvEntry(int action)
for(i=0;i<6;i++)
{
if(rhd.memBase[i])
dbgprintf("Memory base_%d 0x%x size 0x%x\n",
i,rhd.memBase[i],(1<<rhd.memsize[i]));
dbgprintf("Memory base_%d 0x%x size 0x%x\n",
i,rhd.memBase[i],(1<<rhd.memsize[i]));
};
for(i=0;i<6;i++)
{
if(rhd.ioBase[i])
dbgprintf("Io base_%d 0x%x size 0x%x\n",
i,rhd.ioBase[i],(1<<rhd.memsize[i]));
if(rhd.ioBase[i])
dbgprintf("Io base_%d 0x%x size 0x%x\n",
i,rhd.ioBase[i],(1<<rhd.memsize[i]));
};
if(!RHDPreInit())
return 0;
@ -92,70 +92,74 @@ u32_t __stdcall drvEntry(int action)
int __stdcall srv_2d(ioctl_t *io)
{
u32_t *inp;
u32_t *outp;
u32_t *inp;
u32_t *outp;
inp = io->input;
outp = io->output;
inp = io->input;
outp = io->output;
switch(io->io_code)
{
case SRV_GETVERSION:
if(io->out_size==4)
{
*outp = API_VERSION;
return 0;
}
break;
switch(io->io_code)
{
case SRV_GETVERSION:
if(io->out_size==4)
{
*outp = API_VERSION;
return 0;
}
break;
case PX_CREATE:
if(io->inp_size==7)
return CreatePixmap((pixmap_t*)inp);
break;
case PX_CREATE:
if(io->inp_size==7)
return CreatePixmap((pixmap_t*)inp);
break;
case PX_DESTROY:
if(io->inp_size==7)
return DestroyPixmap((pixmap_t*)inp);
break;
case PX_DESTROY:
if(io->inp_size==7)
return DestroyPixmap((pixmap_t*)inp);
break;
case PX_CLEAR:
if(io->inp_size==2)
return ClearPixmap((io_clear_t*)inp);
break;
case PX_CLEAR:
if(io->inp_size==2)
return ClearPixmap((io_clear_t*)inp);
break;
case PX_DRAW_RECT:
if(io->inp_size==7)
return DrawRect((io_draw_t*)inp);
break;
case PX_DRAW_RECT:
if(io->inp_size==7)
return DrawRect((io_draw_t*)inp);
break;
case PX_FILL_RECT:
if(io->inp_size==10)
return FillRect((io_fill_t*)inp);
break;
case PX_FILL_RECT:
if(io->inp_size==10)
return FillRect((io_fill_t*)inp);
break;
case PX_LINE:
if(io->inp_size==6)
return Line((io_draw_t*)inp);
break;
case PX_LINE:
if(io->inp_size==6)
return Line((io_draw_t*)inp);
break;
case PX_BLIT:
if(io->inp_size==8)
return Blit((io_blit_t*)inp);
break;
case PX_BLIT:
if(io->inp_size==8)
return Blit((io_blit_t*)inp);
break;
case PX_BLIT_TRANSPARENT:
if(io->inp_size==9)
return BlitTransparent((io_blit_t*)inp);
break;
case PX_BLIT_TRANSPARENT:
if(io->inp_size==9)
return BlitTransparent((io_blit_t*)inp);
break;
case PX_BLIT_ALPHA:
if(io->inp_size==9)
return RadeonComposite((io_blit_t*)inp);
break;
#if !R300_PIO
default:
return ERR_PARAM;
case PX_BLIT_ALPHA:
if(io->inp_size==9)
return RadeonComposite((io_blit_t*)inp);
break;
#endif
default:
return ERR_PARAM;
};
return ERR_PARAM;
}
@ -165,12 +169,18 @@ int __stdcall srv_2d(ioctl_t *io)
#include "ati_mem.c"
#include "init_cp.c"
#include "r500.inc"
#include "clip.inc"
#include "pixmap.inc"
#include "accel_2d.inc"
#if !R300_PIO
#include "init_3d.inc"
#include "blend.inc"
#endif

12
programs/system/drivers/ati2d/ati_mem.c
View File

@ -43,7 +43,7 @@ struct mem_block
{
struct mem_block *next;
struct mem_block *prev;
u32_t start;
addr_t start;
size_t size;
};
@ -168,13 +168,13 @@ int rhdInitHeap(RHDPtr rhdPtr)
return init_heap(&rhdPtr->fb_heap, base, rhdPtr->FbFreeSize);
};
void *rhd_mem_alloc(RHDPtr rhdPtr,int region, int size)
addr_t rhd_mem_alloc(RHDPtr rhdPtr,int region, int size)
{
struct mem_block *block, **heap;
heap = get_heap(rhdPtr, region);
if (!heap || !*heap)
return NULL;
return 0;
/* Make things easier on ourselves: all allocations at least
* 4k aligned.
@ -185,12 +185,12 @@ void *rhd_mem_alloc(RHDPtr rhdPtr,int region, int size)
block = alloc_block(*heap, size);
if (!block)
return NULL;
return 0;
return (void*)(block->start & ~USED_BLOCK);
return (block->start & ~USED_BLOCK);
}
int rhd_mem_free(RHDPtr rhdPtr, int region, void *offset)
int rhd_mem_free(RHDPtr rhdPtr, int region, addr_t offset)
{
struct mem_block *block, **heap;

87
programs/system/drivers/ati2d/ati2d.h → programs/system/drivers/ati2d/atihw.h
View File

@ -1,15 +1,11 @@
typedef void *pointer;
typedef unsigned int memType;
typedef struct { float hi, lo; } range;
#define PCI_CMD_STAT_REG 0x04
typedef enum
{
CHIP_FAMILY_UNKNOW,
@ -94,7 +90,6 @@ typedef enum
(info->ChipFamily == CHIP_FAMILY_RS480))
typedef enum {
CARD_PCI,
CARD_AGP,
@ -138,32 +133,28 @@ typedef struct
#define RADEON_DEFAULT_PCI_APER_SIZE 32 /* in MB */
#define RADEON_PCIGART_TABLE_SIZE (32*1024)
typedef struct RHDRec
{
u32_t MMIOBase;
u32_t MMIOMapSize;
addr_t MMIOBase;
size_t MMIOMapSize;
// CARD32 FbBase; /* map base of fb */
// u32_t PhisBase;
// u32_t FbIntAddress; /* card internal address of FB */
// u32_t FbMapSize;
addr_t FbFreeStart;
addr_t FbFreeSize;
u32_t FbFreeStart;
u32_t FbFreeSize;
/* visible part of the framebuffer */
/* visible part of the framebuffer */
// unsigned int FbScanoutStart;
// unsigned int FbScanoutSize;
u32_t LinearAddr; /* Frame buffer physical address */
// u32_t LinearAddr; /* Frame buffer physical address */
u32_t fbLocation;
addr_t fbLocation; /* Frame buffer physical address */
u32_t mc_fb_location;
u32_t mc_agp_location;
u32_t mc_agp_location_hi;
u32_t videoRam;
size_t videoRam;
u32_t MemCntl;
u32_t BusCntl;
@ -171,7 +162,6 @@ typedef struct RHDRec
unsigned long FbSecureSize; /* Size of secured fb area at end of
framebuffer */
RADEONChipFamily ChipFamily;
RADEONErrata ChipErrata;
@ -203,7 +193,10 @@ typedef struct RHDRec
u32_t displayWidth;
u32_t displayHeight;
u32_t gartSize;
u32_t *gart_table;
addr_t gart_table_dma;
addr_t gart_vm_start;
size_t gart_size;
u32_t* ringBase;
u32_t ring_rp;
@ -212,7 +205,6 @@ typedef struct RHDRec
u32_t ring_avail;
u32_t bufSize;
u32_t gartTexSize;
u32_t pciAperSize;
u32_t CPusecTimeout;
@ -249,39 +241,6 @@ extern RHD_t rhd;
#define R5XX_DP_BRUSH_BKGD_CLR 0x1478
#define R5XX_DP_BRUSH_FRGD_CLR 0x147c
#define R5XX_BRUSH_DATA0 0x1480
#define R5XX_BRUSH_DATA1 0x1484
# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
# define RADEON_GMC_BRUSH_NONE (15 << 4)
# define RADEON_GMC_DST_16BPP (4 << 8)
# define RADEON_GMC_DST_24BPP (5 << 8)
# define RADEON_GMC_DST_32BPP (6 << 8)
# define RADEON_GMC_DST_DATATYPE_SHIFT 8
# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
# define RADEON_GMC_WR_MSK_DIS (1 << 30)
# define RADEON_ROP3_S 0x00cc0000
# define RADEON_ROP3_P 0x00f00000
#define RADEON_CP_PACKET0 0x00000000
#define RADEON_CP_PACKET1 0x40000000
#define RADEON_CP_PACKET2 0x80000000
#define RADEON_CP_PACKET3 0xC0000000
# define RADEON_CNTL_PAINT 0x00009100
# define RADEON_CNTL_BITBLT 0x00009200
# define RADEON_CNTL_TRANBLT 0x00009C00
# define RADEON_CNTL_PAINT_POLYLINE 0x00009500
# define RADEON_CNTL_PAINT_MULTI 0x00009A00
#define CP_PACKET0(reg, n) \
(RADEON_CP_PACKET0 | ((n - 1 ) << 16) | ((reg) >> 2))
@ -413,10 +372,7 @@ _RHDRegMask(RHDPtr rhdPtr, u16_t offset, u32_t value, u32_t mask)
#define RHDRegMask(ptr, offset, value, mask) _RHDRegMask((ptr)->rhdPtr, (offset), (value), (mask))
RHDPtr FindPciDevice();
Bool RHDPreInit();
int rhdInitHeap(RHDPtr rhdPtr);
#define RHDFUNC(ptr)
@ -451,7 +407,6 @@ void __stdcall r500_SelectCursor(cursor_t *cursor);
void __stdcall r500_SetCursor(cursor_t *cursor, int x, int y);
void __stdcall r500_CursorRestore(int x, int y);
void R5xx2DInit();
typedef struct {
@ -542,3 +497,19 @@ typedef enum _PictFormatShort {
} PictFormatShort;
void dump_mem();
RHDPtr FindPciDevice();
Bool RHDPreInit();
void R5xx2DInit();
int Init3DEngine(RHDPtr info);
void init_gart(RHDPtr info);
int rhdInitHeap(RHDPtr rhdPtr);

302
programs/system/drivers/ati2d/init.c
View File

@ -3,7 +3,7 @@
static Bool rhdMapMMIO(RHDPtr rhdPtr)
{
rhdPtr->MMIOMapSize = 1 << rhdPtr->memsize[RHD_MMIO_BAR];
rhdPtr->MMIOBase = MapIoMem((void*)rhdPtr->memBase[RHD_MMIO_BAR],
rhdPtr->MMIOBase = MapIoMem(rhdPtr->memBase[RHD_MMIO_BAR],
rhdPtr->MMIOMapSize,PG_SW+PG_NOCACHE);
if( rhdPtr->MMIOBase==0)
return 0;
@ -108,61 +108,74 @@ static Bool avivo_get_mc_idle(RHDPtr info)
}
}
#define LOC_FB 0x1
#define LOC_AGP 0x2
#define LOC_FB 0x1
#define LOC_AGP 0x2
static void radeon_read_mc_fb_agp_location(RHDPtr info, int mask,
u32_t *fb_loc, u32_t *agp_loc, u32_t *agp_loc_hi)
{
if (info->ChipFamily >= CHIP_FAMILY_RV770) {
if (mask & LOC_FB)
*fb_loc = INREG(R700_MC_VM_FB_LOCATION);
if (mask & LOC_AGP) {
*agp_loc = INREG(R600_MC_VM_AGP_BOT);
*agp_loc_hi = INREG(R600_MC_VM_AGP_TOP);
}
} else if (info->ChipFamily >= CHIP_FAMILY_R600) {
if (mask & LOC_FB)
*fb_loc = INREG(R600_MC_VM_FB_LOCATION);
if (mask & LOC_AGP) {
*agp_loc = INREG(R600_MC_VM_AGP_BOT);
*agp_loc_hi = INREG(R600_MC_VM_AGP_TOP);
}
} else if (info->ChipFamily == CHIP_FAMILY_RV515) {
if (mask & LOC_FB)
*fb_loc = INMC(info, RV515_MC_FB_LOCATION);
if (mask & LOC_AGP) {
*agp_loc = INMC(info, RV515_MC_AGP_LOCATION);
*agp_loc_hi = 0;
}
} else if (info->ChipFamily == CHIP_FAMILY_RS600) {
if (mask & LOC_FB)
*fb_loc = INMC(info, RS600_MC_FB_LOCATION);
if (mask & LOC_AGP) {
*agp_loc = 0;//INMC(pScrn, RS600_MC_AGP_LOCATION);
*agp_loc_hi = 0;
}
} else if ((info->ChipFamily == CHIP_FAMILY_RS690) ||
(info->ChipFamily == CHIP_FAMILY_RS740)) {
if (mask & LOC_FB)
*fb_loc = INMC(info, RS690_MC_FB_LOCATION);
if (mask & LOC_AGP) {
*agp_loc = INMC(info, RS690_MC_AGP_LOCATION);
*agp_loc_hi = 0;
}
} else if (info->ChipFamily >= CHIP_FAMILY_R520) {
if (mask & LOC_FB)
*fb_loc = INMC(info, R520_MC_FB_LOCATION);
if (mask & LOC_AGP) {
*agp_loc = INMC(info, R520_MC_AGP_LOCATION);
*agp_loc_hi = 0;
}
} else {
if (mask & LOC_FB)
*fb_loc = INREG(RADEON_MC_FB_LOCATION);
if (mask & LOC_AGP)
*agp_loc = INREG(RADEON_MC_AGP_LOCATION);
if (info->ChipFamily >= CHIP_FAMILY_RV770)
{
if (mask & LOC_FB)
*fb_loc = INREG(R700_MC_VM_FB_LOCATION);
if (mask & LOC_AGP) {
*agp_loc = INREG(R600_MC_VM_AGP_BOT);
*agp_loc_hi = INREG(R600_MC_VM_AGP_TOP);
}
}
else if (info->ChipFamily >= CHIP_FAMILY_R600)
{
if (mask & LOC_FB)
*fb_loc = INREG(R600_MC_VM_FB_LOCATION);
if (mask & LOC_AGP) {
*agp_loc = INREG(R600_MC_VM_AGP_BOT);
*agp_loc_hi = INREG(R600_MC_VM_AGP_TOP);
}
}
else if (info->ChipFamily == CHIP_FAMILY_RV515)
{
if (mask & LOC_FB)
*fb_loc = INMC(info, RV515_MC_FB_LOCATION);
if (mask & LOC_AGP) {
*agp_loc = INMC(info, RV515_MC_AGP_LOCATION);
*agp_loc_hi = 0;
}
}
else if (info->ChipFamily == CHIP_FAMILY_RS600)
{
if (mask & LOC_FB)
*fb_loc = INMC(info, RS600_MC_FB_LOCATION);
if (mask & LOC_AGP) {
*agp_loc = 0;//INMC(pScrn, RS600_MC_AGP_LOCATION);
*agp_loc_hi = 0;
}
}
else if ((info->ChipFamily == CHIP_FAMILY_RS690) ||
(info->ChipFamily == CHIP_FAMILY_RS740))
{
if (mask & LOC_FB)
*fb_loc = INMC(info, RS690_MC_FB_LOCATION);
if (mask & LOC_AGP) {
*agp_loc = INMC(info, RS690_MC_AGP_LOCATION);
*agp_loc_hi = 0;
}
}
else if (info->ChipFamily >= CHIP_FAMILY_R520)
{
if (mask & LOC_FB)
*fb_loc = INMC(info, R520_MC_FB_LOCATION);
if (mask & LOC_AGP) {
*agp_loc = INMC(info, R520_MC_AGP_LOCATION);
*agp_loc_hi = 0;
}
}
else
{
if (mask & LOC_FB)
*fb_loc = INREG(RADEON_MC_FB_LOCATION);
if (mask & LOC_AGP)
*agp_loc = INREG(RADEON_MC_AGP_LOCATION);
}
}
@ -226,7 +239,6 @@ static void radeon_write_mc_fb_agp_location(RHDPtr info, int mask, u32_t fb_loc,
}
}
#if !R300_PIO
static void RADEONUpdateMemMapRegisters(RHDPtr info)
{
@ -259,7 +271,7 @@ static void RADEONUpdateMemMapRegisters(RHDPtr info)
tmp = INREG(AVIVO_D2CRTC_CONTROL);
usleep(10000);
usleep(1000);
timeout = 0;
while (!(avivo_get_mc_idle(info)))
{
@ -272,7 +284,7 @@ static void RADEONUpdateMemMapRegisters(RHDPtr info)
* to maybe hit the disk and continue trying to setup despite
* the MC being non-idle
*/
usleep(2000000);
usleep(20000);
}
usleep(10);
}
@ -386,7 +398,7 @@ static void RADEONUpdateMemMapRegisters(RHDPtr info)
OUTREG(RADEON_OV0_SCALE_CNTL, ov0_scale_cntl );
igp_no_mcfb:
igp_no_mcfb:
radeon_write_mc_fb_agp_location(info, LOC_AGP, 0,
info->mc_agp_location, 0);
/* Make sure map fully reached the chip */
@ -445,8 +457,6 @@ static void RADEONUpdateMemMapRegisters(RHDPtr info)
};
};
#endif
static void RADEONInitMemoryMap(RHDPtr info)
{
@ -536,17 +546,17 @@ static void RADEONInitMemoryMap(RHDPtr info)
* re-enabled later by the DRM
*/
// if (IS_AVIVO_VARIANT) {
// if (info->ChipFamily >= CHIP_FAMILY_R600) {
// OUTREG(R600_HDP_NONSURFACE_BASE, (info->mc_fb_location << 16) & 0xff0000);
// }
// else {
// OUTREG(AVIVO_HDP_FB_LOCATION, info->mc_fb_location);
// }
// info->mc_agp_location = 0x003f0000;
// }
// else
// info->mc_agp_location = 0xffffffc0;
if (IS_AVIVO_VARIANT) {
if (info->ChipFamily >= CHIP_FAMILY_R600) {
OUTREG(R600_HDP_NONSURFACE_BASE, (info->mc_fb_location << 16) & 0xff0000);
}
else {
OUTREG(AVIVO_HDP_FB_LOCATION, info->mc_fb_location);
}
info->mc_agp_location = 0x003f0000;
}
else
info->mc_agp_location = 0xffffffc0;
dbgprintf("RADEONInitMemoryMap() : \n");
dbgprintf(" mem_size : 0x%08x\n", (u32_t)mem_size);
@ -554,11 +564,9 @@ static void RADEONInitMemoryMap(RHDPtr info)
dbgprintf(" MC_AGP_LOCATION : 0x%08x\n", (unsigned)info->mc_agp_location);
dbgprintf(" FB_LOCATION : 0x%08x\n", (unsigned)info->fbLocation);
#if !R300_PIO
RADEONUpdateMemMapRegisters(info);
#endif
}
@ -788,11 +796,11 @@ static Bool RADEONPreInitVRAM(RHDPtr info)
info->videoRam &= ~1023;
info->FbMapSize = info->videoRam * 1024;
info->gartSize = RADEON_DEFAULT_GART_SIZE;
// info->gartSize = RADEON_DEFAULT_GART_SIZE;
info->ringSize = RADEON_DEFAULT_RING_SIZE;
info->bufSize = RADEON_DEFAULT_BUFFER_SIZE;
info->gartTexSize = info->gartSize - (info->ringSize + info->bufSize);
// info->gartTexSize = info->gartSize - (info->ringSize + info->bufSize);
info->pciAperSize = RADEON_DEFAULT_PCI_APER_SIZE;
info->CPusecTimeout = RADEON_DEFAULT_CP_TIMEOUT;
@ -878,7 +886,7 @@ static Bool RADEONPreInitChipType(RHDPtr rhdPtr)
rhdPtr->has_tcl = TRUE;
}
rhdPtr->LinearAddr = rhdPtr->memBase[RHD_FB_BAR];
// rhdPtr->LinearAddr = rhdPtr->memBase[RHD_FB_BAR];
return TRUE;
}
@ -979,15 +987,10 @@ Bool RHDPreInit()
}
dbgprintf("VideoRAM: %d kByte\n",rhd.videoRam);
// rhd.FbFreeStart = 0;
init_gart(&rhd);
rhd.FbFreeSize = rhd.videoRam << 10;
// if( !rhdMapFB(&rhd))
// return FALSE;
// rhd.FbScanoutStart = 0;
// rhd.FbScanoutSize = 8*1024*1024;
rhd.FbFreeStart = 10*1024*1024;
rhd.FbFreeSize = rhd.FbMapSize - rhd.FbFreeStart - rhd.FbSecureSize;
@ -1115,4 +1118,143 @@ static void init_pipes(RHDPtr info)
OUTREG(RADEON_RB3D_CNTL, 0);
};
#define RADEON_AIC_PT_BASE 0x01d8
#define RADEON_AIC_LO_ADDR 0x01dc
#define RADEON_AIC_HI_ADDR 0x01e0
#define RADEON_AIC_TLB_ADDR 0x01e4
#define RADEON_AIC_TLB_DATA 0x01e8
#define RADEON_PCIE_INDEX 0x0030
#define RADEON_PCIE_DATA 0x0034
#define RADEON_PCIE_TX_GART_CNTL 0x10
# define RADEON_PCIE_TX_GART_EN (1 << 0)
# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1)
# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1 << 1)
# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3 << 1)
# define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0 << 3)
# define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1 << 3)
# define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1 << 5)
# define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1 << 8)
#define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
#define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
#define RADEON_PCIE_TX_GART_BASE 0x13
#define RADEON_PCIE_TX_GART_START_LO 0x14
#define RADEON_PCIE_TX_GART_START_HI 0x15
#define RADEON_PCIE_TX_GART_END_LO 0x16
#define RADEON_PCIE_TX_GART_END_HI 0x17
#define RADEON_WRITE8(offset, val) \
*(volatile u8_t*)((addr_t)rhd.MMIOBase + (offset)) = val
#define RADEON_WRITE_PCIE( addr, val ) \
do { \
RADEON_WRITE8( RADEON_PCIE_INDEX, \
((addr) & 0xff)); \
OUTREG( RADEON_PCIE_DATA, (val) ); \
} while (0)
static u32_t RADEON_READ_PCIE(int addr)
{
RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
return INREG(RADEON_PCIE_DATA);
}
static void radeon_set_pciegart(RHDPtr info, int on)
{
u32_t tmp = RADEON_READ_PCIE(RADEON_PCIE_TX_GART_CNTL);
if (on)
{
RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
info->gart_vm_start);
RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
info->gart_table_dma);
RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
info->gart_vm_start);
RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
info->gart_vm_start + info->gart_size - 1);
// radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
OUTREG(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */
RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
RADEON_PCIE_TX_GART_EN);
} else {
RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
tmp & ~RADEON_PCIE_TX_GART_EN);
}
}
static void radeon_set_pcigart(RHDPtr info, int on)
{
u32_t tmp;
tmp = INREG(RADEON_AIC_CNTL);
if( on )
{
OUTREG(RADEON_AIC_CNTL, tmp | RADEON_PCIGART_TRANSLATE_EN);
/* set PCI GART page-table base address
*/
OUTREG(RADEON_AIC_PT_BASE, info->gart_table_dma);
/* set address range for PCI address translate
*/
OUTREG(RADEON_AIC_LO_ADDR, info->gart_vm_start);
OUTREG(RADEON_AIC_HI_ADDR, info->gart_vm_start
+ info->gart_size - 1);
/* Turn off AGP aperture -- is this required for PCI GART?
*/
// radeon_write_agp_location(dev_priv, 0xffffffc0);
OUTREG(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */
}
else OUTREG(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
}
void init_gart(RHDPtr info)
{
u32_t *pci_gart;
count_t pages;
info->gart_size = 16*1024*1024;
info->gart_vm_start = info->fbLocation + (info->videoRam << 10);
// info->gart_vm_start = info->fbLocation - info->gart_size;
// info->gart_table = (u32_t*)KernelAlloc( RADEON_PCIGART_TABLE_SIZE );
// if ( ! info->gart_table) {
// dbgprintf("cannot allocate PCI GART page!\n");
// return;
// }
// info->gart_table_dma = GetPgAddr(info->gart_table);
info->gart_table_dma = info->gart_vm_start - RADEON_PCIGART_TABLE_SIZE;
info->gart_table = (u32_t*)MapIoMem(info->gart_table_dma,
RADEON_PCIGART_TABLE_SIZE,
PG_SW | PG_NOCACHE);
pci_gart = info->gart_table;
memset(pci_gart, 0, RADEON_PCIGART_TABLE_SIZE);
__asm__ __volatile(
"wbinvd"
:::"memory");
radeon_set_pciegart(info, 1);
dbgprintf("gart size 0x%x\n", info->gart_size);
dbgprintf("gart base 0x%x\n", info->gart_vm_start);
dbgprintf("gart table 0x%x\n", info->gart_table);
dbgprintf("gart table dma 0x%x\n", info->gart_table_dma);
}

2
programs/system/drivers/ati2d/makefile
View File

@ -8,7 +8,7 @@ INCLUDES = -I ../include
HFILES:= ../include/types.h \
../include/syscall.h \
ati2d.h \
atihw.h \
pci.h \
accel_2d.h \
r5xx_regs.h \

3
programs/system/drivers/ati2d/pci.h
View File

@ -67,6 +67,9 @@ typedef struct
#define PCI_DFN_FROM_TAG(tag) (((tag) & 0x0000ff00u) >> 8)
#define PCI_CMD_STAT_REG 0x04
typedef unsigned int PCITAG;
extern inline PCITAG

285
programs/system/drivers/ati2d/pixmap.inc
View File

@ -1,98 +1,245 @@
int CreatePixmap(pixmap_t *io)
{
local_pixmap_t *pixmap;
local_pixmap_t *pixmap;
unsigned pitch;
size_t size;
unsigned pitch;
size_t size;
void *local;
addr_t mem_local = 0;
addr_t mem_dma = 0;
void *mapped;
if( (io->width == 0) || (io->width > 2048)||
(io->height == 0)|| (io->height > 2048))
{
if( (io->width == 0) || (io->width > 2048)||
(io->height == 0)|| (io->height > 2048))
{
dbgprintf("Invalid pixmap size w:%d h:%d\n", io->width,io->height);
return ERR_PARAM;
};
};
pitch = ((io->width+15)&~15)*4;
size = pitch*io->height;
pixmap = malloc(sizeof(local_pixmap_t));
dbgprintf("pitch = %d\n", pitch);
if(!pixmap)
return ERR_PARAM;
local = rhd_mem_alloc(&rhd,RHD_MEM_FB,size) ;
if ( !local)
{
pitch = ((io->width+15)&~15)*4;
size = pitch*io->height;
dbgprintf("pitch = %d\n", pitch);
if( (io->flags & PX_MEM_MASK) == PX_MEM_LOCAL ) {
mem_local = rhd_mem_alloc(&rhd,RHD_MEM_FB,size);
mem_dma = mem_local + rhd.fbLocation;
}
else
mem_local = mem_dma = AllocPages( size >> 12 );
if ( !mem_local) {
dbgprintf("Not enough memory for pixmap\n");
return ERR_PARAM;
};
pixmap = malloc(sizeof(local_pixmap_t));
if(!pixmap)
{
rhd_mem_free(&rhd, RHD_MEM_FB,local);
return ERR_PARAM;
}
else
{
void *mapped;
size = (size+4095) & ~ 4095;
if (mapped = UserAlloc(size))
{
CommitPages(mapped, ((u32_t)local+rhd.LinearAddr)|7|(1<<9), size);
io->mapped = mapped;
io->pitch = pitch;
io->handle = (u32_t)pixmap;
pixmap->width = io->width;
pixmap->height = io->height;
pixmap->format = PICT_a8r8g8b8;
pixmap->flags = PX_MEM_LOCAL; //io->flags;
pixmap->pitch = pitch;
pixmap->mapped = mapped;
pixmap->pitch_offset = ((pitch/64)<<22)| (((u32_t)local+rhd.fbLocation)>>10);
pixmap->local = local+rhd.fbLocation;
dbgprintf("pixmap.pitch_offset: %x\n", pixmap->pitch_offset);
dbgprintf("width: %d height: %d\n",pixmap->width,pixmap->height );
dbgprintf("map at %x\n", pixmap->mapped);
return ERR_OK;
};
rhd_mem_free(&rhd, RHD_MEM_FB,local);
free(pixmap);
};
return ERR_PARAM;
return ERR_PARAM;
};
pixmap->pitch_offset = ((pitch/64)<<22)| (mem_dma>>10);
pixmap->local = mem_dma;
size = (size+4095) & ~ 4095;
if (mapped = UserAlloc(size))
{
CommitPages(mapped, mem_dma|7|(1<<9), size);
io->mapped = mapped;
io->pitch = pitch;
io->handle = (u32_t)pixmap;
pixmap->width = io->width;
pixmap->height = io->height;
pixmap->format = PICT_a8r8g8b8;
pixmap->flags = io->flags;
pixmap->pitch = pitch;
pixmap->mapped = mapped;
dbgprintf("pixmap.pitch_offset: %x\n", pixmap->pitch_offset);
dbgprintf("width: %d height: %d\n",pixmap->width,pixmap->height );
dbgprintf("map at %x\n", pixmap->mapped);
return ERR_OK;
};
rhd_mem_free(&rhd, RHD_MEM_FB, mem_local);
free(pixmap);
return ERR_PARAM;
};
int DestroyPixmap( pixmap_t *io )
{
local_pixmap_t *pixmap;
size_t size;
local_pixmap_t *pixmap;
size_t size;
dbgprintf("Destroy pixmap %x\n", io->handle);
dbgprintf("Destroy pixmap %x\n", io->handle);
if(io->handle == -1)
if(io->handle == -1)
return ERR_PARAM;
else
else
pixmap = (local_pixmap_t*)io->handle;
size = (pixmap->pitch*pixmap->height+4095) & ~ 4095;
size = (pixmap->pitch*pixmap->height+4095) & ~ 4095;
UnmapPages(pixmap->mapped, size);
UserFree(pixmap->mapped);
UnmapPages(pixmap->mapped, size);
UserFree(pixmap->mapped);
rhd_mem_free(&rhd,RHD_MEM_FB,pixmap->local-rhd.fbLocation);
free(pixmap);
if( (io->flags & PX_MEM_MASK) == PX_MEM_LOCAL )
{
rhd_mem_free(&rhd,RHD_MEM_FB,pixmap->local-rhd.fbLocation);
}
else
{
count_t pages = size >> 12;
addr_t base = pixmap->local;
io->format = 0;
io->pitch = 0;
io->mapped = NULL;
io->handle = 0;
while( pages--)
{
addr_t tmp;
// __asm__ __volatile__(
// "call *__imp__PageFree"
// :"=eax" (tmp):"a" (base) );
// base+= 4096;
};
}
free(pixmap);
io->format = 0;
io->pitch = 0;
io->mapped = NULL;
io->handle = 0;
return ERR_OK;
};
# define ATI_PCIGART_PAGE_SIZE 4096 /**< PCI GART page size */
# define ATI_PCIGART_PAGE_MASK (~(ATI_PCIGART_PAGE_SIZE-1))
#define ATI_PCIE_WRITE 0x4
#define ATI_PCIE_READ 0x8
#define upper_32_bits(n) ((u32_t)(((n) >> 16) >> 16))
static addr_t bind_pixmap(local_pixmap_t *pixmap)
{
count_t pages;
addr_t base;
u32_t tmp;
u32_t *gart = rhd.gart_table;
pages = ((pixmap->height * pixmap->pitch+4095)&~4095)>>12;
base = pixmap->local;
// tmp = INREG(RADEON_AIC_CNTL);
// OUTREG(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
while(pages--)
{
addr_t page_base;
// *gart = base & ATI_PCIGART_PAGE_MASK;
// base+= 4096;
// gart++;
page_base = base & ATI_PCIGART_PAGE_MASK;
page_base >>= 8;
page_base |= (upper_32_bits(base) & 0xff) << 24;
page_base |= ATI_PCIE_READ | ATI_PCIE_WRITE;
*gart = page_base;
base+= 4096;
gart++;
}
__asm__ __volatile("sfence":::"memory");
// OUTREG(RADEON_AIC_CNTL, tmp | RADEON_PCIGART_TRANSLATE_EN);
// OUTREG(RADEON_AIC_PT_BASE, rhd.gart_table_dma);
RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
RADEON_PCIE_TX_GART_EN
| RADEON_PCIE_TX_GART_INVALIDATE_TLB);
return ((pixmap->pitch / 64) << 22) | (rhd.gart_vm_start >> 10);
}
#if 0
int LockPixmap(userpixmap_t *io)
{
pixmap_t *pixmap;
size_t size;
void *usermap;
dbgprintf("Lock pixmap %x\n", io->pixmap);
if(io->pixmap == (pixmap_t*)-1)
return ERR_PARAM;
else
pixmap = io->pixmap;
if( (pixmap->flags & 1) == PX_LOCK )
return ERR_PARAM;
size = (pixmap->pitch*pixmap->width+4095) & ~ 4095;
if (usermap = UserAlloc(size))
{
CommitPages(usermap, ((u32_t)pixmap->raw+rhd.PhisBase)|7|(1<<9), size);
pixmap->flags |= PX_LOCK;
pixmap->usermap = usermap;
io->usermap = usermap;
io->pitch = pixmap->pitch;
dbgprintf("map at %x\n", io->usermap);
return ERR_OK;
}
else
return ERR_PARAM;
};
int UnlockPixmap(userpixmap_t *io)
{
pixmap_t *pixmap;
size_t size;
dbgprintf("Unlock pixmap %x\n", io->pixmap);
if(io->pixmap == (pixmap_t*)-1)
return ERR_PARAM;
else
pixmap = io->pixmap;
if( (pixmap->flags & 1) != PX_LOCK )
return ERR_PARAM;
/* Sanity checks */
if( (pixmap->usermap == 0)||
((u32_t)pixmap->usermap >= 0x80000000) ||
((u32_t)pixmap->usermap & 4095)
)
return ERR_PARAM;
size = (pixmap->pitch*pixmap->width+4095) & ~ 4095;
UnmapPages(pixmap->usermap, size);
UserFree(pixmap->usermap);
pixmap->usermap = NULL;
pixmap->flags &= ~PX_LOCK;
io->usermap = NULL;
io->pitch = 0;
return ERR_OK;
};
#endif

4
programs/system/drivers/ati2d/r500.inc
View File

@ -175,9 +175,9 @@ void R5xx2DInit()
scr_pixmap.format = PICT_a8r8g8b8;
scr_pixmap.flags = PX_MEM_LOCAL;
scr_pixmap.pitch = rhd.displayWidth * 4 ;//screenpitch;
scr_pixmap.local = (void*)rhd.fbLocation;
scr_pixmap.local = rhd.fbLocation;
scr_pixmap.pitch_offset = rhd.dst_pitch_offset;
scr_pixmap.mapped = (void*)0;
scr_pixmap.mapped = 0;
R5xxFIFOWaitLocal(2);
OUTREG(R5XX_DST_PITCH_OFFSET,rhd.dst_pitch_offset);

246
programs/system/drivers/ati2d/syscall.h
View File

@ -1,246 +0,0 @@
#define OS_BASE 0x80000000
typedef struct
{
u32_t handle;
u32_t io_code;
void *input;
int inp_size;
void *output;
int out_size;
}ioctl_t;
typedef int (__stdcall *srv_proc_t)(ioctl_t *);
#define ERR_OK 0
#define ERR_PARAM -1
u32_t __stdcall drvEntry(int)__asm__("_drvEntry");
///////////////////////////////////////////////////////////////////////////////
#define STDCALL __attribute__ ((stdcall)) __attribute__ ((dllimport))
#define IMPORT __attribute__ ((dllimport))
///////////////////////////////////////////////////////////////////////////////
#define SysMsgBoardStr __SysMsgBoardStr
#define PciApi __PciApi
//#define RegService __RegService
#define CreateObject __CreateObject
#define DestroyObject __DestroyObject
///////////////////////////////////////////////////////////////////////////////
#define PG_SW 0x003
#define PG_NOCACHE 0x018
void* STDCALL AllocKernelSpace(size_t size)__asm__("AllocKernelSpace");
void* STDCALL KernelAlloc(size_t size)__asm__("KernelAlloc");
void* STDCALL KernelFree(void *mem)__asm__("KernelFree");
void* STDCALL UserAlloc(size_t size)__asm__("UserAlloc");
int STDCALL UserFree(void *mem)__asm__("UserFree");
void* STDCALL CreateRingBuffer(size_t size, u32_t map)__asm__("CreateRingBuffer");
u32_t STDCALL RegService(char *name, srv_proc_t proc)__asm__("RegService");
//void *CreateObject(u32 pid, size_t size);
//void *DestroyObject(void *obj);
u32_t STDCALL MapIoMem(void* base,size_t size,u32_t flags)__asm__("MapIoMem");
///////////////////////////////////////////////////////////////////////////////
static u32_t PciApi(int cmd);
u8_t STDCALL PciRead8 (u32_t bus, u32_t devfn, u32_t reg)__asm__("PciRead8");
u16_t STDCALL PciRead16(u32_t bus, u32_t devfn, u32_t reg)__asm__("PciRead16");
u32_t STDCALL PciRead32(u32_t bus, u32_t devfn, u32_t reg)__asm__("PciRead32");
#define pciReadLong(tag, reg) \
PciRead32(PCI_BUS_FROM_TAG(tag),PCI_DFN_FROM_TAG(tag),(reg))
#define pciReadByte(tag, reg) \
PciRead8(PCI_BUS_FROM_TAG(tag),PCI_DFN_FROM_TAG(tag),(reg))
u32_t STDCALL PciWrite8 (u32_t bus, u32_t devfn, u32_t reg,u8_t val) __asm__("PciWrite8");
u32_t STDCALL PciWrite16(u32_t bus, u32_t devfn, u32_t reg,u16_t val)__asm__("PciWrite16");
u32_t STDCALL PciWrite32(u32_t bus, u32_t devfn, u32_t reg,u32_t val)__asm__("PciWrite32");
#define pciWriteLong(tag, reg, val) \
PciWrite32(PCI_BUS_FROM_TAG(tag),PCI_DFN_FROM_TAG(tag),(reg),(val))
///////////////////////////////////////////////////////////////////////////////
int dbg_open(char *path);
int dbgprintf(const char* format, ...);
///////////////////////////////////////////////////////////////////////////////
extern inline int GetScreenSize()
{
int retval;
asm("int $0x40"
:"=a"(retval)
:"a"(61), "b"(1));
return retval;
}
extern inline int GetScreenBpp()
{
int retval;
asm("int $0x40"
:"=a"(retval)
:"a"(61), "b"(2));
return retval;
}
extern inline int GetScreenPitch()
{
int retval;
asm("int $0x40"
:"=a"(retval)
:"a"(61), "b"(3));
return retval;
}
extern inline u32_t GetPgAddr(void *mem)
{
u32_t retval;
__asm__ __volatile__ (
"call *__imp__GetPgAddr \n\t"
:"=eax" (retval)
:"a" (mem) );
return retval;
};
extern inline void CommitPages(void *mem, u32_t page, u32_t size)
{
size = (size+4095) & ~4095;
__asm__ __volatile__ (
"call *__imp__CommitPages"
::"a" (page), "b"(mem),"c"(size>>12)
:"edx" );
__asm__ __volatile__ ("":::"eax","ebx","ecx");
};
extern inline void UnmapPages(void *mem, size_t size)
{
size = (size+4095) & ~4095;
__asm__ __volatile__ (
"call *__imp__UnmapPages"
::"a" (mem), "c"(size>>12)
:"edx");
__asm__ __volatile__ ("":::"eax","ecx");
};
extern inline void usleep(u32_t delay)
{
if( !delay )
delay++;
delay*=2000;
__asm__ __volatile__ (
"1:\n\t"
"xorl %%eax, %%eax \n\t"
"cpuid \n\t"
"decl %%edi \n\t"
"jnz 1b"
:
:"D"(delay)
:"eax","ebx","ecx","edx");
};
extern inline u32_t __PciApi(int cmd)
{
u32_t retval;
__asm__ __volatile__ (
"call *__imp__PciApi"
:"=a" (retval)
:"a" (cmd)
:"memory");
return retval;
};
extern inline void* __CreateObject(u32_t pid, size_t size)
{
void *retval;
__asm__ __volatile__ (
"call *__imp__CreateObject \n\t"
:"=a" (retval)
:"a" (size),"b"(pid)
:"esi","edi", "memory");
return retval;
}
extern inline void *__DestroyObject(void *obj)
{
__asm__ __volatile__ (
"call *__imp__DestroyObject"
:
:"a" (obj)
:"ebx","edx","esi","edi", "memory");
}
/*
u32 __RegService(char *name, srv_proc_t proc)
{
u32 retval;
asm __volatile__
(
"pushl %%eax \n\t"
"pushl %%ebx \n\t"
"call *__imp__RegService \n\t"
:"=eax" (retval)
:"a" (proc), "b" (name)
:"memory"
);
return retval;
};
*/
extern inline u32_t safe_cli(void)
{
u32_t ifl;
__asm__ __volatile__ (
"pushf\n\t"
"popl %0\n\t"
"cli\n"
: "=r" (ifl));
return ifl;
}
extern inline void safe_sti(u32_t ifl)
{
__asm__ __volatile__ (
"pushl %0\n\t"
"popf\n"
: : "r" (ifl)
);
}
extern inline void __clear (void * dst, unsigned len)
{
u32_t tmp;
__asm__ __volatile__ (
// "xorl %%eax, %%eax \n\t"
"cld \n\t"
"rep stosb \n"
:"=c"(tmp),"=D"(tmp)
:"a"(0),"c"(len),"D"(dst));
__asm__ __volatile__ ("":::"ecx","edi");
};

19
programs/system/drivers/ati2d/types.h
View File

@ -1,19 +0,0 @@
#define NULL (void*)0
typedef unsigned char u8_t;
typedef unsigned short int u16_t;
typedef unsigned int u32_t;
typedef unsigned long long u64_t;
typedef unsigned int size_t;
typedef unsigned int count_t;
typedef unsigned int eflags_t;
typedef unsigned int Bool;
#define TRUE (Bool)1
#define FALSE (Bool)0

13
programs/system/drivers/include/syscall.h
View File

@ -49,10 +49,13 @@ void* STDCALL CreateRingBuffer(size_t size, u32_t map)__asm__("CreateRingBuffer"
u32_t STDCALL RegService(char *name, srv_proc_t proc)__asm__("RegService");
int STDCALL AttachIntHandler(int irq, void *handler, u32_t access) __asm__("AttachIntHandler");
//void *CreateObject(u32 pid, size_t size);
//void *DestroyObject(void *obj);
addr_t STDCALL MapIoMem(void* base,size_t size,u32_t flags)__asm__("MapIoMem");
addr_t STDCALL MapIoMem(addr_t base, size_t size, u32_t flags)__asm__("MapIoMem");
///////////////////////////////////////////////////////////////////////////////
@ -271,6 +274,14 @@ extern inline void out32(const u16_t port, const u32_t val)
("outl %1, %0\n" : : "dN"(port), "a"(val));
}
extern inline u8_t in8(const u16_t port)
{
u8_t tmp;
__asm__ __volatile__
("inb %1, %0\n" : "=a"(tmp) : "dN"(port));
return tmp;
};
extern inline u16_t in16(const u16_t port)
{
u16_t tmp;