kernel: enable write combined memory type
git-svn-id: svn://kolibrios.org@5360 a494cfbc-eb01-0410-851d-a64ba20cac60
This commit is contained in:
Sergey Semyonov (Serge)
parent
2ce28a4047
commit
75873a0173
@ -1,6 +1,6 @@
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; ;;
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;; Copyright (C) KolibriOS team 2004-2014. All rights reserved. ;;
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;; Copyright (C) KolibriOS team 2004-2015. All rights reserved. ;;
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;; Distributed under terms of the GNU General Public License ;;
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;; ;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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@ -98,6 +98,9 @@ CAPS_ALTMOVCR8 equ 74 ;
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MSR_SYSENTER_CS equ 0x174
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MSR_SYSENTER_ESP equ 0x175
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MSR_SYSENTER_EIP equ 0x176
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MSR_CR_PAT equ 0x277
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MSR_MTRR_DEF_TYPE equ 0x2FF
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MSR_AMD_EFER equ 0xC0000080 ; Extended Feature Enable Register
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MSR_AMD_STAR equ 0xC0000081 ; SYSCALL/SYSRET Target Address Register
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@ -276,7 +279,9 @@ PG_WRITE equ 0x002
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PG_USER equ 0x004
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PG_PCD equ 0x008
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PG_PWT equ 0x010
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PG_ACCESSED equ 0x020
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PG_DIRTY equ 0x040
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PG_PAT equ 0x080
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PG_GLOBAL equ 0x100
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PG_SHARED equ 0x200
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@ -287,6 +292,18 @@ PG_NOCACHE equ 0x018 ; (PG_PCD+PG_PWT)
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PDE_LARGE equ 0x080
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PAT_WB equ 0x000
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PAT_WC equ 0x008
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PAT_UCM equ 0x010
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PAT_UC equ 0x018
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PAT_TYPE_UC equ 0
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PAT_TYPE_WC equ 1
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PAT_TYPE_WB equ 6
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PAT_TYPE_UCM equ 7
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PAT_VALUE equ 0x00070106; (UC<<24)|(UCM<<16)|(WC<<8)|WB
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;;;;;;;;;;;boot time variables
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BOOT_BPP equ 0x9000 ;byte bits per pixel
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@ -25,21 +25,65 @@ endp
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; Helper procedure for mtrr_reconfigure and set_mtrr,
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; called before changes in MTRRs.
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; 1. disable and flush caches
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; 2. clear PGE bit in cr4
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; 3. flush TLB
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; 4. disable mtrr
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proc mtrr_begin_change
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mov eax, cr0
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or eax, 0x60000000 ;disable caching
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mov cr0, eax
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wbinvd ;invalidate cache
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bt [cpu_caps], CAPS_PGE
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jnc .cr3_flush
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mov eax, cr4
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btr eax, 7 ;clear cr4.PGE
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mov cr4, eax ;flush TLB
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jmp @F ;skip extra serialization
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.cr3_flush:
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mov eax, cr3
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mov cr3, eax ;flush TLB
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@@:
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mov ecx, MSR_MTRR_DEF_TYPE
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rdmsr
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btr eax, 11 ;clear enable flag
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wrmsr ;disable mtrr
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ret
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endp
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; Helper procedure for mtrr_reconfigure and set_mtrr,
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; called after changes in MTRRs.
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; 1. enable mtrr
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; 2. flush all caches
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; 3. flush TLB
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; 4. restore cr4.PGE flag, if required
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proc mtrr_end_change
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mov ecx, MSR_MTRR_DEF_TYPE
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rdmsr
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or ah, 8 ; enable variable-ranges MTRR
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and al, 0xF0 ; default memtype = UC
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wrmsr
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wbinvd ;again invalidate
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mov eax, cr0
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and eax, not 0x60000000
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mov cr0, eax ; enable caching
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mov eax, cr3
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mov cr3, eax ;flush tlb
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bt [cpu_caps], CAPS_PGE
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jnc @F
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mov eax, cr4
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bts eax, 7 ;set cr4.PGE flag
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mov cr4, eax
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@@:
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ret
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endp
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@ -695,12 +739,15 @@ end virtual
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jmp @b
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@@:
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; 9i. Configure MTRR_DEF_TYPE.
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mov ecx, 0x2FF
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rdmsr
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or ah, 8 ; enable variable-ranges MTRR
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and al, 0xF0; default memtype = UC
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; 9i. Check PAT support and reprogram PAT_MASR for write combining memory
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bt [cpu_caps], CAPS_PAT
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jnc @F
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mov ecx, MSR_CR_PAT
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mov eax, PAT_VALUE ;UC UCM WC WB
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mov edx, eax
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wrmsr
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@@:
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; 9j. Changes are done.
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call mtrr_end_change
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@ -738,7 +785,9 @@ proc set_mtrr stdcall, base:dword,size:dword,mem_type:dword
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ret
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.found:
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; found, write values
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push ecx
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call mtrr_begin_change
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pop ecx
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xor edx, edx
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mov eax, [base]
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or eax, [mem_type]
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@ -219,8 +219,6 @@ dll_cur_addr dd MIN_DEFAULT_DLL_ADDR
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align 4
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pte_valid_mask dd 0xFFFFF000+PG_SHARED+PG_NOCACHE+PG_UWR
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keyboard dd 1
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syslang dd 1
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@ -363,6 +361,7 @@ next_memblock rd 1
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mst MEM_STATE
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pte_valid_mask rd 1
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page_start rd 1
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page_end rd 1
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sys_page_map rd 1
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@ -351,17 +351,26 @@ high_code:
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mov fs, cx
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mov gs, bx
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xor eax, eax
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mov ebx, 0xFFFFF000+PG_SHARED+PG_NOCACHE+PG_UWR
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bt [cpu_caps], CAPS_PAT
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setc al
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shl eax, 7
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or ebx, eax
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mov eax, PG_GLOBAL
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bt [cpu_caps], CAPS_PGE
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jnc @F
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or [sys_proc+PROC.pdt_0+(OS_BASE shr 20)], eax
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or [pte_valid_mask], eax
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or ebx, eax
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mov ebx, cr4
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or ebx, CR4_PGE
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mov cr4, ebx
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mov eax, cr4
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or eax, CR4_PGE
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mov cr4, eax
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@@:
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mov [pte_valid_mask], ebx
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xor eax, eax
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mov dword [sys_proc+PROC.pdt_0], eax
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mov dword [sys_proc+PROC.pdt_0+4], eax
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