8a54b2712a
git-svn-id: svn://kolibrios.org@6110 a494cfbc-eb01-0410-851d-a64ba20cac60
367 lines
8.4 KiB
C
367 lines
8.4 KiB
C
/*
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* Copyright © 2007 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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*
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include <string.h>
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#include <stdlib.h>
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#include <stdint.h>
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#include <assert.h>
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#include <errno.h>
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#include <drm.h>
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#include <i915_drm.h>
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//#include <pciaccess.h>
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#include "libdrm_macros.h"
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#include "intel_bufmgr.h"
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#include "intel_bufmgr_priv.h"
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#include "xf86drm.h"
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/** @file intel_bufmgr.c
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*
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* Convenience functions for buffer management methods.
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*/
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drm_intel_bo *
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drm_intel_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name,
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unsigned long size, unsigned int alignment)
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{
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return bufmgr->bo_alloc(bufmgr, name, size, alignment);
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}
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drm_intel_bo *
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drm_intel_bo_alloc_for_render(drm_intel_bufmgr *bufmgr, const char *name,
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unsigned long size, unsigned int alignment)
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{
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return bufmgr->bo_alloc_for_render(bufmgr, name, size, alignment);
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}
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drm_intel_bo *
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drm_intel_bo_alloc_userptr(drm_intel_bufmgr *bufmgr,
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const char *name, void *addr,
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uint32_t tiling_mode,
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uint32_t stride,
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unsigned long size,
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unsigned long flags)
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{
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if (bufmgr->bo_alloc_userptr)
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return bufmgr->bo_alloc_userptr(bufmgr, name, addr, tiling_mode,
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stride, size, flags);
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return NULL;
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}
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drm_intel_bo *
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drm_intel_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name,
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int x, int y, int cpp, uint32_t *tiling_mode,
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unsigned long *pitch, unsigned long flags)
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{
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return bufmgr->bo_alloc_tiled(bufmgr, name, x, y, cpp,
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tiling_mode, pitch, flags);
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}
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void
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drm_intel_bo_reference(drm_intel_bo *bo)
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{
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bo->bufmgr->bo_reference(bo);
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}
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void
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drm_intel_bo_unreference(drm_intel_bo *bo)
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{
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if (bo == NULL)
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return;
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bo->bufmgr->bo_unreference(bo);
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}
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int
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drm_intel_bo_map(drm_intel_bo *buf, int write_enable)
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{
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return buf->bufmgr->bo_map(buf, write_enable);
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}
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int
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drm_intel_bo_unmap(drm_intel_bo *buf)
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{
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return buf->bufmgr->bo_unmap(buf);
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}
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int
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drm_intel_bo_subdata(drm_intel_bo *bo, unsigned long offset,
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unsigned long size, const void *data)
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{
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return bo->bufmgr->bo_subdata(bo, offset, size, data);
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}
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int
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drm_intel_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
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unsigned long size, void *data)
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{
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int ret;
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if (bo->bufmgr->bo_get_subdata)
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return bo->bufmgr->bo_get_subdata(bo, offset, size, data);
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if (size == 0 || data == NULL)
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return 0;
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ret = drm_intel_bo_map(bo, 0);
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if (ret)
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return ret;
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memcpy(data, (unsigned char *)bo->virtual + offset, size);
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drm_intel_bo_unmap(bo);
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return 0;
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}
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void
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drm_intel_bo_wait_rendering(drm_intel_bo *bo)
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{
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bo->bufmgr->bo_wait_rendering(bo);
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}
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void
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drm_intel_bufmgr_destroy(drm_intel_bufmgr *bufmgr)
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{
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bufmgr->destroy(bufmgr);
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}
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int
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drm_intel_bo_exec(drm_intel_bo *bo, int used,
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drm_clip_rect_t * cliprects, int num_cliprects, int DR4)
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{
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return bo->bufmgr->bo_exec(bo, used, cliprects, num_cliprects, DR4);
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}
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int
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drm_intel_bo_mrb_exec(drm_intel_bo *bo, int used,
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drm_clip_rect_t *cliprects, int num_cliprects, int DR4,
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unsigned int rings)
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{
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if (bo->bufmgr->bo_mrb_exec)
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return bo->bufmgr->bo_mrb_exec(bo, used,
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cliprects, num_cliprects, DR4,
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rings);
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switch (rings) {
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case I915_EXEC_DEFAULT:
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case I915_EXEC_RENDER:
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return bo->bufmgr->bo_exec(bo, used,
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cliprects, num_cliprects, DR4);
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default:
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return -ENODEV;
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}
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}
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void
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drm_intel_bufmgr_set_debug(drm_intel_bufmgr *bufmgr, int enable_debug)
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{
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bufmgr->debug = enable_debug;
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}
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int
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drm_intel_bufmgr_check_aperture_space(drm_intel_bo ** bo_array, int count)
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{
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return bo_array[0]->bufmgr->check_aperture_space(bo_array, count);
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}
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int
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drm_intel_bo_flink(drm_intel_bo *bo, uint32_t * name)
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{
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if (bo->bufmgr->bo_flink)
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return bo->bufmgr->bo_flink(bo, name);
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return -ENODEV;
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}
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int
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drm_intel_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
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drm_intel_bo *target_bo, uint32_t target_offset,
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uint32_t read_domains, uint32_t write_domain)
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{
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return bo->bufmgr->bo_emit_reloc(bo, offset,
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target_bo, target_offset,
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read_domains, write_domain);
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}
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/* For fence registers, not GL fences */
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int
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drm_intel_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
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drm_intel_bo *target_bo, uint32_t target_offset,
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uint32_t read_domains, uint32_t write_domain)
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{
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return bo->bufmgr->bo_emit_reloc_fence(bo, offset,
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target_bo, target_offset,
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read_domains, write_domain);
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}
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int
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drm_intel_bo_pin(drm_intel_bo *bo, uint32_t alignment)
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{
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if (bo->bufmgr->bo_pin)
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return bo->bufmgr->bo_pin(bo, alignment);
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return -ENODEV;
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}
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int
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drm_intel_bo_unpin(drm_intel_bo *bo)
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{
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if (bo->bufmgr->bo_unpin)
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return bo->bufmgr->bo_unpin(bo);
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return -ENODEV;
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}
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int
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drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
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uint32_t stride)
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{
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if (bo->bufmgr->bo_set_tiling)
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return bo->bufmgr->bo_set_tiling(bo, tiling_mode, stride);
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*tiling_mode = I915_TILING_NONE;
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return 0;
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}
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int
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drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
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uint32_t * swizzle_mode)
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{
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if (bo->bufmgr->bo_get_tiling)
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return bo->bufmgr->bo_get_tiling(bo, tiling_mode, swizzle_mode);
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*tiling_mode = I915_TILING_NONE;
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*swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
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return 0;
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}
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int
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drm_intel_bo_set_softpin_offset(drm_intel_bo *bo, uint64_t offset)
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{
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if (bo->bufmgr->bo_set_softpin_offset)
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return bo->bufmgr->bo_set_softpin_offset(bo, offset);
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return -ENODEV;
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}
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int
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drm_intel_bo_disable_reuse(drm_intel_bo *bo)
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{
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if (bo->bufmgr->bo_disable_reuse)
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return bo->bufmgr->bo_disable_reuse(bo);
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return 0;
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}
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int
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drm_intel_bo_is_reusable(drm_intel_bo *bo)
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{
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if (bo->bufmgr->bo_is_reusable)
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return bo->bufmgr->bo_is_reusable(bo);
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return 0;
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}
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int
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drm_intel_bo_busy(drm_intel_bo *bo)
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{
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if (bo->bufmgr->bo_busy)
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return bo->bufmgr->bo_busy(bo);
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return 0;
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}
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int
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drm_intel_bo_madvise(drm_intel_bo *bo, int madv)
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{
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if (bo->bufmgr->bo_madvise)
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return bo->bufmgr->bo_madvise(bo, madv);
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return -1;
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}
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int
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drm_intel_bo_use_48b_address_range(drm_intel_bo *bo, uint32_t enable)
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{
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if (bo->bufmgr->bo_use_48b_address_range) {
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bo->bufmgr->bo_use_48b_address_range(bo, enable);
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return 0;
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}
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return -ENODEV;
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}
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int
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drm_intel_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
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{
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return bo->bufmgr->bo_references(bo, target_bo);
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}
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#if 0
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static size_t
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drm_intel_probe_agp_aperture_size(int fd)
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{
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struct pci_device *pci_dev;
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size_t size = 0;
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int ret;
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ret = pci_system_init();
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if (ret)
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goto err;
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/* XXX handle multiple adaptors? */
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pci_dev = pci_device_find_by_slot(0, 0, 2, 0);
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if (pci_dev == NULL)
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goto err;
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ret = pci_device_probe(pci_dev);
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if (ret)
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goto err;
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size = pci_dev->regions[2].size;
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err:
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pci_system_cleanup ();
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return size;
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}
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#endif
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int
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drm_intel_get_aperture_sizes(int fd, size_t *mappable, size_t *total)
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{
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struct drm_i915_gem_get_aperture aperture;
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int ret;
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ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);
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if (ret)
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return ret;
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/* XXX add a query for the kernel value? */
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*mappable = 512 * 1024 * 1024; /* minimum possible value */
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*total = aperture.aper_size;
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return 0;
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}
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