1148 lines
34 KiB
C
1148 lines
34 KiB
C
/*
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* Intel GTT (Graphics Translation Table) routines
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*
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* Caveat: This driver implements the linux agp interface, but this is far from
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* a agp driver! GTT support ended up here for purely historical reasons: The
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* old userspace intel graphics drivers needed an interface to map memory into
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* the GTT. And the drm provides a default interface for graphic devices sitting
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* on an agp port. So it made sense to fake the GTT support as an agp port to
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* avoid having to create a new api.
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*
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* With gem this does not make much sense anymore, just needlessly complicates
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* the code. But as long as the old graphics stack is still support, it's stuck
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* here.
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*
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* /fairy-tale-mode off
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*/
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#include <linux/module.h>
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#include <errno-base.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/export.h>
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//#include <linux/pagemap.h>
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//#include <linux/agp_backend.h>
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//#include <asm/smp.h>
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#include <linux/spinlock.h>
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#include "agp.h"
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#include "intel-agp.h"
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#include "intel-gtt.h"
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#include <syscall.h>
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struct pci_dev *
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pci_get_device(unsigned int vendor, unsigned int device, struct pci_dev *from);
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#define PCI_VENDOR_ID_INTEL 0x8086
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#define PCI_DEVICE_ID_INTEL_82830_HB 0x3575
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#define PCI_DEVICE_ID_INTEL_82845G_HB 0x2560
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#define PCI_DEVICE_ID_INTEL_82915G_IG 0x2582
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#define PCI_DEVICE_ID_INTEL_82915GM_IG 0x2592
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#define PCI_DEVICE_ID_INTEL_82945G_IG 0x2772
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#define PCI_DEVICE_ID_INTEL_82945GM_IG 0x27A2
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#define AGP_NORMAL_MEMORY 0
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#define AGP_USER_TYPES (1 << 16)
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#define AGP_USER_MEMORY (AGP_USER_TYPES)
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#define AGP_USER_CACHED_MEMORY (AGP_USER_TYPES + 1)
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/*
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* If we have Intel graphics, we're not going to have anything other than
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* an Intel IOMMU. So make the correct use of the PCI DMA API contingent
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* on the Intel IOMMU support (CONFIG_INTEL_IOMMU).
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* Only newer chipsets need to bother with this, of course.
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*/
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#ifdef CONFIG_INTEL_IOMMU
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#define USE_PCI_DMA_API 1
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#else
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#define USE_PCI_DMA_API 0
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#endif
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struct intel_gtt_driver {
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unsigned int gen : 8;
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unsigned int is_g33 : 1;
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unsigned int is_pineview : 1;
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unsigned int is_ironlake : 1;
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unsigned int has_pgtbl_enable : 1;
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unsigned int dma_mask_size : 8;
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/* Chipset specific GTT setup */
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int (*setup)(void);
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/* This should undo anything done in ->setup() save the unmapping
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* of the mmio register file, that's done in the generic code. */
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void (*cleanup)(void);
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void (*write_entry)(dma_addr_t addr, unsigned int entry, unsigned int flags);
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/* Flags is a more or less chipset specific opaque value.
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* For chipsets that need to support old ums (non-gem) code, this
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* needs to be identical to the various supported agp memory types! */
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bool (*check_flags)(unsigned int flags);
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void (*chipset_flush)(void);
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};
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static struct _intel_private {
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struct intel_gtt base;
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const struct intel_gtt_driver *driver;
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struct pci_dev *pcidev; /* device one */
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struct pci_dev *bridge_dev;
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u8 __iomem *registers;
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phys_addr_t gtt_bus_addr;
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u32 PGETBL_save;
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u32 __iomem *gtt; /* I915G */
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bool clear_fake_agp; /* on first access via agp, fill with scratch */
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int num_dcache_entries;
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void __iomem *i9xx_flush_page;
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char *i81x_gtt_table;
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struct resource ifp_resource;
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int resource_valid;
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struct page *scratch_page;
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int refcount;
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} intel_private;
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#define INTEL_GTT_GEN intel_private.driver->gen
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#define IS_G33 intel_private.driver->is_g33
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#define IS_PINEVIEW intel_private.driver->is_pineview
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#define IS_IRONLAKE intel_private.driver->is_ironlake
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#define HAS_PGTBL_EN intel_private.driver->has_pgtbl_enable
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static int intel_gtt_setup_scratch_page(void)
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{
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dma_addr_t dma_addr;
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dma_addr = AllocPage();
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if (dma_addr == 0)
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return -ENOMEM;
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intel_private.base.scratch_page_dma = dma_addr;
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intel_private.scratch_page = NULL;
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return 0;
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}
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static unsigned int intel_gtt_stolen_size(void)
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{
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u16 gmch_ctrl;
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u8 rdct;
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int local = 0;
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static const int ddt[4] = { 0, 16, 32, 64 };
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unsigned int stolen_size = 0;
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if (INTEL_GTT_GEN == 1)
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return 0; /* no stolen mem on i81x */
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pci_read_config_word(intel_private.bridge_dev,
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I830_GMCH_CTRL, &gmch_ctrl);
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if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
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intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
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switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
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case I830_GMCH_GMS_STOLEN_512:
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stolen_size = KB(512);
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break;
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case I830_GMCH_GMS_STOLEN_1024:
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stolen_size = MB(1);
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break;
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case I830_GMCH_GMS_STOLEN_8192:
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stolen_size = MB(8);
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break;
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case I830_GMCH_GMS_LOCAL:
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rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
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stolen_size = (I830_RDRAM_ND(rdct) + 1) *
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MB(ddt[I830_RDRAM_DDT(rdct)]);
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local = 1;
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break;
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default:
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stolen_size = 0;
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break;
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}
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} else if (INTEL_GTT_GEN == 6) {
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/*
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* SandyBridge has new memory control reg at 0x50.w
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*/
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u16 snb_gmch_ctl;
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pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
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switch (snb_gmch_ctl & SNB_GMCH_GMS_STOLEN_MASK) {
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case SNB_GMCH_GMS_STOLEN_32M:
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stolen_size = MB(32);
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break;
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case SNB_GMCH_GMS_STOLEN_64M:
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stolen_size = MB(64);
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break;
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case SNB_GMCH_GMS_STOLEN_96M:
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stolen_size = MB(96);
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break;
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case SNB_GMCH_GMS_STOLEN_128M:
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stolen_size = MB(128);
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break;
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case SNB_GMCH_GMS_STOLEN_160M:
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stolen_size = MB(160);
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break;
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case SNB_GMCH_GMS_STOLEN_192M:
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stolen_size = MB(192);
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break;
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case SNB_GMCH_GMS_STOLEN_224M:
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stolen_size = MB(224);
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break;
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case SNB_GMCH_GMS_STOLEN_256M:
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stolen_size = MB(256);
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break;
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case SNB_GMCH_GMS_STOLEN_288M:
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stolen_size = MB(288);
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break;
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case SNB_GMCH_GMS_STOLEN_320M:
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stolen_size = MB(320);
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break;
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case SNB_GMCH_GMS_STOLEN_352M:
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stolen_size = MB(352);
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break;
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case SNB_GMCH_GMS_STOLEN_384M:
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stolen_size = MB(384);
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break;
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case SNB_GMCH_GMS_STOLEN_416M:
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stolen_size = MB(416);
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break;
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case SNB_GMCH_GMS_STOLEN_448M:
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stolen_size = MB(448);
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break;
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case SNB_GMCH_GMS_STOLEN_480M:
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stolen_size = MB(480);
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break;
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case SNB_GMCH_GMS_STOLEN_512M:
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stolen_size = MB(512);
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break;
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}
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} else {
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switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
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case I855_GMCH_GMS_STOLEN_1M:
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stolen_size = MB(1);
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break;
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case I855_GMCH_GMS_STOLEN_4M:
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stolen_size = MB(4);
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break;
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case I855_GMCH_GMS_STOLEN_8M:
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stolen_size = MB(8);
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break;
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case I855_GMCH_GMS_STOLEN_16M:
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stolen_size = MB(16);
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break;
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case I855_GMCH_GMS_STOLEN_32M:
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stolen_size = MB(32);
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break;
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case I915_GMCH_GMS_STOLEN_48M:
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stolen_size = MB(48);
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break;
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case I915_GMCH_GMS_STOLEN_64M:
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stolen_size = MB(64);
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break;
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case G33_GMCH_GMS_STOLEN_128M:
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stolen_size = MB(128);
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break;
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case G33_GMCH_GMS_STOLEN_256M:
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stolen_size = MB(256);
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break;
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case INTEL_GMCH_GMS_STOLEN_96M:
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stolen_size = MB(96);
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break;
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case INTEL_GMCH_GMS_STOLEN_160M:
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stolen_size = MB(160);
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break;
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case INTEL_GMCH_GMS_STOLEN_224M:
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stolen_size = MB(224);
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break;
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case INTEL_GMCH_GMS_STOLEN_352M:
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stolen_size = MB(352);
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break;
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default:
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stolen_size = 0;
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break;
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}
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}
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if (stolen_size > 0) {
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dev_info(&intel_private.bridge_dev->dev, "detected %dK %s memory\n",
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stolen_size / KB(1), local ? "local" : "stolen");
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} else {
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dev_info(&intel_private.bridge_dev->dev,
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"no pre-allocated video memory detected\n");
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stolen_size = 0;
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}
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return stolen_size;
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}
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static void i965_adjust_pgetbl_size(unsigned int size_flag)
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{
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u32 pgetbl_ctl, pgetbl_ctl2;
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/* ensure that ppgtt is disabled */
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pgetbl_ctl2 = readl(intel_private.registers+I965_PGETBL_CTL2);
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pgetbl_ctl2 &= ~I810_PGETBL_ENABLED;
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writel(pgetbl_ctl2, intel_private.registers+I965_PGETBL_CTL2);
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/* write the new ggtt size */
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pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
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pgetbl_ctl &= ~I965_PGETBL_SIZE_MASK;
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pgetbl_ctl |= size_flag;
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writel(pgetbl_ctl, intel_private.registers+I810_PGETBL_CTL);
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}
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static unsigned int i965_gtt_total_entries(void)
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{
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int size;
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u32 pgetbl_ctl;
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u16 gmch_ctl;
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pci_read_config_word(intel_private.bridge_dev,
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I830_GMCH_CTRL, &gmch_ctl);
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if (INTEL_GTT_GEN == 5) {
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switch (gmch_ctl & G4x_GMCH_SIZE_MASK) {
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case G4x_GMCH_SIZE_1M:
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case G4x_GMCH_SIZE_VT_1M:
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i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1MB);
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break;
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case G4x_GMCH_SIZE_VT_1_5M:
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i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1_5MB);
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break;
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case G4x_GMCH_SIZE_2M:
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case G4x_GMCH_SIZE_VT_2M:
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i965_adjust_pgetbl_size(I965_PGETBL_SIZE_2MB);
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break;
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}
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}
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pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
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switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
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case I965_PGETBL_SIZE_128KB:
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size = KB(128);
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break;
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case I965_PGETBL_SIZE_256KB:
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size = KB(256);
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break;
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case I965_PGETBL_SIZE_512KB:
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size = KB(512);
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break;
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/* GTT pagetable sizes bigger than 512KB are not possible on G33! */
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case I965_PGETBL_SIZE_1MB:
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size = KB(1024);
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break;
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case I965_PGETBL_SIZE_2MB:
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size = KB(2048);
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break;
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case I965_PGETBL_SIZE_1_5MB:
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size = KB(1024 + 512);
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break;
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default:
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dev_info(&intel_private.pcidev->dev,
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"unknown page table size, assuming 512KB\n");
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size = KB(512);
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}
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return size/4;
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}
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static unsigned int intel_gtt_total_entries(void)
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{
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int size;
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if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5)
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return i965_gtt_total_entries();
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else if (INTEL_GTT_GEN == 6) {
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u16 snb_gmch_ctl;
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pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
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switch (snb_gmch_ctl & SNB_GTT_SIZE_MASK) {
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default:
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case SNB_GTT_SIZE_0M:
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printk(KERN_ERR "Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl);
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size = MB(0);
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break;
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case SNB_GTT_SIZE_1M:
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size = MB(1);
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break;
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case SNB_GTT_SIZE_2M:
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size = MB(2);
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break;
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}
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return size/4;
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} else {
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/* On previous hardware, the GTT size was just what was
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* required to map the aperture.
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*/
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return intel_private.base.gtt_mappable_entries;
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}
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}
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static unsigned int intel_gtt_mappable_entries(void)
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{
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unsigned int aperture_size;
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if (INTEL_GTT_GEN == 1) {
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u32 smram_miscc;
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pci_read_config_dword(intel_private.bridge_dev,
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I810_SMRAM_MISCC, &smram_miscc);
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if ((smram_miscc & I810_GFX_MEM_WIN_SIZE)
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== I810_GFX_MEM_WIN_32M)
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aperture_size = MB(32);
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else
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aperture_size = MB(64);
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} else if (INTEL_GTT_GEN == 2) {
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u16 gmch_ctrl;
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pci_read_config_word(intel_private.bridge_dev,
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I830_GMCH_CTRL, &gmch_ctrl);
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if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_64M)
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aperture_size = MB(64);
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else
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aperture_size = MB(128);
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} else {
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/* 9xx supports large sizes, just look at the length */
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aperture_size = pci_resource_len(intel_private.pcidev, 2);
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}
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return aperture_size >> PAGE_SHIFT;
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}
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static void intel_gtt_teardown_scratch_page(void)
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{
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// FreePage(intel_private.scratch_page_dma);
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}
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static void intel_gtt_cleanup(void)
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{
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intel_private.driver->cleanup();
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iounmap(intel_private.gtt);
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iounmap(intel_private.registers);
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intel_gtt_teardown_scratch_page();
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}
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static int intel_gtt_init(void)
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{
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u32 gma_addr;
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u32 gtt_map_size;
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int ret;
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ret = intel_private.driver->setup();
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if (ret != 0)
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{
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return ret;
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};
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|
|
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intel_private.base.gtt_mappable_entries = intel_gtt_mappable_entries();
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intel_private.base.gtt_total_entries = intel_gtt_total_entries();
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|
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/* save the PGETBL reg for resume */
|
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intel_private.PGETBL_save =
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readl(intel_private.registers+I810_PGETBL_CTL)
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& ~I810_PGETBL_ENABLED;
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/* we only ever restore the register when enabling the PGTBL... */
|
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if (HAS_PGTBL_EN)
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intel_private.PGETBL_save |= I810_PGETBL_ENABLED;
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dev_info(&intel_private.bridge_dev->dev,
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"detected gtt size: %dK total, %dK mappable\n",
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intel_private.base.gtt_total_entries * 4,
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intel_private.base.gtt_mappable_entries * 4);
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gtt_map_size = intel_private.base.gtt_total_entries * 4;
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|
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intel_private.gtt = NULL;
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// if (INTEL_GTT_GEN < 6 && INTEL_GTT_GEN > 2)
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// intel_private.gtt = ioremap_wc(intel_private.gtt_bus_addr,
|
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// gtt_map_size);
|
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if (intel_private.gtt == NULL)
|
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intel_private.gtt = ioremap(intel_private.gtt_bus_addr,
|
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gtt_map_size);
|
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if (intel_private.gtt == NULL) {
|
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intel_private.driver->cleanup();
|
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iounmap(intel_private.registers);
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return -ENOMEM;
|
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}
|
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intel_private.base.gtt = intel_private.gtt;
|
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|
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asm volatile("wbinvd");
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|
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intel_private.base.stolen_size = intel_gtt_stolen_size();
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|
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intel_private.base.needs_dmar = USE_PCI_DMA_API && INTEL_GTT_GEN > 2;
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|
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ret = intel_gtt_setup_scratch_page();
|
|
if (ret != 0) {
|
|
intel_gtt_cleanup();
|
|
return ret;
|
|
}
|
|
|
|
if (INTEL_GTT_GEN <= 2)
|
|
pci_read_config_dword(intel_private.pcidev, I810_GMADDR,
|
|
&gma_addr);
|
|
else
|
|
pci_read_config_dword(intel_private.pcidev, I915_GMADDR,
|
|
&gma_addr);
|
|
|
|
intel_private.base.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void i830_write_entry(dma_addr_t addr, unsigned int entry,
|
|
unsigned int flags)
|
|
{
|
|
u32 pte_flags = I810_PTE_VALID;
|
|
|
|
if (flags == AGP_USER_CACHED_MEMORY)
|
|
pte_flags |= I830_PTE_SYSTEM_CACHED;
|
|
|
|
writel(addr | pte_flags, intel_private.gtt + entry);
|
|
}
|
|
|
|
bool intel_enable_gtt(void)
|
|
{
|
|
u8 __iomem *reg;
|
|
|
|
if (INTEL_GTT_GEN >= 6)
|
|
return true;
|
|
|
|
if (INTEL_GTT_GEN == 2) {
|
|
u16 gmch_ctrl;
|
|
|
|
pci_read_config_word(intel_private.bridge_dev,
|
|
I830_GMCH_CTRL, &gmch_ctrl);
|
|
gmch_ctrl |= I830_GMCH_ENABLED;
|
|
pci_write_config_word(intel_private.bridge_dev,
|
|
I830_GMCH_CTRL, gmch_ctrl);
|
|
|
|
pci_read_config_word(intel_private.bridge_dev,
|
|
I830_GMCH_CTRL, &gmch_ctrl);
|
|
if ((gmch_ctrl & I830_GMCH_ENABLED) == 0) {
|
|
dev_err(&intel_private.pcidev->dev,
|
|
"failed to enable the GTT: GMCH_CTRL=%x\n",
|
|
gmch_ctrl);
|
|
return false;
|
|
}
|
|
}
|
|
|
|
/* On the resume path we may be adjusting the PGTBL value, so
|
|
* be paranoid and flush all chipset write buffers...
|
|
*/
|
|
if (INTEL_GTT_GEN >= 3)
|
|
writel(0, intel_private.registers+GFX_FLSH_CNTL);
|
|
|
|
reg = intel_private.registers+I810_PGETBL_CTL;
|
|
writel(intel_private.PGETBL_save, reg);
|
|
if (HAS_PGTBL_EN && (readl(reg) & I810_PGETBL_ENABLED) == 0) {
|
|
dev_err(&intel_private.pcidev->dev,
|
|
"failed to enable the GTT: PGETBL=%x [expected %x]\n",
|
|
readl(reg), intel_private.PGETBL_save);
|
|
return false;
|
|
}
|
|
|
|
if (INTEL_GTT_GEN >= 3)
|
|
writel(0, intel_private.registers+GFX_FLSH_CNTL);
|
|
|
|
return true;
|
|
}
|
|
|
|
static bool i830_check_flags(unsigned int flags)
|
|
{
|
|
switch (flags) {
|
|
case 0:
|
|
case AGP_PHYS_MEMORY:
|
|
case AGP_USER_CACHED_MEMORY:
|
|
case AGP_USER_MEMORY:
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
void intel_gtt_insert_sg_entries(struct pagelist *st,
|
|
unsigned int pg_start,
|
|
unsigned int flags)
|
|
{
|
|
int i, j;
|
|
|
|
j = pg_start;
|
|
|
|
for(i = 0; i < st->nents; i++)
|
|
{
|
|
dma_addr_t addr = st->page[i];
|
|
intel_private.driver->write_entry(addr, j, flags);
|
|
j++;
|
|
};
|
|
|
|
readl(intel_private.gtt+j-1);
|
|
}
|
|
|
|
static void intel_gtt_insert_pages(unsigned int first_entry,
|
|
unsigned int num_entries,
|
|
dma_addr_t *pages,
|
|
unsigned int flags)
|
|
{
|
|
int i, j;
|
|
|
|
for (i = 0, j = first_entry; i < num_entries; i++, j++) {
|
|
dma_addr_t addr = pages[i];
|
|
intel_private.driver->write_entry(addr,
|
|
j, flags);
|
|
}
|
|
readl(intel_private.gtt+j-1);
|
|
}
|
|
|
|
|
|
void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries)
|
|
{
|
|
unsigned int i;
|
|
|
|
for (i = first_entry; i < (first_entry + num_entries); i++) {
|
|
intel_private.driver->write_entry(intel_private.base.scratch_page_dma,
|
|
i, 0);
|
|
}
|
|
readl(intel_private.gtt+i-1);
|
|
}
|
|
|
|
static void intel_i9xx_setup_flush(void)
|
|
{
|
|
/* return if already configured */
|
|
if (intel_private.ifp_resource.start)
|
|
return;
|
|
|
|
if (INTEL_GTT_GEN == 6)
|
|
return;
|
|
|
|
/* setup a resource for this object */
|
|
// intel_private.ifp_resource.name = "Intel Flush Page";
|
|
// intel_private.ifp_resource.flags = IORESOURCE_MEM;
|
|
|
|
intel_private.resource_valid = 0;
|
|
|
|
/* Setup chipset flush for 915 */
|
|
// if (IS_G33 || INTEL_GTT_GEN >= 4) {
|
|
// intel_i965_g33_setup_chipset_flush();
|
|
// } else {
|
|
// intel_i915_setup_chipset_flush();
|
|
// }
|
|
|
|
// if (intel_private.ifp_resource.start)
|
|
// intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
|
|
if (!intel_private.i9xx_flush_page)
|
|
dev_err(&intel_private.pcidev->dev,
|
|
"can't ioremap flush page - no chipset flushing\n");
|
|
}
|
|
|
|
static void i9xx_cleanup(void)
|
|
{
|
|
if (intel_private.i9xx_flush_page)
|
|
iounmap(intel_private.i9xx_flush_page);
|
|
// if (intel_private.resource_valid)
|
|
// release_resource(&intel_private.ifp_resource);
|
|
intel_private.ifp_resource.start = 0;
|
|
intel_private.resource_valid = 0;
|
|
}
|
|
|
|
static void i9xx_chipset_flush(void)
|
|
{
|
|
if (intel_private.i9xx_flush_page)
|
|
writel(1, intel_private.i9xx_flush_page);
|
|
}
|
|
|
|
static void i965_write_entry(dma_addr_t addr,
|
|
unsigned int entry,
|
|
unsigned int flags)
|
|
{
|
|
u32 pte_flags;
|
|
|
|
pte_flags = I810_PTE_VALID;
|
|
if (flags == AGP_USER_CACHED_MEMORY)
|
|
pte_flags |= I830_PTE_SYSTEM_CACHED;
|
|
|
|
/* Shift high bits down */
|
|
addr |= (addr >> 28) & 0xf0;
|
|
writel(addr | pte_flags, intel_private.gtt + entry);
|
|
}
|
|
|
|
static bool gen6_check_flags(unsigned int flags)
|
|
{
|
|
return true;
|
|
}
|
|
|
|
static void haswell_write_entry(dma_addr_t addr, unsigned int entry,
|
|
unsigned int flags)
|
|
{
|
|
unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT;
|
|
unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT;
|
|
u32 pte_flags;
|
|
|
|
if (type_mask == AGP_USER_MEMORY)
|
|
pte_flags = HSW_PTE_UNCACHED | I810_PTE_VALID;
|
|
else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) {
|
|
pte_flags = GEN6_PTE_LLC_MLC | I810_PTE_VALID;
|
|
if (gfdt)
|
|
pte_flags |= GEN6_PTE_GFDT;
|
|
} else { /* set 'normal'/'cached' to LLC by default */
|
|
pte_flags = GEN6_PTE_LLC | I810_PTE_VALID;
|
|
if (gfdt)
|
|
pte_flags |= GEN6_PTE_GFDT;
|
|
}
|
|
|
|
/* gen6 has bit11-4 for physical addr bit39-32 */
|
|
addr |= (addr >> 28) & 0xff0;
|
|
writel(addr | pte_flags, intel_private.gtt + entry);
|
|
}
|
|
|
|
static void gen6_write_entry(dma_addr_t addr, unsigned int entry,
|
|
unsigned int flags)
|
|
{
|
|
unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT;
|
|
unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT;
|
|
u32 pte_flags;
|
|
|
|
if (type_mask == AGP_USER_MEMORY)
|
|
pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID;
|
|
else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) {
|
|
pte_flags = GEN6_PTE_LLC_MLC | I810_PTE_VALID;
|
|
if (gfdt)
|
|
pte_flags |= GEN6_PTE_GFDT;
|
|
} else { /* set 'normal'/'cached' to LLC by default */
|
|
pte_flags = GEN6_PTE_LLC | I810_PTE_VALID;
|
|
if (gfdt)
|
|
pte_flags |= GEN6_PTE_GFDT;
|
|
}
|
|
|
|
/* gen6 has bit11-4 for physical addr bit39-32 */
|
|
addr |= (addr >> 28) & 0xff0;
|
|
writel(addr | pte_flags, intel_private.gtt + entry);
|
|
}
|
|
|
|
static void valleyview_write_entry(dma_addr_t addr, unsigned int entry,
|
|
unsigned int flags)
|
|
{
|
|
unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT;
|
|
unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT;
|
|
u32 pte_flags;
|
|
|
|
if (type_mask == AGP_USER_MEMORY)
|
|
pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID;
|
|
else {
|
|
pte_flags = GEN6_PTE_LLC | I810_PTE_VALID;
|
|
if (gfdt)
|
|
pte_flags |= GEN6_PTE_GFDT;
|
|
}
|
|
|
|
/* gen6 has bit11-4 for physical addr bit39-32 */
|
|
addr |= (addr >> 28) & 0xff0;
|
|
writel(addr | pte_flags, intel_private.gtt + entry);
|
|
|
|
writel(1, intel_private.registers + GFX_FLSH_CNTL_VLV);
|
|
}
|
|
|
|
static void gen6_cleanup(void)
|
|
{
|
|
}
|
|
|
|
/* Certain Gen5 chipsets require require idling the GPU before
|
|
* unmapping anything from the GTT when VT-d is enabled.
|
|
*/
|
|
static inline int needs_idle_maps(void)
|
|
{
|
|
#ifdef CONFIG_INTEL_IOMMU
|
|
const unsigned short gpu_devid = intel_private.pcidev->device;
|
|
|
|
/* Query intel_iommu to see if we need the workaround. Presumably that
|
|
* was loaded first.
|
|
*/
|
|
if ((gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB ||
|
|
gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG) &&
|
|
intel_iommu_gfx_mapped)
|
|
return 1;
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
static int i9xx_setup(void)
|
|
{
|
|
u32 reg_addr;
|
|
int size = KB(512);
|
|
|
|
pci_read_config_dword(intel_private.pcidev, I915_MMADDR, ®_addr);
|
|
|
|
reg_addr &= 0xfff80000;
|
|
|
|
if (INTEL_GTT_GEN >= 7)
|
|
size = MB(2);
|
|
|
|
intel_private.registers = ioremap(reg_addr, size);
|
|
if (!intel_private.registers)
|
|
return -ENOMEM;
|
|
|
|
if (INTEL_GTT_GEN == 3) {
|
|
u32 gtt_addr;
|
|
|
|
pci_read_config_dword(intel_private.pcidev,
|
|
I915_PTEADDR, >t_addr);
|
|
intel_private.gtt_bus_addr = gtt_addr;
|
|
} else {
|
|
u32 gtt_offset;
|
|
|
|
switch (INTEL_GTT_GEN) {
|
|
case 5:
|
|
case 6:
|
|
case 7:
|
|
gtt_offset = MB(2);
|
|
break;
|
|
case 4:
|
|
default:
|
|
gtt_offset = KB(512);
|
|
break;
|
|
}
|
|
intel_private.gtt_bus_addr = reg_addr + gtt_offset;
|
|
}
|
|
|
|
if (needs_idle_maps())
|
|
intel_private.base.do_idle_maps = 1;
|
|
|
|
intel_i9xx_setup_flush();
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct intel_gtt_driver i915_gtt_driver = {
|
|
.gen = 3,
|
|
.has_pgtbl_enable = 1,
|
|
.setup = i9xx_setup,
|
|
.cleanup = i9xx_cleanup,
|
|
/* i945 is the last gpu to need phys mem (for overlay and cursors). */
|
|
.write_entry = i830_write_entry,
|
|
.dma_mask_size = 32,
|
|
.check_flags = i830_check_flags,
|
|
.chipset_flush = i9xx_chipset_flush,
|
|
};
|
|
static const struct intel_gtt_driver g33_gtt_driver = {
|
|
.gen = 3,
|
|
.is_g33 = 1,
|
|
.setup = i9xx_setup,
|
|
.cleanup = i9xx_cleanup,
|
|
.write_entry = i965_write_entry,
|
|
.dma_mask_size = 36,
|
|
.check_flags = i830_check_flags,
|
|
.chipset_flush = i9xx_chipset_flush,
|
|
};
|
|
static const struct intel_gtt_driver pineview_gtt_driver = {
|
|
.gen = 3,
|
|
.is_pineview = 1, .is_g33 = 1,
|
|
.setup = i9xx_setup,
|
|
.cleanup = i9xx_cleanup,
|
|
.write_entry = i965_write_entry,
|
|
.dma_mask_size = 36,
|
|
.check_flags = i830_check_flags,
|
|
.chipset_flush = i9xx_chipset_flush,
|
|
};
|
|
static const struct intel_gtt_driver i965_gtt_driver = {
|
|
.gen = 4,
|
|
.has_pgtbl_enable = 1,
|
|
.setup = i9xx_setup,
|
|
.cleanup = i9xx_cleanup,
|
|
.write_entry = i965_write_entry,
|
|
.dma_mask_size = 36,
|
|
.check_flags = i830_check_flags,
|
|
.chipset_flush = i9xx_chipset_flush,
|
|
};
|
|
static const struct intel_gtt_driver g4x_gtt_driver = {
|
|
.gen = 5,
|
|
.setup = i9xx_setup,
|
|
.cleanup = i9xx_cleanup,
|
|
.write_entry = i965_write_entry,
|
|
.dma_mask_size = 36,
|
|
.check_flags = i830_check_flags,
|
|
.chipset_flush = i9xx_chipset_flush,
|
|
};
|
|
static const struct intel_gtt_driver ironlake_gtt_driver = {
|
|
.gen = 5,
|
|
.is_ironlake = 1,
|
|
.setup = i9xx_setup,
|
|
.cleanup = i9xx_cleanup,
|
|
.write_entry = i965_write_entry,
|
|
.dma_mask_size = 36,
|
|
.check_flags = i830_check_flags,
|
|
.chipset_flush = i9xx_chipset_flush,
|
|
};
|
|
static const struct intel_gtt_driver sandybridge_gtt_driver = {
|
|
.gen = 6,
|
|
.setup = i9xx_setup,
|
|
.cleanup = gen6_cleanup,
|
|
.write_entry = gen6_write_entry,
|
|
.dma_mask_size = 40,
|
|
.check_flags = gen6_check_flags,
|
|
.chipset_flush = i9xx_chipset_flush,
|
|
};
|
|
static const struct intel_gtt_driver haswell_gtt_driver = {
|
|
.gen = 6,
|
|
.setup = i9xx_setup,
|
|
.cleanup = gen6_cleanup,
|
|
.write_entry = haswell_write_entry,
|
|
.dma_mask_size = 40,
|
|
.check_flags = gen6_check_flags,
|
|
.chipset_flush = i9xx_chipset_flush,
|
|
};
|
|
static const struct intel_gtt_driver valleyview_gtt_driver = {
|
|
.gen = 7,
|
|
.setup = i9xx_setup,
|
|
.cleanup = gen6_cleanup,
|
|
.write_entry = valleyview_write_entry,
|
|
.dma_mask_size = 40,
|
|
.check_flags = gen6_check_flags,
|
|
};
|
|
|
|
/* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of
|
|
* driver and gmch_driver must be non-null, and find_gmch will determine
|
|
* which one should be used if a gmch_chip_id is present.
|
|
*/
|
|
static const struct intel_gtt_driver_description {
|
|
unsigned int gmch_chip_id;
|
|
char *name;
|
|
const struct intel_gtt_driver *gtt_driver;
|
|
} intel_gtt_chipsets[] = {
|
|
{ PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)",
|
|
&i915_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_82915G_IG, "915G",
|
|
&i915_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM",
|
|
&i915_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_82945G_IG, "945G",
|
|
&i915_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM",
|
|
&i915_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME",
|
|
&i915_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ",
|
|
&i965_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_82G35_IG, "G35",
|
|
&i965_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q",
|
|
&i965_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_82965G_IG, "965G",
|
|
&i965_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM",
|
|
&i965_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE",
|
|
&i965_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_G33_IG, "G33",
|
|
&g33_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_Q35_IG, "Q35",
|
|
&g33_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_Q33_IG, "Q33",
|
|
&g33_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150",
|
|
&pineview_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150",
|
|
&pineview_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_GM45_IG, "GM45",
|
|
&g4x_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake",
|
|
&g4x_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43",
|
|
&g4x_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43",
|
|
&g4x_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_B43_IG, "B43",
|
|
&g4x_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_B43_1_IG, "B43",
|
|
&g4x_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_G41_IG, "G41",
|
|
&g4x_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG,
|
|
"HD Graphics", &ironlake_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG,
|
|
"HD Graphics", &ironlake_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG,
|
|
"Sandybridge", &sandybridge_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG,
|
|
"Sandybridge", &sandybridge_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG,
|
|
"Sandybridge", &sandybridge_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG,
|
|
"Sandybridge", &sandybridge_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG,
|
|
"Sandybridge", &sandybridge_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG,
|
|
"Sandybridge", &sandybridge_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG,
|
|
"Sandybridge", &sandybridge_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT1_IG,
|
|
"Ivybridge", &sandybridge_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT2_IG,
|
|
"Ivybridge", &sandybridge_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT1_IG,
|
|
"Ivybridge", &sandybridge_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT2_IG,
|
|
"Ivybridge", &sandybridge_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG,
|
|
"Ivybridge", &sandybridge_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT2_IG,
|
|
"Ivybridge", &sandybridge_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_VALLEYVIEW_IG,
|
|
"ValleyView", &valleyview_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_HASWELL_D_GT1_IG,
|
|
"Haswell", &haswell_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_IG,
|
|
"Haswell", &haswell_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_PLUS_IG,
|
|
"Haswell", &haswell_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_HASWELL_M_GT1_IG,
|
|
"Haswell", &haswell_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_IG,
|
|
"Haswell", &haswell_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_PLUS_IG,
|
|
"Haswell", &haswell_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_HASWELL_S_GT1_IG,
|
|
"Haswell", &haswell_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_IG,
|
|
"Haswell", &haswell_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_PLUS_IG,
|
|
"Haswell", &haswell_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT1_IG,
|
|
"Haswell", &haswell_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_IG,
|
|
"Haswell", &haswell_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_PLUS_IG,
|
|
"Haswell", &haswell_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT1_IG,
|
|
"Haswell", &haswell_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_IG,
|
|
"Haswell", &haswell_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_PLUS_IG,
|
|
"Haswell", &haswell_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT1_IG,
|
|
"Haswell", &haswell_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_IG,
|
|
"Haswell", &haswell_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_PLUS_IG,
|
|
"Haswell", &haswell_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT1_IG,
|
|
"Haswell", &haswell_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_IG,
|
|
"Haswell", &haswell_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_PLUS_IG,
|
|
"Haswell", &haswell_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT1_IG,
|
|
"Haswell", &haswell_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_IG,
|
|
"Haswell", &haswell_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_PLUS_IG,
|
|
"Haswell", &haswell_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT1_IG,
|
|
"Haswell", &haswell_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_IG,
|
|
"Haswell", &haswell_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_PLUS_IG,
|
|
"Haswell", &haswell_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT1_IG,
|
|
"Haswell", &haswell_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_IG,
|
|
"Haswell", &haswell_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_PLUS_IG,
|
|
"Haswell", &haswell_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT1_IG,
|
|
"Haswell", &haswell_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_IG,
|
|
"Haswell", &haswell_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_PLUS_IG,
|
|
"Haswell", &haswell_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT1_IG,
|
|
"Haswell", &haswell_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_IG,
|
|
"Haswell", &haswell_gtt_driver },
|
|
{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_PLUS_IG,
|
|
"Haswell", &haswell_gtt_driver },
|
|
{ 0, NULL, NULL }
|
|
};
|
|
|
|
static int find_gmch(u16 device)
|
|
{
|
|
struct pci_dev *gmch_device;
|
|
|
|
gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
|
|
if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
|
|
gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
|
|
device, gmch_device);
|
|
}
|
|
|
|
if (!gmch_device)
|
|
return 0;
|
|
|
|
intel_private.pcidev = gmch_device;
|
|
return 1;
|
|
}
|
|
|
|
int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev,
|
|
struct agp_bridge_data *bridge)
|
|
{
|
|
int i, mask;
|
|
intel_private.driver = NULL;
|
|
|
|
for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) {
|
|
if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) {
|
|
intel_private.driver =
|
|
intel_gtt_chipsets[i].gtt_driver;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (!intel_private.driver)
|
|
return 0;
|
|
|
|
if (bridge) {
|
|
bridge->dev_private_data = &intel_private;
|
|
bridge->dev = bridge_pdev;
|
|
}
|
|
|
|
intel_private.bridge_dev = bridge_pdev;
|
|
|
|
dbgprintf("Intel %s Chipset\n", intel_gtt_chipsets[i].name);
|
|
|
|
mask = intel_private.driver->dma_mask_size;
|
|
// if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask)))
|
|
// dev_err(&intel_private.pcidev->dev,
|
|
// "set gfx device dma mask %d-bit failed!\n", mask);
|
|
// else
|
|
// pci_set_consistent_dma_mask(intel_private.pcidev,
|
|
// DMA_BIT_MASK(mask));
|
|
|
|
if (intel_gtt_init() != 0) {
|
|
// intel_gmch_remove();
|
|
|
|
return 0;
|
|
}
|
|
|
|
return 1;
|
|
}
|
|
EXPORT_SYMBOL(intel_gmch_probe);
|
|
|
|
const struct intel_gtt *intel_gtt_get(void)
|
|
{
|
|
return &intel_private.base;
|
|
}
|
|
EXPORT_SYMBOL(intel_gtt_get);
|
|
|
|
void intel_gtt_chipset_flush(void)
|
|
{
|
|
if (intel_private.driver->chipset_flush)
|
|
intel_private.driver->chipset_flush();
|
|
}
|
|
EXPORT_SYMBOL(intel_gtt_chipset_flush);
|
|
|
|
|
|
//phys_addr_t get_bus_addr(void)
|
|
//{
|
|
// return intel_private.gma_bus_addr;
|
|
//};
|