Improved logic flow and code readability based on suggestions

This commit is contained in:
YVishere committed 2026-03-19 18:24:42 -05:00
1 parent 3c8782552d
commit cd73ea0da6
2 files changed
+14 -24

No files matched your search

+9 -12
View File
@@ -13,40 +13,37 @@ VEN_STRIDE = 8
; clears and returns value in esi
if used PCI_find_dev
proc PCI_find_dev stdcall ven_id, dev_id
push edx
xor esi, esi
mov esi, ven1_array
cmp [ven_id], VirtVendorID1
jz .pre_loop
jz .next_device_id
mov esi, ven2_array
cmp [ven_id], VirtVendorID2
jnz @F ;unknown vendor id
jnz .not_found ;unknown vendor id
.pre_loop:
push edx
.loop:
.next_device_id:
mov edx, [esi] ;fewer memory accesses
test edx, edx
jz .not_found ;end of array
cmp edx, [dev_id]
jz .found
add esi, VEN_STRIDE
jmp .loop
.found:
cmp edx, [dev_id]
jnz .next_device_id
;Found device
sub esi, VEN_STRIDE ;The loop adds it an one time extra
pop edx
ret
.not_found:
pop edx
@@:
xor esi, esi
ret
endp
+5 -12
View File
@@ -13,12 +13,6 @@ DEBUG equ 1
__DEBUG__ equ 1
__DEBUG_LEVEL__ equ 1
API_VERSION equ 0 ;debug
STRIDE equ 4 ;size of row in devices table
SRV_GETVERSION equ 0
section '.flat' code readable writable executable
include '../proc32.inc'
include '../struct.inc'
@@ -61,10 +55,9 @@ proc detect
mov ecx, edx
shr ecx, 16 ;cx upper half - device id, dx lower half - vendor id
;prepare regs for find dev proc
movzx ecx, cx
;prepare regs for find dev proc
movzx edx, dx
stdcall PCI_find_dev, edx, ecx
test esi, esi
jz .notVirt
@@ -76,9 +69,9 @@ proc detect
jmp .next_dev
.finish:
xor eax, eax
pop ebx
inc eax
xor eax, eax
pop ebx
inc eax
ret
endp