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Leency
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Leency
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 LeencyandClaude Opus 5
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 Egor00f
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 Matou1306
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Leency
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302bf7e221 | ||
 IgorA
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 b00bl1k
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@@ -1,644 +0,0 @@
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;; sky2.inc - Marvell Yukon-2 (88E805x and friends) registers
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;; for KolibriOS
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;;
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;; Minimal subset needed to probe the chip and read the permanent
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;; MAC address. Expand later for rings, BMU, status LE, etc.
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;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; PCI Power Management (capability; standard offset when present)
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; We poke the common location used by bge: config offset 0x4C is often PMCSR
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; on these chips (capability linked). OpenBSD uses BGE_PCI_PWRMGMT_CMD.
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PCI_PWRMGMT_CMD = 0x4C
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PCI_PWR_D0 = 0x00
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PCI_PWR_D3hot = 0x03
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PCI_PWR_PME_ENABLE = 0x0100
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;----------------------------------------------------------------------
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; PCI vendor / device IDs (subset of the Yukon-2 family)
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;----------------------------------------------------------------------
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PCI_VENDOR_MARVELL = 0x11AB
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; Common 88E805x / Yukon-2 device IDs
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PCI_DEVICE_88E8021 = 0x4340
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PCI_DEVICE_88E8022 = 0x4341
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PCI_DEVICE_88E8035 = 0x4350
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PCI_DEVICE_88E8036 = 0x4351
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PCI_DEVICE_88E8038 = 0x4352
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PCI_DEVICE_88E8039 = 0x4353
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PCI_DEVICE_88E8040 = 0x4354
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PCI_DEVICE_88E8040T = 0x4355
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PCI_DEVICE_88E8052 = 0x4360
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PCI_DEVICE_88E8053 = 0x4361
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PCI_DEVICE_88E8055 = 0x4363 ; the one we care about first
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PCI_DEVICE_88E8056 = 0x4364
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PCI_DEVICE_88E8057 = 0x4362
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PCI_DEVICE_88E8058 = 0x436A
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PCI_DEVICE_88E8071 = 0x436B
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PCI_DEVICE_88E8072 = 0x436C
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PCI_DEVICE_88E8075 = 0x4370
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;----------------------------------------------------------------------
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; Control / Status registers (block 0)
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;----------------------------------------------------------------------
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B0_RAP = 0x0000
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B0_CTST = 0x0004 ; Control/Status (16-bit)
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B0_POWER_CTRL = 0x0007
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B0_ISRC = 0x0008
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B0_IMSK = 0x000C
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B0_HWE_ISRC = 0x0010
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B0_HWE_IMSK = 0x0014
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; Yukon-2 special ISR registers
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B0_Y2_SP_ISRC2 = 0x001C
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B0_Y2_SP_ISRC3 = 0x0020
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B0_Y2_SP_EISR = 0x0024
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B0_Y2_SP_LISR = 0x0028
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B0_Y2_SP_ICR = 0x002C
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; CTST bits we care about for a minimal bring-up
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CS_RST_SET = 0x0001
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CS_RST_CLR = 0x0002
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CS_MRST_SET = 0x0004
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CS_MRST_CLR = 0x0008
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CS_STOP_MASTER = 0x0020
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CS_STOP_DONE = 0x0040
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CS_SW_IRQ = 0x0200
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CS_CL_SW_IRQ = 0x0100
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;----------------------------------------------------------------------
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; Block 2 – MAC addresses, chip ID, clocks
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;----------------------------------------------------------------------
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B2_MAC_1 = 0x0100 ; port 0 permanent MAC (6 bytes)
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B2_MAC_2 = 0x0108 ; port 1 (if dual)
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B2_MAC_3 = 0x0110
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B2_CONN_TYP = 0x0118
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B2_PMD_TYP = 0x0119
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B2_MAC_CFG = 0x011A ; chip revision in bits 7:4
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B2_CHIP_ID = 0x011B
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B2_E_0 = 0x011C
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B2_Y2_CLK_GATE = 0x011D
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B2_Y2_HW_RES = 0x011E
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B2_E_3 = 0x011F
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B2_Y2_CLK_CTRL = 0x0120
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; Chip ID values (read from B2_CHIP_ID)
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CHIP_ID_YUKON_XL = 0xB3
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CHIP_ID_YUKON_EC_U = 0xB4 ; 88E8055 is often this
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CHIP_ID_YUKON_EX = 0xB5
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CHIP_ID_YUKON_EC = 0xB6
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CHIP_ID_YUKON_FE = 0xB7
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CHIP_ID_YUKON_FE_P = 0xB8
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CHIP_ID_YUKON_SUPR = 0xB9
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CHIP_ID_YUKON_UL_2 = 0xBA
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CHIP_ID_YUKON_OPT = 0xBC
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CHIP_ID_YUKON_PRM = 0xBD
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CHIP_ID_YUKON_OP_2 = 0xBE
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; B2_MAC_CFG
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CFG_CHIP_R_MSK = 0xF0 ; revision in bits 7:4
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CFG_SNG_MAC = 0x01 ; 1 = single MAC
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;----------------------------------------------------------------------
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; ASF / test-control / RAM-interface (used during reset)
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;----------------------------------------------------------------------
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B28_Y2_ASF_STAT_CMD = 0x0E68 ; 32 bit ASF Status and Command Reg
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Y2_ASF_RESET = 1 shl 3 ; ASF system in reset state
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Y2_ASF_DISABLE = 1 shl 12 ; ASF unit disable (in B0_CTST)
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B2_TST_CTRL1 = 0x0158 ; 8 bit Test Control Register 1
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TST_CFG_WRITE_ON = 1 shl 1 ; Enable Config Reg WR
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TST_CFG_WRITE_OFF = 1 shl 0 ; Disable Config Reg WR
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; Standard PCI config space status register (offset 0x06) - sticky error bits,
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; write-1-to-clear. Cleared during reset in case a previous driver load / BIOS
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; left an error latched (matches Linux sky2_reset()).
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PCI_STATUS_ERROR_BITS = 0xF900 ; PARITY | SIG_SYSERR | REC_MABORT |
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; REC_TABORT | SIG_TABORT | DET_PARITY
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Y2_CLK_DIV_DIS = 1 shl 0 ; disable core clock division (B2_Y2_CLK_CTRL)
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Y2_LED_STAT_ON = 1 shl 9 ; "driver loaded" status LED on (B0_CTST)
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;----------------------------------------------------------------------
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; Block 8 / Tx Arbiter, GMAC control (SK_REG-style: stride 0x80/port)
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;----------------------------------------------------------------------
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GMAC_CTRL = 0x0F00 ; 32 bit GMAC Control Reg
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GMAC_IRQ_MSK = 0x0F0C ; 8 bit GMAC Interrupt Mask Reg
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GMAC_LINK_CTRL = 0x0F10 ; 16 bit GMAC Link Control Reg
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GMLC_RST_CLR = 1 shl 1 ; Clear GMAC Link Reset
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GMLC_RST_SET = 1 shl 0 ; Set GMAC Link Reset
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; GMAC_CTRL bits (this is the GMAC core's OWN reset - distinct from
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; GMAC_LINK_CTRL above, and from GPHY_CTRL below. All three are separate
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; reset domains and Linux/OpenBSD both toggle all three during bring-up.
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GMC_LOOP_OFF = 1 shl 4
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GMC_PAUSE_ON = 1 shl 3
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GMC_RST_CLR = 1 shl 1 ; Clear GMAC (core) Reset
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GMC_RST_SET = 1 shl 0 ; Set GMAC (core) Reset
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; GPHY_CTRL - the internal PHY block's own reset (separate register,
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; offset 0xf04, SK_REG-style stride 0x80/port like GMAC_CTRL/LINK_CTRL).
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; Missing this entirely is what left the PHY permanently unresponsive
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; to MDIO on first bring-up - see field log from 2026-08-08.
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GPHY_CTRL = 0x0F04
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GPC_RST_CLR = 1 shl 1 ; Clear GPHY Reset
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GPC_RST_SET = 1 shl 0 ; Set GPHY Reset
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;----------------------------------------------------------------------
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; MMIO-mirrored PCI config space. The chip exposes a window of its own
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; PCI config space directly in MMIO (NOT the same thing as a real PCI
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; config cycle via PciRead/PciWrite) - used for the per-chip "OUR_REG"
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; power-control registers below. See sky2_pci_read32/if_msk.c
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; SK_Y2_PCI_REG() in the reference drivers.
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;----------------------------------------------------------------------
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Y2_CFG_SPC = 0x1C00
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PCI_DEV_REG1 = 0x40
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PCI_DEV_REG2 = 0x44
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PCI_DEV_REG3 = 0x80
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PCI_DEV_REG4 = 0x84
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PCI_DEV_REG5 = 0x88
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PCI_CFG_REG_1 = 0x94
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; PCI_DEV_REG2 bits
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PCI_EN_DUMMY_RD = 1 shl 3 ; Enable dummy read
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PCI_REV_DESC = 1 shl 2 ; Reverse descriptor bytes (BE CPUs only)
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PCI_USEDATA64 = 1 shl 0 ; Use 64-bit data bus extension
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; PCI_DEV_REG1 bits - per-port PHY power-down / "coma" mode. These must
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; be CLEARED or the internal PHY stays powered down and MDIO will never
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; respond, no matter how long you poll (matches the observed symptom).
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PCI_Y2_PHY1_POWD = 1 shl 26
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PCI_Y2_PHY2_POWD = 1 shl 27
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PCI_Y2_PHY1_COMA = 1 shl 28
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PCI_Y2_PHY2_COMA = 1 shl 29
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; PCI_DEV_REG4 ASPM control bits, masked off during the EC-Ultra/EX/FE+
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; "advanced power control" bring-up sequence (SKY2_HW_ADV_POWER_CTL)
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P_FORCE_ASPM_REQUEST = 1 shl 15
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P_ASPM_GPHY_LINK_DOWN = 1 shl 14
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P_ASPM_INT_FIFO_EMPTY = 1 shl 13
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P_ASPM_CLKRUN_REQUEST = 1 shl 12
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P_ASPM_CONTROL_MSK = P_FORCE_ASPM_REQUEST or P_ASPM_GPHY_LINK_DOWN \
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or P_ASPM_CLKRUN_REQUEST or P_ASPM_INT_FIFO_EMPTY
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; PCI_DEV_REG5 Vmain_av timer bits, similarly masked
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P_CTL_TIM_VMAIN_AV_MSK = 3 shl 27
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B2_GP_IO = 0x015C
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GLB_GPIO_STAT_RACE_DIS = 1 shl 13 ; workaround for dev 4.107 on EC-U/EX
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Y2_HW_WOL_ON = 1 shl 15
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;----------------------------------------------------------------------
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; GMAC / PHY block (per-port, stride 0x1000, base 0x2800 for port 0)
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;----------------------------------------------------------------------
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BASE_GMAC_1 = 0x2800 ; port 0 GMAC/PHY register block
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BASE_GMAC_2 = 0x3800 ; port 1 GMAC/PHY register block
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; Offsets relative to the per-port GMAC block (add to BASE_GMAC_n)
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GM_GP_STAT = 0x0000 ; 16 bit r/o General Purpose Status
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GM_GP_CTRL = 0x0004 ; 16 bit r/w General Purpose Control
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GM_TX_CTRL = 0x0008
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GM_RX_CTRL = 0x000C
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GM_SERIAL_MODE = 0x0018 ; 16 bit r/w Serial Mode Register
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GM_MC_ADDR_H1 = 0x0034
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GM_MC_ADDR_H2 = 0x0038
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GM_MC_ADDR_H3 = 0x003C
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GM_MC_ADDR_H4 = 0x0040
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GM_SMI_CTRL = 0x0080 ; 16 bit r/w SMI (MDIO) Control
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GM_SMI_DATA = 0x0084 ; 16 bit r/w SMI Data
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GM_PHY_ADDR = 0x0088 ; 16 bit r/w GPHY Address
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; GM_GP_STAT bits
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GM_GPSR_SPEED = 1 shl 15 ; 1 = 100 Mbps (see GIG_SPEED for 1000)
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GM_GPSR_DUPLEX = 1 shl 14 ; 1 = Full duplex
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GM_GPSR_FC_TX_DIS = 1 shl 13
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GM_GPSR_LINK_UP = 1 shl 12 ; Link Up Status
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GM_GPSR_GIG_SPEED = 1 shl 4 ; 1 = 1000 Mbps
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; GM_GP_CTRL bits
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GM_GPCR_TX_ENA = 1 shl 12
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GM_GPCR_RX_ENA = 1 shl 11
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; GM_RX_CTRL bits
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GM_RXCR_UCF_ENA = 1 shl 15 ; enable unicast filtering
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GM_RXCR_MCF_ENA = 1 shl 14 ; enable multicast filtering
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; GM_SMI_CTRL bits/fields
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GM_SMI_CT_PHY_A_MSK = 0x1F shl 11
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GM_SMI_CT_REG_A_MSK = 0x1F shl 6
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GM_SMI_CT_OP_RD = 1 shl 5 ; opcode read (0 = write)
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GM_SMI_CT_RD_VAL = 1 shl 4 ; read completed, data valid
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GM_SMI_CT_BUSY = 1 shl 3 ; operation in progress
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PHY_ADDR_MARV = 0 ; internal PHY is always MDIO addr 0
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PHY_RETRIES = 20 ; MDIO poll retries; each retry sleeps
|
||||
; ~1ms (Sleep() is ms, not centiseconds -
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; confirmed empirically), so 20 = ~20ms
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; worst-case before giving up
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;----------------------------------------------------------------------
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; Marvell internal PHY (88E1xxx) register numbers, via GM_SMI_*
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;----------------------------------------------------------------------
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PHY_MARV_CTRL = 0x00 ; PHY Control
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PHY_MARV_AUNE_ADV = 0x04 ; Auto-Neg. Advertisement
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||||
PHY_MARV_1000T_CTRL = 0x09 ; 1000Base-T Control
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||||
PHY_MARV_PHY_CTRL = 0x10 ; PHY Specific Control
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||||
PHY_MARV_PHY_STAT = 0x11 ; PHY Specific Status
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||||
PHY_MARV_INT_MASK = 0x12 ; Interrupt Mask
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PHY_MARV_INT_STAT = 0x13 ; Interrupt Status (r/o, clear-on-read)
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PHY_MARV_EXT_CTRL = 0x14 ; Ext. PHY Specific Control
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; PHY_MARV_CTRL bits
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PHY_CT_RESET = 1 shl 15 ; (sc) reset all PHY regs
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PHY_CT_SPS_LSB = 1 shl 13 ; speed select, low bit -> PHY_CT_SP100
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PHY_CT_ANE = 1 shl 12 ; Auto-Negotiation Enabled
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PHY_CT_RE_CFG = 1 shl 9 ; (sc) Restart Auto-Negotiation
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PHY_CT_DUP_MD = 1 shl 8 ; Duplex Mode (forced)
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PHY_CT_SPS_MSB = 1 shl 6 ; speed select, high bit -> PHY_CT_SP1000
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PHY_CT_SP1000 = PHY_CT_SPS_MSB
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PHY_CT_SP100 = PHY_CT_SPS_LSB
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; PHY_MARV_AUNE_ADV bits
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PHY_AN_CSMA = 1 shl 0 ; selector = IEEE 802.3 (always set)
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PHY_M_AN_10_HD = 1 shl 5
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PHY_M_AN_10_FD = 1 shl 6
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PHY_M_AN_100_HD = 1 shl 7
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PHY_M_AN_100_FD = 1 shl 8
|
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|
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; PHY_MARV_1000T_CTRL bits
|
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PHY_M_1000C_AHD = 1 shl 8 ; advertise 1000Base-T half duplex
|
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PHY_M_1000C_AFD = 1 shl 9 ; advertise 1000Base-T full duplex
|
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|
||||
; PHY_MARV_PHY_CTRL bits (copper, "newer PHY" variants incl. EC Ultra)
|
||||
PHY_M_PC_MDIX_MSK = 3 shl 5
|
||||
PHY_M_PC_ENA_AUTO = 3 ; enable automatic MDI/MDIX crossover
|
||||
PHY_M_PC_EN_DET_MSK = 3 shl 8 ; energy detect mask
|
||||
PHY_M_PC_DSC_MSK = 7 shl 12 ; downshift counter mask
|
||||
PHY_M_PC_DOWN_S_ENA = 1 shl 11 ; downshift enable
|
||||
|
||||
; PHY_MARV_PHY_STAT bits
|
||||
PHY_M_PS_SPEED_MSK = 3 shl 14
|
||||
PHY_M_PS_SPEED_1000 = 1 shl 15
|
||||
PHY_M_PS_SPEED_100 = 1 shl 14
|
||||
PHY_M_PS_FULL_DUP = 1 shl 13
|
||||
PHY_M_PS_LINK_UP = 1 shl 10
|
||||
PHY_M_PS_MDI_X_STAT = 1 shl 6
|
||||
|
||||
; PHY_MARV_INT_MASK / PHY_MARV_INT_STAT bits. Reading INT_STAT clears the
|
||||
; pending condition at the PHY - no separate ack is needed once this is
|
||||
; serviced (confirmed against both reference drivers: neither writes
|
||||
; back to INT_STAT, and the top-level B0_ISRC bit below is just a live
|
||||
; passthrough of the PHY's own interrupt line).
|
||||
PHY_M_IS_LSP_CHANGE = 1 shl 14 ; Link Speed Changed
|
||||
PHY_M_IS_DUP_CHANGE = 1 shl 13 ; Duplex Mode Changed
|
||||
PHY_M_IS_LST_CHANGE = 1 shl 10 ; Link Status Changed
|
||||
PHY_M_DEF_MSK = PHY_M_IS_LSP_CHANGE or PHY_M_IS_DUP_CHANGE \
|
||||
or PHY_M_IS_LST_CHANGE
|
||||
|
||||
;----------------------------------------------------------------------
|
||||
; Chip-level (not per-port) interrupt status/mask. B0_ISRC/B0_IMSK are
|
||||
; already declared above (block 0 registers); B0_ISRC is a live,
|
||||
; read-only OR of every currently-asserting enabled source - nothing
|
||||
; needs to be written back to it, only to the underlying source that
|
||||
; set it (here, PHY_MARV_INT_STAT above).
|
||||
;----------------------------------------------------------------------
|
||||
Y2_IS_IRQ_PHY1 = 1 shl 4 ; interrupt from PHY on port 0
|
||||
Y2_IS_STAT_BMU = 1 shl 30 ; status BMU (RX/TX completion) interrupt
|
||||
|
||||
;----------------------------------------------------------------------
|
||||
; List-element (LE) descriptor rings. Yukon-2 uses a uniform 8-byte
|
||||
; descriptor for TX, RX, AND the status/completion ring: addr(4),
|
||||
; length(2), ctrl/css(1), opcode(1). Cross-checked byte-for-byte
|
||||
; against OpenBSD's msk_tx_desc/msk_rx_desc (if_skreg.h) as well as
|
||||
; Linux's sky2_tx_le/sky2_rx_le/sky2_status_le - full agreement.
|
||||
;
|
||||
; Deliberately out of scope for this pass: 64-bit DMA addressing
|
||||
; (OP_ADDR64 - not needed, this is a 32-bit OS so every physical
|
||||
; address already fits in the low 32 bits), scatter-gather/multi-
|
||||
; fragment packets, VLAN tagging, checksum offload, RSS, jumbo
|
||||
; frames, and TX/RX interrupt-coalescing timers (STAT_*_TIMER_INI -
|
||||
; left at their power-on-reset default, which just means the status
|
||||
; ring reports completions eagerly rather than batched).
|
||||
;----------------------------------------------------------------------
|
||||
OP_ADDR64 = 0x21
|
||||
OP_BUFFER = 0x40
|
||||
OP_PACKET = 0x41
|
||||
OP_RXSTAT = 0x60
|
||||
OP_TXINDEXLE = 0x68
|
||||
HW_OWNER = 0x80 ; opcode-byte bit: entry owned by hardware
|
||||
LE_EOP = 0x80 ; ctrl-byte bit: end of packet (TX only)
|
||||
|
||||
; Receive Frame Status bits (in a status-ring RX entry's "status" field)
|
||||
GMR_FS_LEN = 0x7FFF shl 16
|
||||
GMR_FS_RX_OK = 1 shl 8
|
||||
GMR_FS_GOOD_FC = 1 shl 7
|
||||
GMR_FS_BAD_FC = 1 shl 6
|
||||
GMR_FS_MII_ERR = 1 shl 5
|
||||
GMR_FS_LONG_ERR = 1 shl 4
|
||||
GMR_FS_FRAGMENT = 1 shl 3
|
||||
GMR_FS_CRC_ERR = 1 shl 1
|
||||
GMR_FS_RX_FF_OV = 1 shl 0
|
||||
GMR_FS_ANY_ERR = GMR_FS_RX_FF_OV or GMR_FS_CRC_ERR or GMR_FS_FRAGMENT \
|
||||
or GMR_FS_LONG_ERR or GMR_FS_MII_ERR or GMR_FS_BAD_FC
|
||||
|
||||
CSS_LINK_BIT = 1 shl 0 ; port number, within a status entry's css byte
|
||||
|
||||
;----------------------------------------------------------------------
|
||||
; Queue block (Q_CSR/Q_WM/Q_AL/Q_TEST/Q_DONE) - stride B8_Q_REGS-based,
|
||||
; one block per queue (RX1/RX2/sync-TX1/sync-TX2/async-TX1/async-TX2).
|
||||
; We only ever use RX1 (port 0 receive) and async-TX1 (port 0 transmit).
|
||||
;----------------------------------------------------------------------
|
||||
B8_Q_REGS = 0x0400
|
||||
Q_R1 = 0x0000 ; RX queue, port 0
|
||||
Q_XS1 = 0x0200 ; sync TX queue, port 0 (kept disabled)
|
||||
Q_XA1 = 0x0280 ; async TX queue, port 0 - the one we use
|
||||
|
||||
Q_DONE = 0x24 ; 16 bit - Done Index
|
||||
Q_CSR = 0x34 ; 32 bit - BMU Control/Status
|
||||
Q_TEST = 0x38 ; 32 bit - Test/Control
|
||||
Q_WM = 0x40 ; 16 bit - FIFO Watermark
|
||||
Q_AL = 0x42 ; 8 bit - FIFO Alignment
|
||||
|
||||
BMU_CLR_IRQ_PAR = 1 shl 11
|
||||
BMU_CLR_IRQ_CHK = 1 shl 10
|
||||
BMU_START = 1 shl 8
|
||||
BMU_FIFO_ENA = 1 shl 5
|
||||
BMU_FIFO_RST = 1 shl 4
|
||||
BMU_OP_ON = 1 shl 3
|
||||
BMU_OP_OFF = 1 shl 2
|
||||
BMU_FIFO_OP_ON = 1 shl 7
|
||||
BMU_RST_CLR = 1 shl 1
|
||||
BMU_CLR_RESET = BMU_FIFO_RST or BMU_OP_OFF or BMU_RST_CLR
|
||||
BMU_OPER_INIT = BMU_CLR_IRQ_PAR or BMU_CLR_IRQ_CHK or BMU_START \
|
||||
or BMU_FIFO_ENA or BMU_OP_ON
|
||||
BMU_WM_DEFAULT = 0x600
|
||||
|
||||
F_TX_CHK_AUTO_OFF = 1 shl 31 ; Q_TEST: disable TX descriptor auto-check
|
||||
F_TX_CHK_AUTO_ON = 1 shl 30
|
||||
F_M_RX_RAM_DIS = 1 shl 24 ; Q_TEST bit: MAC Rx RAM read port
|
||||
; disabled - required on EC-Ultra
|
||||
; chip_rev > A0 (ours is rev 3), see
|
||||
; Linux sky2_rx_start()
|
||||
CHIP_REV_YU_EC_U_A0 = 1
|
||||
|
||||
;----------------------------------------------------------------------
|
||||
; Prefetch unit - the interface between the driver's LE ring and the
|
||||
; hardware. Separate register block from Q_CSR above despite similar
|
||||
; per-queue addressing (base + queue-offset + reg).
|
||||
;----------------------------------------------------------------------
|
||||
Y2_B8_PREF_REGS = 0x0450
|
||||
|
||||
PREF_UNIT_CTRL = 0x00 ; 32 bit
|
||||
PREF_UNIT_LAST_IDX = 0x04 ; 16 bit
|
||||
PREF_UNIT_ADDR_LO = 0x08 ; 32 bit
|
||||
PREF_UNIT_ADDR_HI = 0x0C ; 32 bit
|
||||
PREF_UNIT_GET_IDX = 0x10 ; 16 bit
|
||||
PREF_UNIT_PUT_IDX = 0x14 ; 16 bit
|
||||
|
||||
PREF_UNIT_RST_SET = 1 shl 0
|
||||
PREF_UNIT_RST_CLR = 1 shl 1
|
||||
PREF_UNIT_OP_ON = 1 shl 3
|
||||
|
||||
;----------------------------------------------------------------------
|
||||
; RAM buffer arbiter - per-queue FIFO sizing within the chip's internal
|
||||
; RAM. Sizes are in "qwords" (8-byte units) per the hardware register
|
||||
; definition; sky2_ramset-equivalent code below converts from KB.
|
||||
;----------------------------------------------------------------------
|
||||
B16_RAM_REGS = 0x0800
|
||||
|
||||
RB_START = 0x00 ; 32 bit
|
||||
RB_END = 0x04 ; 32 bit
|
||||
RB_WP = 0x08 ; 32 bit
|
||||
RB_RP = 0x0C ; 32 bit
|
||||
RB_RX_UTPP = 0x10 ; 32 bit - Rx upper thresh, pause pkt
|
||||
RB_RX_LTPP = 0x14 ; 32 bit - Rx lower thresh, pause pkt
|
||||
RB_RX_UTHP = 0x18 ; 32 bit - Rx upper thresh, high prio
|
||||
RB_RX_LTHP = 0x1C ; 32 bit - Rx lower thresh, high prio
|
||||
RB_CTRL = 0x28 ; 32 bit
|
||||
|
||||
RB_ENA_STFWD = 1 shl 5 ; enable store & forward (Tx queues)
|
||||
RB_ENA_OP_MD = 1 shl 3
|
||||
RB_DIS_OP_MD = 1 shl 2
|
||||
RB_RST_CLR = 1 shl 1
|
||||
RB_RST_SET = 1 shl 0
|
||||
|
||||
B2_E_0 = 0x011C ; 8 bit - internal RAM size, in 4K blocks
|
||||
|
||||
;----------------------------------------------------------------------
|
||||
; TX arbiter - per-port, SK_REG-style addressing (stride 0x80/port,
|
||||
; same block as GMAC_CTRL/GPHY_CTRL/GMAC_LINK_CTRL).
|
||||
;----------------------------------------------------------------------
|
||||
TXA_ITI_INI = 0x0200 ; 32 bit
|
||||
TXA_LIM_INI = 0x0208 ; 32 bit
|
||||
TXA_CTRL = 0x0210 ; 8 bit
|
||||
TXA_ENA_FSYNC = 1 shl 7
|
||||
TXA_DIS_FSYNC = 1 shl 6
|
||||
TXA_ENA_ALLOC = 1 shl 5
|
||||
TXA_DIS_ALLOC = 1 shl 4
|
||||
TXA_START_RC = 1 shl 3
|
||||
TXA_STOP_RC = 1 shl 2
|
||||
TXA_ENA_ARB = 1 shl 1
|
||||
TXA_DIS_ARB = 1 shl 0
|
||||
|
||||
;----------------------------------------------------------------------
|
||||
; Status/completion ring (card-wide, not per-port). The BMU writes
|
||||
; completion entries here as RX/TX work finishes; the driver polls
|
||||
; each entry's HW_OWNER bit rather than tracking a separate hardware
|
||||
; "put index" register, which keeps the interrupt handler simple and
|
||||
; is exactly the same safety check Linux does per-entry regardless.
|
||||
;----------------------------------------------------------------------
|
||||
STAT_FIFO_ISR_WM= 0x0ead ; 8 bit Status FIFO ISR Watermark Reg
|
||||
|
||||
|
||||
STAT_LEV_TIMER_INI = 0x0eb0 ; 32 bit Level Timer Init. Value Reg
|
||||
STAT_LEV_TIMER_CTRL = 0x0eb8 ; 8 bit Level Timer Control Reg
|
||||
STAT_CTRL = 0x0E80 ; 32 bit
|
||||
STAT_LAST_IDX = 0x0E84 ; 16 bit
|
||||
STAT_LIST_ADDR_LO = 0x0E88 ; 32 bit
|
||||
STAT_LIST_ADDR_HI = 0x0E8C ; 32 bit
|
||||
STAT_TX_IDX_TH = 0x0E98 ; 16 bit
|
||||
STAT_PUT_IDX = 0x0E9C ; 16 bit
|
||||
STAT_FIFO_WM = 0x0EAC ; 8 bit
|
||||
STAT_TX_TIMER_INI = 0x0ec0 ; 32 bit Tx Timer Init. Value Reg
|
||||
STAT_ISR_TIMER_CNT = 0x0ed4 ; 32 bit ISR Timer Counter Reg
|
||||
STAT_ISR_TIMER_CTRL = 0x0ed8 ; 8 bit ISR Timer Control Reg
|
||||
STAT_TX_TIMER_CTRL = 0x0ec8 ; 8 bit Tx Timer Control Reg
|
||||
STAT_ISR_TIMER_INI = 0x0ed0 ; 32 bit ISR Timer Init. Value Reg
|
||||
|
||||
SC_STAT_OP_ON = 1 shl 3
|
||||
SC_STAT_RST_CLR = 1 shl 1
|
||||
SC_STAT_RST_SET = 1 shl 0
|
||||
SC_STAT_CLR_IRQ = 1 shl 4
|
||||
|
||||
;----------------------------------------------------------------------
|
||||
; Ring sizing. Both counts must be powers of two (ring-wrap uses a
|
||||
; mask, not a divide). Kept modest and identical to what RTL8169/
|
||||
; i8254x already use in this tree.
|
||||
;----------------------------------------------------------------------
|
||||
TX_LE_SIZE = 128 ; must be a power of 2, between 128 and 2048
|
||||
RX_LE_SIZE = 128 ; must be a power of 2, between 128 and 2048
|
||||
ST_RING_SIZE = 512 ; comfortably more than TX+RX combined
|
||||
RX_BUF_SIZE = 1536 ; MTU 1500 + Ethernet header + slack
|
||||
|
||||
;----------------------------------------------------------------------
|
||||
; Generic 8-byte list-element layout, shared by TX/RX/status rings
|
||||
; (see the LE ring comment above for the cross-reference).
|
||||
;----------------------------------------------------------------------
|
||||
struct le
|
||||
addr dd ?
|
||||
length dw ?
|
||||
ctrl db ? ; "css" on a status-ring entry
|
||||
opcode db ?
|
||||
ends
|
||||
|
||||
;----------------------------------------------------------------------
|
||||
; Device structure (extends ETH_DEVICE)
|
||||
;----------------------------------------------------------------------
|
||||
struct device ETH_DEVICE
|
||||
|
||||
; PCI / MMIO
|
||||
mmio_addr dd ?
|
||||
pci_bus dd ?
|
||||
pci_dev dd ?
|
||||
irq_line db ?
|
||||
rb 3
|
||||
|
||||
; Chip identification
|
||||
chip_id db ? ; CHIP_ID_YUKON_*
|
||||
chip_rev db ?
|
||||
port db ? ; 0 for single-port cards
|
||||
rb 1
|
||||
|
||||
chip_name dd ? ; pointer to ASCII name
|
||||
|
||||
; Link state, as last read from GM_GP_STAT (see link_status).
|
||||
; device.state (in ETH_DEVICE, standard kernel-facing field) is
|
||||
; kept in sync with these and is what NetLinkChanged reports.
|
||||
link_up db ? ; 0 = down, 1 = up
|
||||
link_duplex db ? ; 0 = half, 1 = full
|
||||
link_speed dw ? ; Mbps: 10 / 100 / 1000 (0 if link down)
|
||||
|
||||
; ---- TX/RX/status rings. Embedded directly in the device
|
||||
; struct, same pattern RTL8169 uses in this tree: the struct
|
||||
; itself is allocated via allocate_and_clear, which guarantees
|
||||
; physical contiguity up to 8 pages (32K) - our rings total
|
||||
; well under 2K, so this is safe. Raw byte reservation (not a
|
||||
; typed struct array) matching RTL8169's own tx_ring/rx_ring
|
||||
; convention - this struct.inc doesn't support array-of-custom-
|
||||
; struct fields, only single-instance nesting; per-entry access
|
||||
; is done via sizeof.le * slot_index offset math instead.
|
||||
|
||||
rb 0x1000-($ and 0xfff) ; align 256
|
||||
tx_le rb TX_LE_SIZE * sizeof.le
|
||||
|
||||
rb 0x1000-($ and 0xfff) ; align 256
|
||||
rx_le rb RX_LE_SIZE * sizeof.le
|
||||
|
||||
rb 0x1000-($ and 0xfff) ; align 256
|
||||
st_le rb ST_RING_SIZE * sizeof.le
|
||||
|
||||
; Software-only bookkeeping, parallel to the rings above but
|
||||
; NOT hardware-visible - just our own buffer-pointer tracking.
|
||||
; (NetAlloc'd pointer per slot; 0 = slot has no owned buffer.)
|
||||
tx_buf rd TX_LE_SIZE
|
||||
rx_buf rd RX_LE_SIZE
|
||||
|
||||
; Ring indices. All are plain 0-based slot numbers, wrapped
|
||||
; with a power-of-two mask (SIZE-1), not divided.
|
||||
tx_prod dw ? ; next free TX slot to fill
|
||||
tx_cons dw ? ; oldest TX slot still in flight
|
||||
rx_put dw ? ; next RX slot to (re)submit
|
||||
rx_next dw ? ; oldest RX slot awaiting completion
|
||||
st_idx dw ? ; next status-ring slot to read
|
||||
|
||||
ends
|
||||
|
||||
|
||||
|
||||
RX_GMF_CTRL_T = 0x0C48
|
||||
TX_GMF_CTRL_T = 0x0D48
|
||||
RX_GMF_LP_THR = 0x0C4A ; 8 bit Rx GMAC FIFO low pause threshold
|
||||
RX_GMF_UP_THR = 0x0C4B ; 8 bit Rx GMAC FIFO upper pause threshold
|
||||
GMF_RST_SET = 1 shl 0
|
||||
GMF_RST_CLR = 1 shl 1
|
||||
GMF_OPER_ON = 1 shl 3
|
||||
GMF_RX_F_FL_ON = 1 shl 7
|
||||
; TX GMF high bits (Yukon-EC Ultra) - store & forward required when no RAM
|
||||
TX_STFW_DIS = 1 shl 31
|
||||
TX_STFW_ENA = 1 shl 30
|
||||
TX_JUMBO_ENA = 1 shl 23
|
||||
TX_JUMBO_DIS = 1 shl 22
|
||||
|
||||
; RAM Interface (B3_*) - initialized during reset even when there is no
|
||||
; external RAM. Still required for the internal FIFO/GMF data path.
|
||||
B3_RI_WTO_R1 = 0x0190
|
||||
B3_RI_WTO_XA1 = 0x0191
|
||||
B3_RI_WTO_XS1 = 0x0192
|
||||
B3_RI_RTO_R1 = 0x0193
|
||||
B3_RI_RTO_XA1 = 0x0194
|
||||
B3_RI_RTO_XS1 = 0x0195
|
||||
B3_RI_WTO_R2 = 0x0196
|
||||
B3_RI_WTO_XA2 = 0x0197
|
||||
B3_RI_WTO_XS2 = 0x0198
|
||||
B3_RI_RTO_R2 = 0x0199
|
||||
B3_RI_RTO_XA2 = 0x019a
|
||||
B3_RI_RTO_XS2 = 0x019b
|
||||
B3_RI_CTRL = 0x01a0
|
||||
RI_RST_CLR = 1 shl 1
|
||||
RI_RST_SET = 1 shl 0
|
||||
SK_RI_TO_53 = 36 ; Linux/OpenBSD default timeout value
|
||||
|
||||
; GM_GP_CTRL extra bits (speed/duplex force)
|
||||
GM_GPCR_GIGS_ENA = 1 shl 7
|
||||
GM_GPCR_DUP_FULL = 1 shl 5
|
||||
GM_GPCR_SPEED_100 = 1 shl 3
|
||||
GM_GPCR_SPEED_1000 = (GM_GPCR_GIGS_ENA or GM_GPCR_SPEED_100)
|
||||
GM_GPCR_AU_DUP_DIS = 1 shl 2
|
||||
GM_GPCR_AU_FCT_DIS = 1 shl 1
|
||||
GM_GPCR_AU_SPD_DIS = 1 shl 0
|
||||
|
||||
TIM_START = 1 shl 2 ; ; Start Timer
|
||||
TIM_STOP = 1 shl 1 ; ; Stop Timer
|
||||
TIM_CLR_IRQ = 1 shl 0 ; ; Clear Timer IRQ (!IRQM)
|
||||
|
||||
|
||||
|
||||
GM_SRC_ADDR_1L = 0x001c;, ; 16 bit r/w Source Address 1 (low)
|
||||
GM_SRC_ADDR_1M = 0x0020;, ; 16 bit r/w Source Address 1 (middle)
|
||||
GM_SRC_ADDR_1H = 0x0024;, ; 16 bit r/w Source Address 1 (high)
|
||||
GM_SRC_ADDR_2L = 0x0028;, ; 16 bit r/w Source Address 2 (low)
|
||||
GM_SRC_ADDR_2M = 0x002c;, ; 16 bit r/w Source Address 2 (middle)
|
||||
GM_SRC_ADDR_2H = 0x0030;, ; 16 bit r/w Source Address 2 (high)
|
||||
|
||||
|
||||
|
||||
Y2_IS_HW_ERR = 1 shl 31 ; Interrupt HW Error
|
||||
Y2_IS_STAT_BMU = 1 shl 30 ; Status BMU Interrupt
|
||||
Y2_IS_ASF = 1 shl 29 ; ASF subsystem Interrupt
|
||||
Y2_IS_CPU_TO = 1 shl 28 ; CPU Timeout
|
||||
Y2_IS_POLL_CHK = 1 shl 27 ; Check IRQ from polling unit
|
||||
Y2_IS_TWSI_RDY = 1 shl 26 ; IRQ on end of TWSI Tx
|
||||
Y2_IS_IRQ_SW = 1 shl 25 ; SW forced IRQ
|
||||
Y2_IS_TIMINT = 1 shl 24 ; IRQ from Timer
|
||||
|
||||
Y2_IS_IRQ_PHY2 = 1 shl 12 ; Interrupt from PHY 2
|
||||
Y2_IS_IRQ_MAC2 = 1 shl 11 ; Interrupt from MAC 2
|
||||
Y2_IS_CHK_RX2 = 1 shl 10 ; Descriptor error Rx 2
|
||||
Y2_IS_CHK_TXS2 = 1 shl 9 ; Descriptor error TXS 2
|
||||
Y2_IS_CHK_TXA2 = 1 shl 8 ; Descriptor error TXA 2
|
||||
|
||||
Y2_IS_PSM_ACK = 1 shl 7 ; PSM Acknowledge (Yukon-Optima only)
|
||||
Y2_IS_PTP_TIST = 1 shl 6 ; PTP Time Stamp (Yukon-Optima only)
|
||||
Y2_IS_PHY_QLNK = 1 shl 5 ; PHY Quick Link (Yukon-Optima only)
|
||||
|
||||
Y2_IS_IRQ_PHY1 = 1 shl 4 ; Interrupt from PHY 1
|
||||
Y2_IS_IRQ_MAC1 = 1 shl 3 ; Interrupt from MAC 1
|
||||
Y2_IS_CHK_RX1 = 1 shl 2 ; Descriptor error Rx 1
|
||||
Y2_IS_CHK_TXS1 = 1 shl 1 ; Descriptor error TXS 1
|
||||
Y2_IS_CHK_TXA1 = 1 shl 0 ; Descriptor error TXA 1
|
||||
@@ -0,0 +1,68 @@
|
||||
#ifndef _ACPI_ACPI_H
|
||||
#define _ACPI_ACPI_H
|
||||
/*
|
||||
* Minimal ACPI-CA type surface for KolibriOS.
|
||||
*
|
||||
* CONFIG_ACPI is never defined here, so <linux/acpi.h> compiles only its
|
||||
* "no ACPI" branch - but that branch still mentions a handful of ACPI-CA
|
||||
* types in the signatures of its inline stubs. Those types are what this
|
||||
* header provides; there is no ACPI interpreter behind them.
|
||||
*/
|
||||
#include <linux/types.h>
|
||||
|
||||
typedef u32 acpi_status;
|
||||
typedef u32 acpi_object_type;
|
||||
typedef u64 acpi_size;
|
||||
typedef u64 acpi_io_address;
|
||||
typedef u64 acpi_physical_address;
|
||||
typedef void *acpi_handle;
|
||||
typedef char *acpi_string;
|
||||
|
||||
#define AE_OK ((acpi_status) 0x0000)
|
||||
#define AE_ERROR ((acpi_status) 0x0001)
|
||||
#define AE_NOT_FOUND ((acpi_status) 0x0005)
|
||||
#define AE_SUPPORT ((acpi_status) 0x001D)
|
||||
|
||||
#define ACPI_SUCCESS(a) ((a) == AE_OK)
|
||||
#define ACPI_FAILURE(a) ((a) != AE_OK)
|
||||
|
||||
#define ACPI_TYPE_INTEGER 0x01
|
||||
#define ACPI_TYPE_STRING 0x02
|
||||
#define ACPI_TYPE_BUFFER 0x03
|
||||
#define ACPI_TYPE_PACKAGE 0x04
|
||||
#define ACPI_TYPE_ANY 0x00
|
||||
|
||||
union acpi_object {
|
||||
acpi_object_type type;
|
||||
struct {
|
||||
acpi_object_type type;
|
||||
u64 value;
|
||||
} integer;
|
||||
struct {
|
||||
acpi_object_type type;
|
||||
u32 length;
|
||||
char *pointer;
|
||||
} string;
|
||||
struct {
|
||||
acpi_object_type type;
|
||||
u32 length;
|
||||
u8 *pointer;
|
||||
} buffer;
|
||||
struct {
|
||||
acpi_object_type type;
|
||||
u32 count;
|
||||
union acpi_object *elements;
|
||||
} package;
|
||||
};
|
||||
|
||||
struct acpi_buffer {
|
||||
acpi_size length;
|
||||
void *pointer;
|
||||
};
|
||||
|
||||
struct acpi_object_list {
|
||||
u32 count;
|
||||
union acpi_object *pointer;
|
||||
};
|
||||
|
||||
#endif /* _ACPI_ACPI_H */
|
||||
@@ -0,0 +1,13 @@
|
||||
#ifndef ACPI_BUTTON_H
|
||||
#define ACPI_BUTTON_H
|
||||
#include <linux/errno.h>
|
||||
#include <linux/notifier.h>
|
||||
/*
|
||||
* nouveau_connector.c asks the ACPI lid device whether the panel is open
|
||||
* before trusting an LVDS hotplug. No ACPI here, so report "open" - the same
|
||||
* answer the upstream !CONFIG_ACPI_BUTTON stub gives.
|
||||
*/
|
||||
static inline int acpi_lid_open(void) { return 1; }
|
||||
static inline int acpi_lid_notifier_register(struct notifier_block *nb) { return -ENODEV; }
|
||||
static inline int acpi_lid_notifier_unregister(struct notifier_block *nb) { return -ENODEV; }
|
||||
#endif
|
||||
@@ -0,0 +1,40 @@
|
||||
#ifndef _ACPI_PDC_INTEL_H
|
||||
#define _ACPI_PDC_INTEL_H
|
||||
/*
|
||||
* Intel _PDC / _OSC capability bits, included unconditionally by <asm/acpi.h>.
|
||||
*
|
||||
* Nothing here evaluates these - KolibriOS drivers never negotiate processor
|
||||
* capabilities with the firmware - but the definitions have to exist for
|
||||
* <linux/acpi.h> to be includable at all. Values match the kernel's
|
||||
* include/acpi/pdc_intel.h.
|
||||
*/
|
||||
|
||||
#define ACPI_PDC_P_FFH (0x0001)
|
||||
#define ACPI_PDC_C_C1_HALT (0x0002)
|
||||
#define ACPI_PDC_T_FFH (0x0004)
|
||||
#define ACPI_PDC_SMP_C1PT (0x0008)
|
||||
#define ACPI_PDC_SMP_C2C3 (0x0010)
|
||||
#define ACPI_PDC_SMP_P_SWCOORD (0x0020)
|
||||
#define ACPI_PDC_SMP_C_SWCOORD (0x0040)
|
||||
#define ACPI_PDC_SMP_T_SWCOORD (0x0080)
|
||||
#define ACPI_PDC_C_C1_FFH (0x0100)
|
||||
#define ACPI_PDC_C_C2C3_FFH (0x0200)
|
||||
#define ACPI_PDC_SMP_P_HWCOORD (0x0800)
|
||||
|
||||
#define ACPI_PDC_EST_CAPABILITY_SMP (ACPI_PDC_SMP_C1PT | \
|
||||
ACPI_PDC_C_C1_HALT | \
|
||||
ACPI_PDC_P_FFH)
|
||||
|
||||
#define ACPI_PDC_EST_CAPABILITY_SWSMP (ACPI_PDC_SMP_C1PT | \
|
||||
ACPI_PDC_C_C1_HALT | \
|
||||
ACPI_PDC_SMP_P_SWCOORD | \
|
||||
ACPI_PDC_SMP_P_HWCOORD | \
|
||||
ACPI_PDC_P_FFH)
|
||||
|
||||
#define ACPI_PDC_C_CAPABILITY_SMP (ACPI_PDC_SMP_C2C3 | \
|
||||
ACPI_PDC_SMP_C1PT | \
|
||||
ACPI_PDC_C_C1_HALT | \
|
||||
ACPI_PDC_C_C1_FFH | \
|
||||
ACPI_PDC_C_C2C3_FFH)
|
||||
|
||||
#endif /* _ACPI_PDC_INTEL_H */
|
||||
@@ -0,0 +1,18 @@
|
||||
#ifndef __ACPI_VIDEO_H
|
||||
#define __ACPI_VIDEO_H
|
||||
/* No ACPI video extensions; nouveau_display.c only calls the register hook. */
|
||||
#include <linux/errno.h>
|
||||
|
||||
enum acpi_backlight_type {
|
||||
acpi_backlight_undef = -1,
|
||||
acpi_backlight_none = 0,
|
||||
acpi_backlight_video,
|
||||
acpi_backlight_vendor,
|
||||
acpi_backlight_native,
|
||||
};
|
||||
|
||||
static inline int acpi_video_register(void) { return -ENODEV; }
|
||||
static inline void acpi_video_unregister(void) { }
|
||||
static inline enum acpi_backlight_type acpi_video_get_backlight_type(void)
|
||||
{ return acpi_backlight_vendor; }
|
||||
#endif
|
||||
@@ -85,6 +85,9 @@ dma_supported(struct device *dev, u64 mask);
|
||||
extern int
|
||||
dma_set_mask(struct device *dev, u64 mask);
|
||||
|
||||
extern int
|
||||
dma_set_coherent_mask(struct device *dev, u64 mask);
|
||||
|
||||
extern int
|
||||
dma_get_cache_alignment(void);
|
||||
|
||||
|
||||
@@ -315,6 +315,18 @@ extern bool xen_biovec_phys_mergeable(const struct bio_vec *vec1,
|
||||
|
||||
#define IO_SPACE_LIMIT 0xffff
|
||||
|
||||
/*
|
||||
* Write-combining range management. Upstream declares these under
|
||||
* CONFIG_MTRR and provides !MTRR fallbacks from <linux/io.h>, which this tree
|
||||
* does not carry - so they are declared unconditionally here and implemented
|
||||
* as no-ops by each driver's kos_io.c. arch_io_*_memtype_wc() is the 4.9
|
||||
* spelling that came in with the PAT rework.
|
||||
*/
|
||||
extern int __must_check arch_phys_wc_add(unsigned long base, unsigned long size);
|
||||
extern void arch_phys_wc_del(int handle);
|
||||
extern int arch_io_reserve_memtype_wc(resource_size_t start, resource_size_t size);
|
||||
extern void arch_io_free_memtype_wc(resource_size_t start, resource_size_t size);
|
||||
|
||||
#ifdef CONFIG_MTRR
|
||||
extern int __must_check arch_phys_wc_index(int handle);
|
||||
#define arch_phys_wc_index arch_phys_wc_index
|
||||
|
||||
@@ -359,6 +359,13 @@ struct drm_file {
|
||||
int event_space;
|
||||
|
||||
struct mutex event_read_lock;
|
||||
|
||||
/*
|
||||
* Upstream stores the opening process here. Nothing opens a DRM node
|
||||
* on this port, so it stays NULL; nouveau_drm.c only feeds it to
|
||||
* pid_nr() when it names a client.
|
||||
*/
|
||||
struct pid *pid;
|
||||
};
|
||||
|
||||
/**
|
||||
@@ -678,6 +685,14 @@ struct drm_device {
|
||||
/*@} */
|
||||
|
||||
struct list_head filelist;
|
||||
/*
|
||||
* Backported from Linux 4.9, which moved filelist from under
|
||||
* struct_mutex to its own lock. Nothing in the 4.6 core takes it, so
|
||||
* it only ever serialises the driver against itself.
|
||||
*/
|
||||
struct mutex filelist_mutex;
|
||||
/* Backported from Linux 4.9; unused without a real inode layer. */
|
||||
struct inode *anon_inode;
|
||||
|
||||
/** \name Memory management */
|
||||
/*@{ */
|
||||
@@ -748,6 +763,12 @@ struct drm_device {
|
||||
// struct drm_agp_head *agp; /**< AGP data */
|
||||
|
||||
struct pci_dev *pdev; /**< PCI device structure */
|
||||
/*
|
||||
* Always NULL here - no platform bus. nouveau_drm.c branches on
|
||||
* pdev vs platformdev when it builds the device name, and the
|
||||
* Tegra half of that branch is never taken.
|
||||
*/
|
||||
struct platform_device *platformdev;
|
||||
#ifdef __alpha__
|
||||
struct pci_controller *hose;
|
||||
#endif
|
||||
@@ -981,6 +1002,15 @@ static __inline__ int drm_pci_device_is_agp(struct drm_device *dev)
|
||||
}
|
||||
void drm_pci_agp_destroy(struct drm_device *dev);
|
||||
|
||||
/*
|
||||
* Implemented in drm_pci.c and the entry point every port's probe calls, but
|
||||
* its upstream declaration is in the "#if 0" block below - so each main.c used
|
||||
* to declare it by hand. Declared here instead.
|
||||
*/
|
||||
extern int drm_get_pci_dev(struct pci_dev *pdev,
|
||||
const struct pci_device_id *ent,
|
||||
struct drm_driver *driver);
|
||||
|
||||
#if 0
|
||||
extern int drm_pci_init(struct drm_driver *driver, struct pci_driver *pdriver);
|
||||
extern void drm_pci_exit(struct drm_driver *driver, struct pci_driver *pdriver);
|
||||
|
||||
@@ -152,6 +152,13 @@ struct drm_display_info {
|
||||
u8 edid_hdmi_dc_modes;
|
||||
|
||||
u8 cea_rev;
|
||||
|
||||
/*
|
||||
* Backported from Linux 4.9: maximum TMDS clock in kHz advertised by an
|
||||
* HDMI sink. drm_edid.c in this tree does not fill it in yet, so it
|
||||
* stays 0 and drivers fall back to their built-in limit.
|
||||
*/
|
||||
int max_tmds_clock;
|
||||
};
|
||||
|
||||
/* data corresponds to displayid vend/prod/serial */
|
||||
@@ -701,6 +708,17 @@ struct drm_crtc_funcs {
|
||||
const struct drm_crtc_state *state,
|
||||
struct drm_property *property,
|
||||
uint64_t *val);
|
||||
|
||||
/*
|
||||
* Backported from Linux 4.9 for the amdgpu port. The 4.6 DRM core in
|
||||
* this tree never calls these; they exist so that drivers written
|
||||
* against the newer struct layout still compile and keep their hooks.
|
||||
*/
|
||||
void (*early_unregister)(struct drm_crtc *crtc);
|
||||
int (*page_flip_target)(struct drm_crtc *crtc,
|
||||
struct drm_framebuffer *fb,
|
||||
struct drm_pending_vblank_event *event,
|
||||
uint32_t flags, uint32_t target);
|
||||
};
|
||||
|
||||
/**
|
||||
@@ -1044,6 +1062,9 @@ struct drm_connector_funcs {
|
||||
const struct drm_connector_state *state,
|
||||
struct drm_property *property,
|
||||
uint64_t *val);
|
||||
|
||||
/* Backported from Linux 4.9 - see drm_crtc_funcs::early_unregister. */
|
||||
void (*early_unregister)(struct drm_connector *connector);
|
||||
};
|
||||
|
||||
/**
|
||||
@@ -1069,6 +1090,9 @@ struct drm_encoder_funcs {
|
||||
* hotplugged in DRM.
|
||||
*/
|
||||
void (*destroy)(struct drm_encoder *encoder);
|
||||
|
||||
/* Backported from Linux 4.9 - see drm_crtc_funcs::early_unregister. */
|
||||
void (*early_unregister)(struct drm_encoder *encoder);
|
||||
};
|
||||
|
||||
#define DRM_CONNECTOR_MAX_ENCODER 3
|
||||
@@ -1490,6 +1514,9 @@ struct drm_plane_funcs {
|
||||
const struct drm_plane_state *state,
|
||||
struct drm_property *property,
|
||||
uint64_t *val);
|
||||
|
||||
/* Backported from Linux 4.9 - see drm_crtc_funcs::early_unregister. */
|
||||
void (*early_unregister)(struct drm_plane *plane);
|
||||
};
|
||||
|
||||
enum drm_plane_type {
|
||||
|
||||
@@ -43,6 +43,15 @@
|
||||
#include <drm/drm_modeset_helper_vtables.h>
|
||||
|
||||
extern void drm_helper_disable_unused_functions(struct drm_device *dev);
|
||||
|
||||
/*
|
||||
* Added after 4.6 and implemented by each port's kos_stubs.c:
|
||||
* drm_crtc_force_disable_all() is 4.9's unload-time "turn everything off",
|
||||
* and drm_kms_helper_is_poll_worker() is how 4.9 avoids deadlocking against
|
||||
* its own hotplug worker - there is no such worker here.
|
||||
*/
|
||||
extern void drm_crtc_force_disable_all(struct drm_device *dev);
|
||||
extern bool drm_kms_helper_is_poll_worker(void);
|
||||
extern int drm_crtc_helper_set_config(struct drm_mode_set *set);
|
||||
extern bool drm_crtc_helper_set_mode(struct drm_crtc *crtc,
|
||||
struct drm_display_mode *mode,
|
||||
|
||||
@@ -0,0 +1,182 @@
|
||||
/*
|
||||
* Copyright (C) 2009 Francisco Jerez.
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining
|
||||
* a copy of this software and associated documentation files (the
|
||||
* "Software"), to deal in the Software without restriction, including
|
||||
* without limitation the rights to use, copy, modify, merge, publish,
|
||||
* distribute, sublicense, and/or sell copies of the Software, and to
|
||||
* permit persons to whom the Software is furnished to do so, subject to
|
||||
* the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the
|
||||
* next paragraph) shall be included in all copies or substantial
|
||||
* portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
|
||||
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
|
||||
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
|
||||
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __DRM_ENCODER_SLAVE_H__
|
||||
#define __DRM_ENCODER_SLAVE_H__
|
||||
|
||||
#include <drm/drmP.h>
|
||||
#include <drm/drm_crtc.h>
|
||||
|
||||
/**
|
||||
* struct drm_encoder_slave_funcs - Entry points exposed by a slave encoder driver
|
||||
* @set_config: Initialize any encoder-specific modesetting parameters.
|
||||
* The meaning of the @params parameter is implementation
|
||||
* dependent. It will usually be a structure with DVO port
|
||||
* data format settings or timings. It's not required for
|
||||
* the new parameters to take effect until the next mode
|
||||
* is set.
|
||||
*
|
||||
* Most of its members are analogous to the function pointers in
|
||||
* &drm_encoder_helper_funcs and they can optionally be used to
|
||||
* initialize the latter. Connector-like methods (e.g. @get_modes and
|
||||
* @set_property) will typically be wrapped around and only be called
|
||||
* if the encoder is the currently selected one for the connector.
|
||||
*/
|
||||
struct drm_encoder_slave_funcs {
|
||||
void (*set_config)(struct drm_encoder *encoder,
|
||||
void *params);
|
||||
|
||||
void (*destroy)(struct drm_encoder *encoder);
|
||||
void (*dpms)(struct drm_encoder *encoder, int mode);
|
||||
void (*save)(struct drm_encoder *encoder);
|
||||
void (*restore)(struct drm_encoder *encoder);
|
||||
bool (*mode_fixup)(struct drm_encoder *encoder,
|
||||
const struct drm_display_mode *mode,
|
||||
struct drm_display_mode *adjusted_mode);
|
||||
int (*mode_valid)(struct drm_encoder *encoder,
|
||||
struct drm_display_mode *mode);
|
||||
void (*mode_set)(struct drm_encoder *encoder,
|
||||
struct drm_display_mode *mode,
|
||||
struct drm_display_mode *adjusted_mode);
|
||||
|
||||
enum drm_connector_status (*detect)(struct drm_encoder *encoder,
|
||||
struct drm_connector *connector);
|
||||
int (*get_modes)(struct drm_encoder *encoder,
|
||||
struct drm_connector *connector);
|
||||
int (*create_resources)(struct drm_encoder *encoder,
|
||||
struct drm_connector *connector);
|
||||
int (*set_property)(struct drm_encoder *encoder,
|
||||
struct drm_connector *connector,
|
||||
struct drm_property *property,
|
||||
uint64_t val);
|
||||
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_encoder_slave - Slave encoder struct
|
||||
* @base: DRM encoder object.
|
||||
* @slave_funcs: Slave encoder callbacks.
|
||||
* @slave_priv: Slave encoder private data.
|
||||
* @bus_priv: Bus specific data.
|
||||
*
|
||||
* A &drm_encoder_slave has two sets of callbacks, @slave_funcs and the
|
||||
* ones in @base. The former are never actually called by the common
|
||||
* CRTC code, it's just a convenience for splitting the encoder
|
||||
* functions in an upper, GPU-specific layer and a (hopefully)
|
||||
* GPU-agnostic lower layer: It's the GPU driver responsibility to
|
||||
* call the slave methods when appropriate.
|
||||
*
|
||||
* drm_i2c_encoder_init() provides a way to get an implementation of
|
||||
* this.
|
||||
*/
|
||||
struct drm_encoder_slave {
|
||||
struct drm_encoder base;
|
||||
|
||||
const struct drm_encoder_slave_funcs *slave_funcs;
|
||||
void *slave_priv;
|
||||
void *bus_priv;
|
||||
};
|
||||
#define to_encoder_slave(x) container_of((x), struct drm_encoder_slave, base)
|
||||
|
||||
int drm_i2c_encoder_init(struct drm_device *dev,
|
||||
struct drm_encoder_slave *encoder,
|
||||
struct i2c_adapter *adap,
|
||||
const struct i2c_board_info *info);
|
||||
|
||||
|
||||
/**
|
||||
* struct drm_i2c_encoder_driver
|
||||
*
|
||||
* Describes a device driver for an encoder connected to the GPU
|
||||
* through an I2C bus. In addition to the entry points in @i2c_driver
|
||||
* an @encoder_init function should be provided. It will be called to
|
||||
* give the driver an opportunity to allocate any per-encoder data
|
||||
* structures and to initialize the @slave_funcs and (optionally)
|
||||
* @slave_priv members of @encoder.
|
||||
*/
|
||||
struct drm_i2c_encoder_driver {
|
||||
struct i2c_driver i2c_driver;
|
||||
|
||||
int (*encoder_init)(struct i2c_client *client,
|
||||
struct drm_device *dev,
|
||||
struct drm_encoder_slave *encoder);
|
||||
|
||||
};
|
||||
#define to_drm_i2c_encoder_driver(x) container_of((x), \
|
||||
struct drm_i2c_encoder_driver, \
|
||||
i2c_driver)
|
||||
|
||||
/**
|
||||
* drm_i2c_encoder_get_client - Get the I2C client corresponding to an encoder
|
||||
*/
|
||||
static inline struct i2c_client *drm_i2c_encoder_get_client(struct drm_encoder *encoder)
|
||||
{
|
||||
return (struct i2c_client *)to_encoder_slave(encoder)->bus_priv;
|
||||
}
|
||||
|
||||
/**
|
||||
* drm_i2c_encoder_register - Register an I2C encoder driver
|
||||
* @owner: Module containing the driver.
|
||||
* @driver: Driver to be registered.
|
||||
*/
|
||||
static inline int drm_i2c_encoder_register(struct module *owner,
|
||||
struct drm_i2c_encoder_driver *driver)
|
||||
{
|
||||
return i2c_register_driver(owner, &driver->i2c_driver);
|
||||
}
|
||||
|
||||
/**
|
||||
* drm_i2c_encoder_unregister - Unregister an I2C encoder driver
|
||||
* @driver: Driver to be unregistered.
|
||||
*/
|
||||
static inline void drm_i2c_encoder_unregister(struct drm_i2c_encoder_driver *driver)
|
||||
{
|
||||
i2c_del_driver(&driver->i2c_driver);
|
||||
}
|
||||
|
||||
void drm_i2c_encoder_destroy(struct drm_encoder *encoder);
|
||||
|
||||
|
||||
/*
|
||||
* Wrapper fxns which can be plugged in to drm_encoder_helper_funcs:
|
||||
*/
|
||||
|
||||
void drm_i2c_encoder_dpms(struct drm_encoder *encoder, int mode);
|
||||
bool drm_i2c_encoder_mode_fixup(struct drm_encoder *encoder,
|
||||
const struct drm_display_mode *mode,
|
||||
struct drm_display_mode *adjusted_mode);
|
||||
void drm_i2c_encoder_prepare(struct drm_encoder *encoder);
|
||||
void drm_i2c_encoder_commit(struct drm_encoder *encoder);
|
||||
void drm_i2c_encoder_mode_set(struct drm_encoder *encoder,
|
||||
struct drm_display_mode *mode,
|
||||
struct drm_display_mode *adjusted_mode);
|
||||
enum drm_connector_status drm_i2c_encoder_detect(struct drm_encoder *encoder,
|
||||
struct drm_connector *connector);
|
||||
void drm_i2c_encoder_save(struct drm_encoder *encoder);
|
||||
void drm_i2c_encoder_restore(struct drm_encoder *encoder);
|
||||
|
||||
|
||||
#endif
|
||||
@@ -226,6 +226,14 @@ int drm_fb_helper_init(struct drm_device *dev,
|
||||
struct drm_fb_helper *helper, int crtc_count,
|
||||
int max_conn);
|
||||
void drm_fb_helper_fini(struct drm_fb_helper *helper);
|
||||
|
||||
/*
|
||||
* 4.9's fbdev handover. There is no other framebuffer driver to evict on
|
||||
* KolibriOS; implemented in each port's kos_stubs.c.
|
||||
*/
|
||||
struct apertures_struct;
|
||||
int drm_fb_helper_remove_conflicting_framebuffers(struct apertures_struct *a,
|
||||
const char *name, bool primary);
|
||||
int drm_fb_helper_blank(int blank, struct fb_info *info);
|
||||
int drm_fb_helper_pan_display(struct fb_var_screeninfo *var,
|
||||
struct fb_info *info);
|
||||
|
||||
@@ -0,0 +1,10 @@
|
||||
#ifndef _DRM_FOURCC_SHIM_H
|
||||
#define _DRM_FOURCC_SHIM_H
|
||||
/*
|
||||
* The tree keeps the format list in uapi/ and the in-kernel helpers in
|
||||
* drm_crtc.h. Upstream drivers include <drm/drm_fourcc.h>; give them that
|
||||
* spelling instead of patching every call site. The guard is deliberately
|
||||
* distinct from the uapi header's own.
|
||||
*/
|
||||
#include <uapi/drm/drm_fourcc.h>
|
||||
#endif
|
||||
@@ -0,0 +1,9 @@
|
||||
#ifndef _DRM_MODE_SHIM_H
|
||||
#define _DRM_MODE_SHIM_H
|
||||
/*
|
||||
* Same reason as drm_fourcc.h: upstream drivers spell this <drm/drm_mode.h>
|
||||
* while the tree keeps it under uapi/. The guard deliberately does not match
|
||||
* the uapi header's own _DRM_MODE_H, or including this first would suppress it.
|
||||
*/
|
||||
#include <uapi/drm/drm_mode.h>
|
||||
#endif
|
||||
@@ -0,0 +1,86 @@
|
||||
/*
|
||||
* Copyright (C) 2009 Francisco Jerez.
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining
|
||||
* a copy of this software and associated documentation files (the
|
||||
* "Software"), to deal in the Software without restriction, including
|
||||
* without limitation the rights to use, copy, modify, merge, publish,
|
||||
* distribute, sublicense, and/or sell copies of the Software, and to
|
||||
* permit persons to whom the Software is furnished to do so, subject to
|
||||
* the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the
|
||||
* next paragraph) shall be included in all copies or substantial
|
||||
* portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
|
||||
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
|
||||
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
|
||||
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __DRM_I2C_CH7006_H__
|
||||
#define __DRM_I2C_CH7006_H__
|
||||
|
||||
/**
|
||||
* struct ch7006_encoder_params
|
||||
*
|
||||
* Describes how the ch7006 is wired up with the GPU. It should be
|
||||
* used as the @params parameter of its @set_config method.
|
||||
*
|
||||
* See "http://www.chrontel.com/pdf/7006.pdf" for their precise
|
||||
* meaning.
|
||||
*/
|
||||
struct ch7006_encoder_params {
|
||||
enum {
|
||||
CH7006_FORMAT_RGB16 = 0,
|
||||
CH7006_FORMAT_YCrCb24m16,
|
||||
CH7006_FORMAT_RGB24m16,
|
||||
CH7006_FORMAT_RGB15,
|
||||
CH7006_FORMAT_RGB24m12C,
|
||||
CH7006_FORMAT_RGB24m12I,
|
||||
CH7006_FORMAT_RGB24m8,
|
||||
CH7006_FORMAT_RGB16m8,
|
||||
CH7006_FORMAT_RGB15m8,
|
||||
CH7006_FORMAT_YCrCb24m8,
|
||||
} input_format;
|
||||
|
||||
enum {
|
||||
CH7006_CLOCK_SLAVE = 0,
|
||||
CH7006_CLOCK_MASTER,
|
||||
} clock_mode;
|
||||
|
||||
enum {
|
||||
CH7006_CLOCK_EDGE_NEG = 0,
|
||||
CH7006_CLOCK_EDGE_POS,
|
||||
} clock_edge;
|
||||
|
||||
int xcm, pcm;
|
||||
|
||||
enum {
|
||||
CH7006_SYNC_SLAVE = 0,
|
||||
CH7006_SYNC_MASTER,
|
||||
} sync_direction;
|
||||
|
||||
enum {
|
||||
CH7006_SYNC_SEPARATED = 0,
|
||||
CH7006_SYNC_EMBEDDED,
|
||||
} sync_encoding;
|
||||
|
||||
enum {
|
||||
CH7006_POUT_1_8V = 0,
|
||||
CH7006_POUT_3_3V,
|
||||
} pout_level;
|
||||
|
||||
enum {
|
||||
CH7006_ACTIVE_HSYNC = 0,
|
||||
CH7006_ACTIVE_DSTART,
|
||||
} active_detect;
|
||||
};
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,63 @@
|
||||
/*
|
||||
* Copyright (C) 2010 Francisco Jerez.
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining
|
||||
* a copy of this software and associated documentation files (the
|
||||
* "Software"), to deal in the Software without restriction, including
|
||||
* without limitation the rights to use, copy, modify, merge, publish,
|
||||
* distribute, sublicense, and/or sell copies of the Software, and to
|
||||
* permit persons to whom the Software is furnished to do so, subject to
|
||||
* the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the
|
||||
* next paragraph) shall be included in all copies or substantial
|
||||
* portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
|
||||
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
|
||||
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
|
||||
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __DRM_I2C_SIL164_H__
|
||||
#define __DRM_I2C_SIL164_H__
|
||||
|
||||
/**
|
||||
* struct sil164_encoder_params
|
||||
*
|
||||
* Describes how the sil164 is connected to the GPU. It should be used
|
||||
* as the @params parameter of its @set_config method.
|
||||
*
|
||||
* See "http://www.siliconimage.com/docs/SiI-DS-0021-E-164.pdf".
|
||||
*/
|
||||
struct sil164_encoder_params {
|
||||
enum {
|
||||
SIL164_INPUT_EDGE_FALLING = 0,
|
||||
SIL164_INPUT_EDGE_RISING
|
||||
} input_edge;
|
||||
|
||||
enum {
|
||||
SIL164_INPUT_WIDTH_12BIT = 0,
|
||||
SIL164_INPUT_WIDTH_24BIT
|
||||
} input_width;
|
||||
|
||||
enum {
|
||||
SIL164_INPUT_SINGLE_EDGE = 0,
|
||||
SIL164_INPUT_DUAL_EDGE
|
||||
} input_dual;
|
||||
|
||||
enum {
|
||||
SIL164_PLL_FILTER_ON = 0,
|
||||
SIL164_PLL_FILTER_OFF,
|
||||
} pll_filter;
|
||||
|
||||
int input_skew; /** < Allowed range [-4, 3], use 0 for no de-skew. */
|
||||
int duallink_skew; /** < Allowed range [-4, 3]. */
|
||||
};
|
||||
|
||||
#endif
|
||||
@@ -257,6 +257,15 @@ struct ttm_buffer_object {
|
||||
struct reservation_object *resv;
|
||||
struct reservation_object ttm_resv;
|
||||
struct mutex wu_mutex;
|
||||
|
||||
/*
|
||||
* Backported from Linux 4.9: fence of the last accelerated move, kept
|
||||
* outside the reservation object so a pipelined eviction can be waited
|
||||
* on without blocking other users. The 4.6 TTM in this tree still
|
||||
* waits synchronously, so the core leaves this NULL; amdgpu sets and
|
||||
* checks it on its own paths.
|
||||
*/
|
||||
struct fence *moving;
|
||||
};
|
||||
|
||||
/**
|
||||
|
||||
@@ -434,8 +434,20 @@ struct ttm_bo_driver {
|
||||
*/
|
||||
int (*io_mem_reserve)(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem);
|
||||
void (*io_mem_free)(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem);
|
||||
|
||||
/*
|
||||
* Backported from Linux 4.9 for the amdgpu port. The 4.6 TTM in this
|
||||
* tree does not consult these hooks - it always uses the default LRU
|
||||
* placement - but drivers written against 4.9 still populate them.
|
||||
*/
|
||||
void (*lru_removal)(struct ttm_buffer_object *bo);
|
||||
struct list_head *(*lru_tail)(struct ttm_buffer_object *bo);
|
||||
struct list_head *(*swap_lru_tail)(struct ttm_buffer_object *bo);
|
||||
};
|
||||
|
||||
struct list_head *ttm_bo_default_lru_tail(struct ttm_buffer_object *bo);
|
||||
struct list_head *ttm_bo_default_swap_lru_tail(struct ttm_buffer_object *bo);
|
||||
|
||||
/**
|
||||
* struct ttm_bo_global_ref - Argument to initialize a struct ttm_bo_global.
|
||||
*/
|
||||
|
||||
@@ -0,0 +1,21 @@
|
||||
#ifndef _LINUX_CLK_H
|
||||
#define _LINUX_CLK_H
|
||||
/*
|
||||
* Tegra-only. nvif/os.h pulls this in unconditionally, but the only nouveau
|
||||
* code that calls a clk_* helper is nvkm/engine/device/tegra.c, which this
|
||||
* port does not build.
|
||||
*/
|
||||
#include <linux/errno.h>
|
||||
#include <linux/err.h>
|
||||
|
||||
struct clk;
|
||||
struct device;
|
||||
|
||||
static inline struct clk *clk_get(struct device *dev, const char *id)
|
||||
{ return ERR_PTR(-ENOENT); }
|
||||
static inline void clk_put(struct clk *clk) { }
|
||||
static inline int clk_prepare_enable(struct clk *clk) { return -ENOSYS; }
|
||||
static inline void clk_disable_unprepare(struct clk *clk) { }
|
||||
static inline unsigned long clk_get_rate(struct clk *clk) { return 0; }
|
||||
static inline int clk_set_rate(struct clk *clk, unsigned long rate) { return -ENOSYS; }
|
||||
#endif
|
||||
@@ -0,0 +1,14 @@
|
||||
#ifndef _LINUX_CONSOLE_H
|
||||
#define _LINUX_CONSOLE_H
|
||||
/* KolibriOS has no VT console layer; the fbdev handover hooks are no-ops. */
|
||||
#define CON_PRINTBUFFER (1)
|
||||
#define CON_CONSDEV (2)
|
||||
#define CON_ENABLED (4)
|
||||
#define CON_BOOT (8)
|
||||
#define CON_ANYTIME (16)
|
||||
#define CON_BRL (32)
|
||||
|
||||
static inline void console_lock(void) { }
|
||||
static inline void console_unlock(void) { }
|
||||
static inline int console_trylock(void) { return 1; }
|
||||
#endif
|
||||
@@ -0,0 +1,7 @@
|
||||
#ifndef _LINUX_DEBUGFS_H
|
||||
#define _LINUX_DEBUGFS_H
|
||||
/* No debugfs in KolibriOS - CONFIG_DEBUG_FS is never defined. */
|
||||
#include <linux/types.h>
|
||||
struct dentry;
|
||||
struct file_operations;
|
||||
#endif
|
||||
@@ -31,6 +31,12 @@ enum probe_type {
|
||||
|
||||
struct device_driver {
|
||||
const char *name;
|
||||
/*
|
||||
* Restored for drm_encoder_slave.c, which pins the slave encoder's
|
||||
* module around a bind. Nothing is ever bound on this port, so it
|
||||
* stays NULL and try_module_get()/module_put() are no-ops.
|
||||
*/
|
||||
struct module *owner;
|
||||
const char *mod_name; /* used for built-in modules */
|
||||
|
||||
bool suppress_bind_attrs; /* disables bind/unbind via sysfs */
|
||||
@@ -126,5 +132,28 @@ static inline __printf(2, 3)
|
||||
void dev_notice(const struct device *dev, const char *fmt, ...)
|
||||
{}
|
||||
|
||||
/*
|
||||
* sysfs attribute types. KolibriOS has no sysfs, so nothing ever walks these
|
||||
* tables - but drivers still declare them at file scope, so the layout has to
|
||||
* exist. Matches the upstream definitions field for field.
|
||||
*/
|
||||
#include <linux/sysfs.h>
|
||||
|
||||
struct device_attribute {
|
||||
struct attribute attr;
|
||||
ssize_t (*show)(struct device *dev, struct device_attribute *attr,
|
||||
char *buf);
|
||||
ssize_t (*store)(struct device *dev, struct device_attribute *attr,
|
||||
const char *buf, size_t count);
|
||||
};
|
||||
|
||||
#define __ATTR(_name, _mode, _show, _store) { \
|
||||
.attr = { .name = __stringify(_name), .mode = (_mode) }, \
|
||||
.show = _show, \
|
||||
.store = _store, \
|
||||
}
|
||||
|
||||
#define DEVICE_ATTR(_name, _mode, _show, _store) \
|
||||
struct device_attribute dev_attr_##_name = __ATTR(_name, _mode, _show, _store)
|
||||
|
||||
#endif /* _DEVICE_H_ */
|
||||
@@ -131,6 +131,12 @@ struct dma_buf {
|
||||
const char *exp_name;
|
||||
struct list_head list_node;
|
||||
void *priv;
|
||||
/*
|
||||
* Upstream keeps the exporter's reservation object here. No dma-buf
|
||||
* is ever created on this port, so nouveau_prime.c's import path is
|
||||
* dead code - but it dereferences the field, so it has to exist.
|
||||
*/
|
||||
struct reservation_object *resv;
|
||||
};
|
||||
|
||||
/**
|
||||
|
||||
@@ -0,0 +1,7 @@
|
||||
#ifndef _LINUX_EFI_H
|
||||
#define _LINUX_EFI_H
|
||||
/* KolibriOS boots via BIOS only; amdgpu only tests efi_enabled(). */
|
||||
#define EFI_BOOT 0
|
||||
#define EFI_RUNTIME_SERVICES 1
|
||||
static inline bool efi_enabled(int feature) { return false; }
|
||||
#endif
|
||||
@@ -470,7 +470,12 @@ struct fb_info {
|
||||
struct fb_fix_screeninfo fix; /* Current fix */
|
||||
struct fb_monspecs monspecs; /* Current Monitor specs */
|
||||
// struct work_struct queue; /* Framebuffer event queue */
|
||||
// struct fb_pixmap pixmap; /* Image hardware mapper */
|
||||
/*
|
||||
* Restored for nouveau, which sets pixmap.buf_align after
|
||||
* drm_fb_helper_initial_config(). Nothing on this port consumes the
|
||||
* field - there is no fbcon - but the assignment has to compile.
|
||||
*/
|
||||
struct fb_pixmap pixmap; /* Image hardware mapper */
|
||||
// struct fb_pixmap sprite; /* Cursor hardware mapper */
|
||||
// struct fb_cmap cmap; /* Current cmap */
|
||||
struct list_head modelist; /* mode list */
|
||||
|
||||
@@ -0,0 +1,83 @@
|
||||
/*
|
||||
* fence-array: aggregates fence to be waited together
|
||||
*
|
||||
* Copyright (C) 2016 Collabora Ltd
|
||||
* Copyright (C) 2016 Advanced Micro Devices, Inc.
|
||||
* Authors:
|
||||
* Gustavo Padovan <gustavo@padovan.org>
|
||||
* Christian König <christian.koenig@amd.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published by
|
||||
* the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_FENCE_ARRAY_H
|
||||
#define __LINUX_FENCE_ARRAY_H
|
||||
|
||||
#include <linux/fence.h>
|
||||
|
||||
/**
|
||||
* struct fence_array_cb - callback helper for fence array
|
||||
* @cb: fence callback structure for signaling
|
||||
* @array: reference to the parent fence array object
|
||||
*/
|
||||
struct fence_array_cb {
|
||||
struct fence_cb cb;
|
||||
struct fence_array *array;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct fence_array - fence to represent an array of fences
|
||||
* @base: fence base class
|
||||
* @lock: spinlock for fence handling
|
||||
* @num_fences: number of fences in the array
|
||||
* @num_pending: fences in the array still pending
|
||||
* @fences: array of the fences
|
||||
*/
|
||||
struct fence_array {
|
||||
struct fence base;
|
||||
|
||||
spinlock_t lock;
|
||||
unsigned num_fences;
|
||||
atomic_t num_pending;
|
||||
struct fence **fences;
|
||||
};
|
||||
|
||||
extern const struct fence_ops fence_array_ops;
|
||||
|
||||
/**
|
||||
* fence_is_array - check if a fence is from the array subsclass
|
||||
*
|
||||
* Return true if it is a fence_array and false otherwise.
|
||||
*/
|
||||
static inline bool fence_is_array(struct fence *fence)
|
||||
{
|
||||
return fence->ops == &fence_array_ops;
|
||||
}
|
||||
|
||||
/**
|
||||
* to_fence_array - cast a fence to a fence_array
|
||||
* @fence: fence to cast to a fence_array
|
||||
*
|
||||
* Returns NULL if the fence is not a fence_array,
|
||||
* or the fence_array otherwise.
|
||||
*/
|
||||
static inline struct fence_array *to_fence_array(struct fence *fence)
|
||||
{
|
||||
if (fence->ops != &fence_array_ops)
|
||||
return NULL;
|
||||
|
||||
return container_of(fence, struct fence_array, base);
|
||||
}
|
||||
|
||||
struct fence_array *fence_array_create(int num_fences, struct fence **fences,
|
||||
u64 context, unsigned seqno,
|
||||
bool signal_on_any);
|
||||
|
||||
#endif /* __LINUX_FENCE_ARRAY_H */
|
||||
@@ -0,0 +1,35 @@
|
||||
#ifndef _LINUX_HRTIMER_H
|
||||
#define _LINUX_HRTIMER_H
|
||||
/*
|
||||
* amdgpu_mode.h only embeds a struct hrtimer in the virtual-DCE crtc and never
|
||||
* arms it on this port, so a structural stub is enough.
|
||||
*/
|
||||
#include <linux/types.h>
|
||||
#include <linux/ktime.h>
|
||||
|
||||
enum hrtimer_restart { HRTIMER_NORESTART, HRTIMER_RESTART };
|
||||
enum hrtimer_mode {
|
||||
HRTIMER_MODE_ABS = 0x0,
|
||||
HRTIMER_MODE_REL = 0x1,
|
||||
HRTIMER_MODE_PINNED = 0x2,
|
||||
};
|
||||
enum hrtimer_base_type { HRTIMER_BASE_MONOTONIC, HRTIMER_MAX_CLOCK_BASES };
|
||||
|
||||
struct hrtimer {
|
||||
ktime_t _softexpires;
|
||||
enum hrtimer_restart (*function)(struct hrtimer *);
|
||||
int state;
|
||||
};
|
||||
|
||||
static inline void hrtimer_init(struct hrtimer *timer, int which, enum hrtimer_mode mode)
|
||||
{ timer->function = NULL; timer->state = 0; }
|
||||
static inline int hrtimer_start(struct hrtimer *t, ktime_t tim, enum hrtimer_mode m) { return 0; }
|
||||
static inline int hrtimer_cancel(struct hrtimer *t) { return 0; }
|
||||
static inline int hrtimer_try_to_cancel(struct hrtimer *t) { return 0; }
|
||||
static inline bool hrtimer_active(const struct hrtimer *t) { return false; }
|
||||
static inline void hrtimer_start_range_ns(struct hrtimer *t, ktime_t tim,
|
||||
u64 range_ns, enum hrtimer_mode m) { }
|
||||
|
||||
/* Sleeps through the DDK's delay(); see the driver's kos_* glue. */
|
||||
extern int schedule_hrtimeout(ktime_t *expires, const enum hrtimer_mode mode);
|
||||
#endif
|
||||
@@ -0,0 +1,27 @@
|
||||
#ifndef _LINUX_HWMON_SYSFS_H
|
||||
#define _LINUX_HWMON_SYSFS_H
|
||||
/* sysfs is absent; amdgpu_pm.c's hwmon attributes are compiled out to stubs. */
|
||||
#include <linux/device.h>
|
||||
|
||||
struct sensor_device_attribute {
|
||||
struct device_attribute dev_attr;
|
||||
int index;
|
||||
};
|
||||
#define to_sensor_dev_attr(_dev_attr) \
|
||||
container_of(_dev_attr, struct sensor_device_attribute, dev_attr)
|
||||
|
||||
#define SENSOR_ATTR(_name, _mode, _show, _store, _index) \
|
||||
{ .dev_attr = __ATTR(_name, _mode, _show, _store), .index = _index }
|
||||
|
||||
#define SENSOR_DEVICE_ATTR(_name, _mode, _show, _store, _index) \
|
||||
struct sensor_device_attribute sensor_dev_attr_##_name = \
|
||||
SENSOR_ATTR(_name, _mode, _show, _store, _index)
|
||||
|
||||
struct sensor_device_attribute_2 {
|
||||
struct device_attribute dev_attr;
|
||||
u8 index;
|
||||
u8 nr;
|
||||
};
|
||||
#define to_sensor_dev_attr_2(_dev_attr) \
|
||||
container_of(_dev_attr, struct sensor_device_attribute_2, dev_attr)
|
||||
#endif
|
||||
@@ -52,6 +52,19 @@ struct i2c_board_info;
|
||||
extern int i2c_transfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
|
||||
int num);
|
||||
|
||||
/*
|
||||
* Declared here rather than left implicit: i2c-core.c defines them, and
|
||||
* nouveau reaches all three - i2c_new_device()/i2c_unregister_device() from
|
||||
* nvkm/subdev/therm/ic.c, i2c_register_driver() through the i2c_add_driver()
|
||||
* inline below.
|
||||
*/
|
||||
struct module;
|
||||
extern int i2c_register_driver(struct module *owner, struct i2c_driver *driver);
|
||||
extern void i2c_del_driver(struct i2c_driver *driver);
|
||||
extern struct i2c_client *i2c_new_device(struct i2c_adapter *adap,
|
||||
struct i2c_board_info const *info);
|
||||
extern void i2c_unregister_device(struct i2c_client *client);
|
||||
|
||||
/**
|
||||
* struct i2c_driver - represent an I2C device driver
|
||||
* @class: What kind of i2c device we instantiate (for detect)
|
||||
@@ -114,11 +127,18 @@ struct i2c_driver {
|
||||
*/
|
||||
int (*command)(struct i2c_client *client, unsigned int cmd, void *arg);
|
||||
|
||||
// struct device_driver driver;
|
||||
/*
|
||||
* Restored for nouveau: nvkm/subdev/therm/ic.c reaches the bound
|
||||
* driver through to_i2c_driver(client->dev.driver)->detect(). There
|
||||
* is no driver-model binding on this port, so dev.driver is always
|
||||
* NULL and the probe short-circuits - but the fields have to exist
|
||||
* for to_i2c_driver() to compile.
|
||||
*/
|
||||
struct device_driver driver;
|
||||
const struct i2c_device_id *id_table;
|
||||
|
||||
/* Device detection callback for automatic device creation */
|
||||
// int (*detect)(struct i2c_client *, struct i2c_board_info *);
|
||||
int (*detect)(struct i2c_client *, struct i2c_board_info *);
|
||||
const unsigned short *address_list;
|
||||
struct list_head clients;
|
||||
};
|
||||
|
||||
@@ -5,6 +5,18 @@
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/irqreturn.h>
|
||||
|
||||
/*
|
||||
* Taking an interrupt outside drm_irq_install(). nouveau's nvkm_pci_init()
|
||||
* does exactly that, so the driver supplies request_irq()/free_irq() over
|
||||
* AttachIntHandler(); the signatures are upstream's.
|
||||
*/
|
||||
typedef irqreturn_t (*irq_handler_t)(int irq, void *dev_id);
|
||||
|
||||
extern int request_irq(unsigned int irq, irq_handler_t handler,
|
||||
unsigned long flags, const char *name, void *dev_id);
|
||||
extern void free_irq(unsigned int irq, void *dev_id);
|
||||
|
||||
#include <linux/kref.h>
|
||||
#include <linux/atomic.h>
|
||||
/*
|
||||
|
||||
@@ -0,0 +1,37 @@
|
||||
#ifndef _LINUX_IOMMU_H
|
||||
#define _LINUX_IOMMU_H
|
||||
/*
|
||||
* No IOMMU on this port. nvif/os.h includes it unconditionally; the only user
|
||||
* is the Tegra SMMU path in nvkm/engine/device/tegra.c, which is not built.
|
||||
*/
|
||||
#include <linux/errno.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#define IOMMU_READ (1 << 0)
|
||||
#define IOMMU_WRITE (1 << 1)
|
||||
#define IOMMU_CACHE (1 << 2)
|
||||
|
||||
struct device;
|
||||
struct iommu_domain;
|
||||
struct iommu_group;
|
||||
|
||||
struct iommu_domain_geometry {
|
||||
dma_addr_t aperture_start;
|
||||
dma_addr_t aperture_end;
|
||||
bool force_aperture;
|
||||
};
|
||||
|
||||
static inline struct iommu_domain *iommu_domain_alloc(void *bus) { return NULL; }
|
||||
static inline void iommu_domain_free(struct iommu_domain *d) { }
|
||||
static inline int iommu_attach_device(struct iommu_domain *d, struct device *dev)
|
||||
{ return -ENODEV; }
|
||||
static inline void iommu_detach_device(struct iommu_domain *d, struct device *dev) { }
|
||||
static inline struct iommu_group *iommu_group_get(struct device *dev) { return NULL; }
|
||||
static inline int iommu_map(struct iommu_domain *domain, unsigned long iova,
|
||||
phys_addr_t paddr, size_t size, int prot)
|
||||
{ return -ENODEV; }
|
||||
static inline size_t iommu_unmap(struct iommu_domain *domain, unsigned long iova,
|
||||
size_t size)
|
||||
{ return 0; }
|
||||
static inline void iommu_group_put(struct iommu_group *g) { }
|
||||
#endif
|
||||
@@ -0,0 +1,27 @@
|
||||
#ifndef _LINUX_IRQ_H
|
||||
#define _LINUX_IRQ_H
|
||||
/*
|
||||
* KolibriOS has no irq_domain layer. amdgpu_irq.c is patched to dispatch IH
|
||||
* ring entries straight to the registered amdgpu_irq_src, so only the types it
|
||||
* still mentions need to exist.
|
||||
*/
|
||||
#include <linux/types.h>
|
||||
|
||||
struct irq_data {
|
||||
unsigned int irq;
|
||||
unsigned long hwirq;
|
||||
void *chip_data;
|
||||
};
|
||||
|
||||
struct irq_chip {
|
||||
const char *name;
|
||||
void (*irq_mask)(struct irq_data *data);
|
||||
void (*irq_unmask)(struct irq_data *data);
|
||||
};
|
||||
|
||||
static inline void *irq_data_get_irq_chip_data(struct irq_data *d)
|
||||
{
|
||||
return d ? d->chip_data : NULL;
|
||||
}
|
||||
static inline void handle_simple_irq(void) { }
|
||||
#endif
|
||||
@@ -0,0 +1,41 @@
|
||||
#ifndef _LINUX_IRQDOMAIN_H
|
||||
#define _LINUX_IRQDOMAIN_H
|
||||
/*
|
||||
* KolibriOS has no irq domain layer.
|
||||
*
|
||||
* amdgpu builds a linear domain purely so that a *different* driver (the ACP
|
||||
* audio co-processor) can receive GPU interrupts by Linux irq number. ACP is
|
||||
* not part of this port, so no mapping is ever created: adev->irq.virq[] stays
|
||||
* zero and amdgpu_irq_dispatch() always takes its direct-call branch.
|
||||
*
|
||||
* These declarations therefore exist to keep the domain setup compiling and
|
||||
* succeeding; the implementations in the driver's kos_stubs.c do nothing.
|
||||
*/
|
||||
#include <linux/types.h>
|
||||
#include <linux/irq.h>
|
||||
|
||||
typedef unsigned long irq_hw_number_t;
|
||||
|
||||
struct irq_domain;
|
||||
struct device_node;
|
||||
|
||||
struct irq_domain_ops {
|
||||
int (*map)(struct irq_domain *d, unsigned int virq, irq_hw_number_t hw);
|
||||
void (*unmap)(struct irq_domain *d, unsigned int virq);
|
||||
int (*xlate)(struct irq_domain *d, struct device_node *node,
|
||||
const u32 *intspec, unsigned int intsize,
|
||||
unsigned long *out_hwirq, unsigned int *out_type);
|
||||
};
|
||||
|
||||
struct irq_domain *irq_domain_add_linear(struct device_node *of_node,
|
||||
unsigned int size,
|
||||
const struct irq_domain_ops *ops,
|
||||
void *host_data);
|
||||
void irq_domain_remove(struct irq_domain *domain);
|
||||
unsigned int irq_create_mapping(struct irq_domain *domain, irq_hw_number_t hwirq);
|
||||
unsigned int irq_find_mapping(struct irq_domain *domain, irq_hw_number_t hwirq);
|
||||
int generic_handle_irq(unsigned int irq);
|
||||
void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip,
|
||||
void (*handle)(void));
|
||||
|
||||
#endif /* _LINUX_IRQDOMAIN_H */
|
||||
@@ -684,7 +684,20 @@ typedef union
|
||||
u64 raw;
|
||||
}evhandle_t;
|
||||
|
||||
struct vm_area_struct {};
|
||||
/*
|
||||
* KolibriOS has no user address space that drivers can map into, so these are
|
||||
* placeholders. The fields exist because the mmap/userptr entry points of the
|
||||
* ported DRM drivers reference them; those paths are never reached, since no
|
||||
* ioctl surface is exposed to user code.
|
||||
*/
|
||||
struct vm_area_struct {
|
||||
unsigned long vm_start;
|
||||
unsigned long vm_end;
|
||||
unsigned long vm_pgoff;
|
||||
unsigned long vm_flags;
|
||||
struct file *vm_file;
|
||||
void *vm_private_data;
|
||||
};
|
||||
struct address_space {};
|
||||
|
||||
#define in_dbg_master() (0)
|
||||
@@ -731,6 +744,13 @@ int del_timer(struct timer_list *timer);
|
||||
|
||||
#define mmiowb() barrier()
|
||||
|
||||
/* String-to-integer conversions; each driver's kos_kernel.c implements them. */
|
||||
extern int kstrtol(const char *s, unsigned int base, long *res);
|
||||
extern int kstrtoul(const char *s, unsigned int base, unsigned long *res);
|
||||
extern int kstrtoint(const char *s, unsigned int base, int *res);
|
||||
extern int kstrtou32(const char *s, unsigned int base, u32 *res);
|
||||
|
||||
|
||||
#define dev_err(dev, format, arg...) \
|
||||
printk("Error %s " format, __func__ , ## arg)
|
||||
|
||||
@@ -740,6 +760,18 @@ int del_timer(struct timer_list *timer);
|
||||
#define dev_info(dev, format, arg...) \
|
||||
printk("Info %s " format , __func__, ## arg)
|
||||
|
||||
/*
|
||||
* nouveau routes all of its logging through dev_*() (NV_PRINTK in
|
||||
* nouveau_drv.h picks the level by name), so the two levels the other drivers
|
||||
* never needed have to exist as well. dev_dbg() keeps its arguments checked
|
||||
* but emits nothing, matching the !CONFIG_DYNAMIC_DEBUG behaviour upstream.
|
||||
*/
|
||||
#define dev_crit(dev, format, arg...) \
|
||||
printk("Critical %s " format, __func__ , ## arg)
|
||||
|
||||
#define dev_dbg(dev, format, arg...) \
|
||||
do { if (0) printk(format, ## arg); } while (0)
|
||||
|
||||
struct page
|
||||
{
|
||||
unsigned int addr;
|
||||
|
||||
@@ -0,0 +1,833 @@
|
||||
/*
|
||||
* A generic kernel FIFO implementation
|
||||
*
|
||||
* Copyright (C) 2013 Stefani Seibold <stefani@seibold.net>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _LINUX_KFIFO_H
|
||||
#define _LINUX_KFIFO_H
|
||||
|
||||
/*
|
||||
* How to porting drivers to the new generic FIFO API:
|
||||
*
|
||||
* - Modify the declaration of the "struct kfifo *" object into a
|
||||
* in-place "struct kfifo" object
|
||||
* - Init the in-place object with kfifo_alloc() or kfifo_init()
|
||||
* Note: The address of the in-place "struct kfifo" object must be
|
||||
* passed as the first argument to this functions
|
||||
* - Replace the use of __kfifo_put into kfifo_in and __kfifo_get
|
||||
* into kfifo_out
|
||||
* - Replace the use of kfifo_put into kfifo_in_spinlocked and kfifo_get
|
||||
* into kfifo_out_spinlocked
|
||||
* Note: the spinlock pointer formerly passed to kfifo_init/kfifo_alloc
|
||||
* must be passed now to the kfifo_in_spinlocked and kfifo_out_spinlocked
|
||||
* as the last parameter
|
||||
* - The formerly __kfifo_* functions are renamed into kfifo_*
|
||||
*/
|
||||
|
||||
/*
|
||||
* Note about locking : There is no locking required until only * one reader
|
||||
* and one writer is using the fifo and no kfifo_reset() will be * called
|
||||
* kfifo_reset_out() can be safely used, until it will be only called
|
||||
* in the reader thread.
|
||||
* For multiple writer and one reader there is only a need to lock the writer.
|
||||
* And vice versa for only one writer and multiple reader there is only a need
|
||||
* to lock the reader.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/stddef.h>
|
||||
#include <linux/scatterlist.h>
|
||||
|
||||
struct __kfifo {
|
||||
unsigned int in;
|
||||
unsigned int out;
|
||||
unsigned int mask;
|
||||
unsigned int esize;
|
||||
void *data;
|
||||
};
|
||||
|
||||
#define __STRUCT_KFIFO_COMMON(datatype, recsize, ptrtype) \
|
||||
union { \
|
||||
struct __kfifo kfifo; \
|
||||
datatype *type; \
|
||||
const datatype *const_type; \
|
||||
char (*rectype)[recsize]; \
|
||||
ptrtype *ptr; \
|
||||
ptrtype const *ptr_const; \
|
||||
}
|
||||
|
||||
#define __STRUCT_KFIFO(type, size, recsize, ptrtype) \
|
||||
{ \
|
||||
__STRUCT_KFIFO_COMMON(type, recsize, ptrtype); \
|
||||
type buf[((size < 2) || (size & (size - 1))) ? -1 : size]; \
|
||||
}
|
||||
|
||||
#define STRUCT_KFIFO(type, size) \
|
||||
struct __STRUCT_KFIFO(type, size, 0, type)
|
||||
|
||||
#define __STRUCT_KFIFO_PTR(type, recsize, ptrtype) \
|
||||
{ \
|
||||
__STRUCT_KFIFO_COMMON(type, recsize, ptrtype); \
|
||||
type buf[0]; \
|
||||
}
|
||||
|
||||
#define STRUCT_KFIFO_PTR(type) \
|
||||
struct __STRUCT_KFIFO_PTR(type, 0, type)
|
||||
|
||||
/*
|
||||
* define compatibility "struct kfifo" for dynamic allocated fifos
|
||||
*/
|
||||
struct kfifo __STRUCT_KFIFO_PTR(unsigned char, 0, void);
|
||||
|
||||
#define STRUCT_KFIFO_REC_1(size) \
|
||||
struct __STRUCT_KFIFO(unsigned char, size, 1, void)
|
||||
|
||||
#define STRUCT_KFIFO_REC_2(size) \
|
||||
struct __STRUCT_KFIFO(unsigned char, size, 2, void)
|
||||
|
||||
/*
|
||||
* define kfifo_rec types
|
||||
*/
|
||||
struct kfifo_rec_ptr_1 __STRUCT_KFIFO_PTR(unsigned char, 1, void);
|
||||
struct kfifo_rec_ptr_2 __STRUCT_KFIFO_PTR(unsigned char, 2, void);
|
||||
|
||||
/*
|
||||
* helper macro to distinguish between real in place fifo where the fifo
|
||||
* array is a part of the structure and the fifo type where the array is
|
||||
* outside of the fifo structure.
|
||||
*/
|
||||
#define __is_kfifo_ptr(fifo) (sizeof(*fifo) == sizeof(struct __kfifo))
|
||||
|
||||
/**
|
||||
* DECLARE_KFIFO_PTR - macro to declare a fifo pointer object
|
||||
* @fifo: name of the declared fifo
|
||||
* @type: type of the fifo elements
|
||||
*/
|
||||
#define DECLARE_KFIFO_PTR(fifo, type) STRUCT_KFIFO_PTR(type) fifo
|
||||
|
||||
/**
|
||||
* DECLARE_KFIFO - macro to declare a fifo object
|
||||
* @fifo: name of the declared fifo
|
||||
* @type: type of the fifo elements
|
||||
* @size: the number of elements in the fifo, this must be a power of 2
|
||||
*/
|
||||
#define DECLARE_KFIFO(fifo, type, size) STRUCT_KFIFO(type, size) fifo
|
||||
|
||||
/**
|
||||
* INIT_KFIFO - Initialize a fifo declared by DECLARE_KFIFO
|
||||
* @fifo: name of the declared fifo datatype
|
||||
*/
|
||||
#define INIT_KFIFO(fifo) \
|
||||
(void)({ \
|
||||
typeof(&(fifo)) __tmp = &(fifo); \
|
||||
struct __kfifo *__kfifo = &__tmp->kfifo; \
|
||||
__kfifo->in = 0; \
|
||||
__kfifo->out = 0; \
|
||||
__kfifo->mask = __is_kfifo_ptr(__tmp) ? 0 : ARRAY_SIZE(__tmp->buf) - 1;\
|
||||
__kfifo->esize = sizeof(*__tmp->buf); \
|
||||
__kfifo->data = __is_kfifo_ptr(__tmp) ? NULL : __tmp->buf; \
|
||||
})
|
||||
|
||||
/**
|
||||
* DEFINE_KFIFO - macro to define and initialize a fifo
|
||||
* @fifo: name of the declared fifo datatype
|
||||
* @type: type of the fifo elements
|
||||
* @size: the number of elements in the fifo, this must be a power of 2
|
||||
*
|
||||
* Note: the macro can be used for global and local fifo data type variables.
|
||||
*/
|
||||
#define DEFINE_KFIFO(fifo, type, size) \
|
||||
DECLARE_KFIFO(fifo, type, size) = \
|
||||
(typeof(fifo)) { \
|
||||
{ \
|
||||
{ \
|
||||
.in = 0, \
|
||||
.out = 0, \
|
||||
.mask = __is_kfifo_ptr(&(fifo)) ? \
|
||||
0 : \
|
||||
ARRAY_SIZE((fifo).buf) - 1, \
|
||||
.esize = sizeof(*(fifo).buf), \
|
||||
.data = __is_kfifo_ptr(&(fifo)) ? \
|
||||
NULL : \
|
||||
(fifo).buf, \
|
||||
} \
|
||||
} \
|
||||
}
|
||||
|
||||
|
||||
static inline unsigned int __must_check
|
||||
__kfifo_uint_must_check_helper(unsigned int val)
|
||||
{
|
||||
return val;
|
||||
}
|
||||
|
||||
static inline int __must_check
|
||||
__kfifo_int_must_check_helper(int val)
|
||||
{
|
||||
return val;
|
||||
}
|
||||
|
||||
/**
|
||||
* kfifo_initialized - Check if the fifo is initialized
|
||||
* @fifo: address of the fifo to check
|
||||
*
|
||||
* Return %true if fifo is initialized, otherwise %false.
|
||||
* Assumes the fifo was 0 before.
|
||||
*/
|
||||
#define kfifo_initialized(fifo) ((fifo)->kfifo.mask)
|
||||
|
||||
/**
|
||||
* kfifo_esize - returns the size of the element managed by the fifo
|
||||
* @fifo: address of the fifo to be used
|
||||
*/
|
||||
#define kfifo_esize(fifo) ((fifo)->kfifo.esize)
|
||||
|
||||
/**
|
||||
* kfifo_recsize - returns the size of the record length field
|
||||
* @fifo: address of the fifo to be used
|
||||
*/
|
||||
#define kfifo_recsize(fifo) (sizeof(*(fifo)->rectype))
|
||||
|
||||
/**
|
||||
* kfifo_size - returns the size of the fifo in elements
|
||||
* @fifo: address of the fifo to be used
|
||||
*/
|
||||
#define kfifo_size(fifo) ((fifo)->kfifo.mask + 1)
|
||||
|
||||
/**
|
||||
* kfifo_reset - removes the entire fifo content
|
||||
* @fifo: address of the fifo to be used
|
||||
*
|
||||
* Note: usage of kfifo_reset() is dangerous. It should be only called when the
|
||||
* fifo is exclusived locked or when it is secured that no other thread is
|
||||
* accessing the fifo.
|
||||
*/
|
||||
#define kfifo_reset(fifo) \
|
||||
(void)({ \
|
||||
typeof((fifo) + 1) __tmp = (fifo); \
|
||||
__tmp->kfifo.in = __tmp->kfifo.out = 0; \
|
||||
})
|
||||
|
||||
/**
|
||||
* kfifo_reset_out - skip fifo content
|
||||
* @fifo: address of the fifo to be used
|
||||
*
|
||||
* Note: The usage of kfifo_reset_out() is safe until it will be only called
|
||||
* from the reader thread and there is only one concurrent reader. Otherwise
|
||||
* it is dangerous and must be handled in the same way as kfifo_reset().
|
||||
*/
|
||||
#define kfifo_reset_out(fifo) \
|
||||
(void)({ \
|
||||
typeof((fifo) + 1) __tmp = (fifo); \
|
||||
__tmp->kfifo.out = __tmp->kfifo.in; \
|
||||
})
|
||||
|
||||
/**
|
||||
* kfifo_len - returns the number of used elements in the fifo
|
||||
* @fifo: address of the fifo to be used
|
||||
*/
|
||||
#define kfifo_len(fifo) \
|
||||
({ \
|
||||
typeof((fifo) + 1) __tmpl = (fifo); \
|
||||
__tmpl->kfifo.in - __tmpl->kfifo.out; \
|
||||
})
|
||||
|
||||
/**
|
||||
* kfifo_is_empty - returns true if the fifo is empty
|
||||
* @fifo: address of the fifo to be used
|
||||
*/
|
||||
#define kfifo_is_empty(fifo) \
|
||||
({ \
|
||||
typeof((fifo) + 1) __tmpq = (fifo); \
|
||||
__tmpq->kfifo.in == __tmpq->kfifo.out; \
|
||||
})
|
||||
|
||||
/**
|
||||
* kfifo_is_full - returns true if the fifo is full
|
||||
* @fifo: address of the fifo to be used
|
||||
*/
|
||||
#define kfifo_is_full(fifo) \
|
||||
({ \
|
||||
typeof((fifo) + 1) __tmpq = (fifo); \
|
||||
kfifo_len(__tmpq) > __tmpq->kfifo.mask; \
|
||||
})
|
||||
|
||||
/**
|
||||
* kfifo_avail - returns the number of unused elements in the fifo
|
||||
* @fifo: address of the fifo to be used
|
||||
*/
|
||||
#define kfifo_avail(fifo) \
|
||||
__kfifo_uint_must_check_helper( \
|
||||
({ \
|
||||
typeof((fifo) + 1) __tmpq = (fifo); \
|
||||
const size_t __recsize = sizeof(*__tmpq->rectype); \
|
||||
unsigned int __avail = kfifo_size(__tmpq) - kfifo_len(__tmpq); \
|
||||
(__recsize) ? ((__avail <= __recsize) ? 0 : \
|
||||
__kfifo_max_r(__avail - __recsize, __recsize)) : \
|
||||
__avail; \
|
||||
}) \
|
||||
)
|
||||
|
||||
/**
|
||||
* kfifo_skip - skip output data
|
||||
* @fifo: address of the fifo to be used
|
||||
*/
|
||||
#define kfifo_skip(fifo) \
|
||||
(void)({ \
|
||||
typeof((fifo) + 1) __tmp = (fifo); \
|
||||
const size_t __recsize = sizeof(*__tmp->rectype); \
|
||||
struct __kfifo *__kfifo = &__tmp->kfifo; \
|
||||
if (__recsize) \
|
||||
__kfifo_skip_r(__kfifo, __recsize); \
|
||||
else \
|
||||
__kfifo->out++; \
|
||||
})
|
||||
|
||||
/**
|
||||
* kfifo_peek_len - gets the size of the next fifo record
|
||||
* @fifo: address of the fifo to be used
|
||||
*
|
||||
* This function returns the size of the next fifo record in number of bytes.
|
||||
*/
|
||||
#define kfifo_peek_len(fifo) \
|
||||
__kfifo_uint_must_check_helper( \
|
||||
({ \
|
||||
typeof((fifo) + 1) __tmp = (fifo); \
|
||||
const size_t __recsize = sizeof(*__tmp->rectype); \
|
||||
struct __kfifo *__kfifo = &__tmp->kfifo; \
|
||||
(!__recsize) ? kfifo_len(__tmp) * sizeof(*__tmp->type) : \
|
||||
__kfifo_len_r(__kfifo, __recsize); \
|
||||
}) \
|
||||
)
|
||||
|
||||
/**
|
||||
* kfifo_alloc - dynamically allocates a new fifo buffer
|
||||
* @fifo: pointer to the fifo
|
||||
* @size: the number of elements in the fifo, this must be a power of 2
|
||||
* @gfp_mask: get_free_pages mask, passed to kmalloc()
|
||||
*
|
||||
* This macro dynamically allocates a new fifo buffer.
|
||||
*
|
||||
* The numer of elements will be rounded-up to a power of 2.
|
||||
* The fifo will be release with kfifo_free().
|
||||
* Return 0 if no error, otherwise an error code.
|
||||
*/
|
||||
#define kfifo_alloc(fifo, size, gfp_mask) \
|
||||
__kfifo_int_must_check_helper( \
|
||||
({ \
|
||||
typeof((fifo) + 1) __tmp = (fifo); \
|
||||
struct __kfifo *__kfifo = &__tmp->kfifo; \
|
||||
__is_kfifo_ptr(__tmp) ? \
|
||||
__kfifo_alloc(__kfifo, size, sizeof(*__tmp->type), gfp_mask) : \
|
||||
-EINVAL; \
|
||||
}) \
|
||||
)
|
||||
|
||||
/**
|
||||
* kfifo_free - frees the fifo
|
||||
* @fifo: the fifo to be freed
|
||||
*/
|
||||
#define kfifo_free(fifo) \
|
||||
({ \
|
||||
typeof((fifo) + 1) __tmp = (fifo); \
|
||||
struct __kfifo *__kfifo = &__tmp->kfifo; \
|
||||
if (__is_kfifo_ptr(__tmp)) \
|
||||
__kfifo_free(__kfifo); \
|
||||
})
|
||||
|
||||
/**
|
||||
* kfifo_init - initialize a fifo using a preallocated buffer
|
||||
* @fifo: the fifo to assign the buffer
|
||||
* @buffer: the preallocated buffer to be used
|
||||
* @size: the size of the internal buffer, this have to be a power of 2
|
||||
*
|
||||
* This macro initialize a fifo using a preallocated buffer.
|
||||
*
|
||||
* The numer of elements will be rounded-up to a power of 2.
|
||||
* Return 0 if no error, otherwise an error code.
|
||||
*/
|
||||
#define kfifo_init(fifo, buffer, size) \
|
||||
({ \
|
||||
typeof((fifo) + 1) __tmp = (fifo); \
|
||||
struct __kfifo *__kfifo = &__tmp->kfifo; \
|
||||
__is_kfifo_ptr(__tmp) ? \
|
||||
__kfifo_init(__kfifo, buffer, size, sizeof(*__tmp->type)) : \
|
||||
-EINVAL; \
|
||||
})
|
||||
|
||||
/**
|
||||
* kfifo_put - put data into the fifo
|
||||
* @fifo: address of the fifo to be used
|
||||
* @val: the data to be added
|
||||
*
|
||||
* This macro copies the given value into the fifo.
|
||||
* It returns 0 if the fifo was full. Otherwise it returns the number
|
||||
* processed elements.
|
||||
*
|
||||
* Note that with only one concurrent reader and one concurrent
|
||||
* writer, you don't need extra locking to use these macro.
|
||||
*/
|
||||
#define kfifo_put(fifo, val) \
|
||||
({ \
|
||||
typeof((fifo) + 1) __tmp = (fifo); \
|
||||
typeof(*__tmp->const_type) __val = (val); \
|
||||
unsigned int __ret; \
|
||||
size_t __recsize = sizeof(*__tmp->rectype); \
|
||||
struct __kfifo *__kfifo = &__tmp->kfifo; \
|
||||
if (__recsize) \
|
||||
__ret = __kfifo_in_r(__kfifo, &__val, sizeof(__val), \
|
||||
__recsize); \
|
||||
else { \
|
||||
__ret = !kfifo_is_full(__tmp); \
|
||||
if (__ret) { \
|
||||
(__is_kfifo_ptr(__tmp) ? \
|
||||
((typeof(__tmp->type))__kfifo->data) : \
|
||||
(__tmp->buf) \
|
||||
)[__kfifo->in & __tmp->kfifo.mask] = \
|
||||
*(typeof(__tmp->type))&__val; \
|
||||
smp_wmb(); \
|
||||
__kfifo->in++; \
|
||||
} \
|
||||
} \
|
||||
__ret; \
|
||||
})
|
||||
|
||||
/**
|
||||
* kfifo_get - get data from the fifo
|
||||
* @fifo: address of the fifo to be used
|
||||
* @val: address where to store the data
|
||||
*
|
||||
* This macro reads the data from the fifo.
|
||||
* It returns 0 if the fifo was empty. Otherwise it returns the number
|
||||
* processed elements.
|
||||
*
|
||||
* Note that with only one concurrent reader and one concurrent
|
||||
* writer, you don't need extra locking to use these macro.
|
||||
*/
|
||||
#define kfifo_get(fifo, val) \
|
||||
__kfifo_uint_must_check_helper( \
|
||||
({ \
|
||||
typeof((fifo) + 1) __tmp = (fifo); \
|
||||
typeof(__tmp->ptr) __val = (val); \
|
||||
unsigned int __ret; \
|
||||
const size_t __recsize = sizeof(*__tmp->rectype); \
|
||||
struct __kfifo *__kfifo = &__tmp->kfifo; \
|
||||
if (__recsize) \
|
||||
__ret = __kfifo_out_r(__kfifo, __val, sizeof(*__val), \
|
||||
__recsize); \
|
||||
else { \
|
||||
__ret = !kfifo_is_empty(__tmp); \
|
||||
if (__ret) { \
|
||||
*(typeof(__tmp->type))__val = \
|
||||
(__is_kfifo_ptr(__tmp) ? \
|
||||
((typeof(__tmp->type))__kfifo->data) : \
|
||||
(__tmp->buf) \
|
||||
)[__kfifo->out & __tmp->kfifo.mask]; \
|
||||
smp_wmb(); \
|
||||
__kfifo->out++; \
|
||||
} \
|
||||
} \
|
||||
__ret; \
|
||||
}) \
|
||||
)
|
||||
|
||||
/**
|
||||
* kfifo_peek - get data from the fifo without removing
|
||||
* @fifo: address of the fifo to be used
|
||||
* @val: address where to store the data
|
||||
*
|
||||
* This reads the data from the fifo without removing it from the fifo.
|
||||
* It returns 0 if the fifo was empty. Otherwise it returns the number
|
||||
* processed elements.
|
||||
*
|
||||
* Note that with only one concurrent reader and one concurrent
|
||||
* writer, you don't need extra locking to use these macro.
|
||||
*/
|
||||
#define kfifo_peek(fifo, val) \
|
||||
__kfifo_uint_must_check_helper( \
|
||||
({ \
|
||||
typeof((fifo) + 1) __tmp = (fifo); \
|
||||
typeof(__tmp->ptr) __val = (val); \
|
||||
unsigned int __ret; \
|
||||
const size_t __recsize = sizeof(*__tmp->rectype); \
|
||||
struct __kfifo *__kfifo = &__tmp->kfifo; \
|
||||
if (__recsize) \
|
||||
__ret = __kfifo_out_peek_r(__kfifo, __val, sizeof(*__val), \
|
||||
__recsize); \
|
||||
else { \
|
||||
__ret = !kfifo_is_empty(__tmp); \
|
||||
if (__ret) { \
|
||||
*(typeof(__tmp->type))__val = \
|
||||
(__is_kfifo_ptr(__tmp) ? \
|
||||
((typeof(__tmp->type))__kfifo->data) : \
|
||||
(__tmp->buf) \
|
||||
)[__kfifo->out & __tmp->kfifo.mask]; \
|
||||
smp_wmb(); \
|
||||
} \
|
||||
} \
|
||||
__ret; \
|
||||
}) \
|
||||
)
|
||||
|
||||
/**
|
||||
* kfifo_in - put data into the fifo
|
||||
* @fifo: address of the fifo to be used
|
||||
* @buf: the data to be added
|
||||
* @n: number of elements to be added
|
||||
*
|
||||
* This macro copies the given buffer into the fifo and returns the
|
||||
* number of copied elements.
|
||||
*
|
||||
* Note that with only one concurrent reader and one concurrent
|
||||
* writer, you don't need extra locking to use these macro.
|
||||
*/
|
||||
#define kfifo_in(fifo, buf, n) \
|
||||
({ \
|
||||
typeof((fifo) + 1) __tmp = (fifo); \
|
||||
typeof(__tmp->ptr_const) __buf = (buf); \
|
||||
unsigned long __n = (n); \
|
||||
const size_t __recsize = sizeof(*__tmp->rectype); \
|
||||
struct __kfifo *__kfifo = &__tmp->kfifo; \
|
||||
(__recsize) ?\
|
||||
__kfifo_in_r(__kfifo, __buf, __n, __recsize) : \
|
||||
__kfifo_in(__kfifo, __buf, __n); \
|
||||
})
|
||||
|
||||
/**
|
||||
* kfifo_in_spinlocked - put data into the fifo using a spinlock for locking
|
||||
* @fifo: address of the fifo to be used
|
||||
* @buf: the data to be added
|
||||
* @n: number of elements to be added
|
||||
* @lock: pointer to the spinlock to use for locking
|
||||
*
|
||||
* This macro copies the given values buffer into the fifo and returns the
|
||||
* number of copied elements.
|
||||
*/
|
||||
#define kfifo_in_spinlocked(fifo, buf, n, lock) \
|
||||
({ \
|
||||
unsigned long __flags; \
|
||||
unsigned int __ret; \
|
||||
spin_lock_irqsave(lock, __flags); \
|
||||
__ret = kfifo_in(fifo, buf, n); \
|
||||
spin_unlock_irqrestore(lock, __flags); \
|
||||
__ret; \
|
||||
})
|
||||
|
||||
/* alias for kfifo_in_spinlocked, will be removed in a future release */
|
||||
#define kfifo_in_locked(fifo, buf, n, lock) \
|
||||
kfifo_in_spinlocked(fifo, buf, n, lock)
|
||||
|
||||
/**
|
||||
* kfifo_out - get data from the fifo
|
||||
* @fifo: address of the fifo to be used
|
||||
* @buf: pointer to the storage buffer
|
||||
* @n: max. number of elements to get
|
||||
*
|
||||
* This macro get some data from the fifo and return the numbers of elements
|
||||
* copied.
|
||||
*
|
||||
* Note that with only one concurrent reader and one concurrent
|
||||
* writer, you don't need extra locking to use these macro.
|
||||
*/
|
||||
#define kfifo_out(fifo, buf, n) \
|
||||
__kfifo_uint_must_check_helper( \
|
||||
({ \
|
||||
typeof((fifo) + 1) __tmp = (fifo); \
|
||||
typeof(__tmp->ptr) __buf = (buf); \
|
||||
unsigned long __n = (n); \
|
||||
const size_t __recsize = sizeof(*__tmp->rectype); \
|
||||
struct __kfifo *__kfifo = &__tmp->kfifo; \
|
||||
(__recsize) ?\
|
||||
__kfifo_out_r(__kfifo, __buf, __n, __recsize) : \
|
||||
__kfifo_out(__kfifo, __buf, __n); \
|
||||
}) \
|
||||
)
|
||||
|
||||
/**
|
||||
* kfifo_out_spinlocked - get data from the fifo using a spinlock for locking
|
||||
* @fifo: address of the fifo to be used
|
||||
* @buf: pointer to the storage buffer
|
||||
* @n: max. number of elements to get
|
||||
* @lock: pointer to the spinlock to use for locking
|
||||
*
|
||||
* This macro get the data from the fifo and return the numbers of elements
|
||||
* copied.
|
||||
*/
|
||||
#define kfifo_out_spinlocked(fifo, buf, n, lock) \
|
||||
__kfifo_uint_must_check_helper( \
|
||||
({ \
|
||||
unsigned long __flags; \
|
||||
unsigned int __ret; \
|
||||
spin_lock_irqsave(lock, __flags); \
|
||||
__ret = kfifo_out(fifo, buf, n); \
|
||||
spin_unlock_irqrestore(lock, __flags); \
|
||||
__ret; \
|
||||
}) \
|
||||
)
|
||||
|
||||
/* alias for kfifo_out_spinlocked, will be removed in a future release */
|
||||
#define kfifo_out_locked(fifo, buf, n, lock) \
|
||||
kfifo_out_spinlocked(fifo, buf, n, lock)
|
||||
|
||||
/**
|
||||
* kfifo_from_user - puts some data from user space into the fifo
|
||||
* @fifo: address of the fifo to be used
|
||||
* @from: pointer to the data to be added
|
||||
* @len: the length of the data to be added
|
||||
* @copied: pointer to output variable to store the number of copied bytes
|
||||
*
|
||||
* This macro copies at most @len bytes from the @from into the
|
||||
* fifo, depending of the available space and returns -EFAULT/0.
|
||||
*
|
||||
* Note that with only one concurrent reader and one concurrent
|
||||
* writer, you don't need extra locking to use these macro.
|
||||
*/
|
||||
#define kfifo_from_user(fifo, from, len, copied) \
|
||||
__kfifo_uint_must_check_helper( \
|
||||
({ \
|
||||
typeof((fifo) + 1) __tmp = (fifo); \
|
||||
const void __user *__from = (from); \
|
||||
unsigned int __len = (len); \
|
||||
unsigned int *__copied = (copied); \
|
||||
const size_t __recsize = sizeof(*__tmp->rectype); \
|
||||
struct __kfifo *__kfifo = &__tmp->kfifo; \
|
||||
(__recsize) ? \
|
||||
__kfifo_from_user_r(__kfifo, __from, __len, __copied, __recsize) : \
|
||||
__kfifo_from_user(__kfifo, __from, __len, __copied); \
|
||||
}) \
|
||||
)
|
||||
|
||||
/**
|
||||
* kfifo_to_user - copies data from the fifo into user space
|
||||
* @fifo: address of the fifo to be used
|
||||
* @to: where the data must be copied
|
||||
* @len: the size of the destination buffer
|
||||
* @copied: pointer to output variable to store the number of copied bytes
|
||||
*
|
||||
* This macro copies at most @len bytes from the fifo into the
|
||||
* @to buffer and returns -EFAULT/0.
|
||||
*
|
||||
* Note that with only one concurrent reader and one concurrent
|
||||
* writer, you don't need extra locking to use these macro.
|
||||
*/
|
||||
#define kfifo_to_user(fifo, to, len, copied) \
|
||||
__kfifo_uint_must_check_helper( \
|
||||
({ \
|
||||
typeof((fifo) + 1) __tmp = (fifo); \
|
||||
void __user *__to = (to); \
|
||||
unsigned int __len = (len); \
|
||||
unsigned int *__copied = (copied); \
|
||||
const size_t __recsize = sizeof(*__tmp->rectype); \
|
||||
struct __kfifo *__kfifo = &__tmp->kfifo; \
|
||||
(__recsize) ? \
|
||||
__kfifo_to_user_r(__kfifo, __to, __len, __copied, __recsize) : \
|
||||
__kfifo_to_user(__kfifo, __to, __len, __copied); \
|
||||
}) \
|
||||
)
|
||||
|
||||
/**
|
||||
* kfifo_dma_in_prepare - setup a scatterlist for DMA input
|
||||
* @fifo: address of the fifo to be used
|
||||
* @sgl: pointer to the scatterlist array
|
||||
* @nents: number of entries in the scatterlist array
|
||||
* @len: number of elements to transfer
|
||||
*
|
||||
* This macro fills a scatterlist for DMA input.
|
||||
* It returns the number entries in the scatterlist array.
|
||||
*
|
||||
* Note that with only one concurrent reader and one concurrent
|
||||
* writer, you don't need extra locking to use these macros.
|
||||
*/
|
||||
#define kfifo_dma_in_prepare(fifo, sgl, nents, len) \
|
||||
({ \
|
||||
typeof((fifo) + 1) __tmp = (fifo); \
|
||||
struct scatterlist *__sgl = (sgl); \
|
||||
int __nents = (nents); \
|
||||
unsigned int __len = (len); \
|
||||
const size_t __recsize = sizeof(*__tmp->rectype); \
|
||||
struct __kfifo *__kfifo = &__tmp->kfifo; \
|
||||
(__recsize) ? \
|
||||
__kfifo_dma_in_prepare_r(__kfifo, __sgl, __nents, __len, __recsize) : \
|
||||
__kfifo_dma_in_prepare(__kfifo, __sgl, __nents, __len); \
|
||||
})
|
||||
|
||||
/**
|
||||
* kfifo_dma_in_finish - finish a DMA IN operation
|
||||
* @fifo: address of the fifo to be used
|
||||
* @len: number of bytes to received
|
||||
*
|
||||
* This macro finish a DMA IN operation. The in counter will be updated by
|
||||
* the len parameter. No error checking will be done.
|
||||
*
|
||||
* Note that with only one concurrent reader and one concurrent
|
||||
* writer, you don't need extra locking to use these macros.
|
||||
*/
|
||||
#define kfifo_dma_in_finish(fifo, len) \
|
||||
(void)({ \
|
||||
typeof((fifo) + 1) __tmp = (fifo); \
|
||||
unsigned int __len = (len); \
|
||||
const size_t __recsize = sizeof(*__tmp->rectype); \
|
||||
struct __kfifo *__kfifo = &__tmp->kfifo; \
|
||||
if (__recsize) \
|
||||
__kfifo_dma_in_finish_r(__kfifo, __len, __recsize); \
|
||||
else \
|
||||
__kfifo->in += __len / sizeof(*__tmp->type); \
|
||||
})
|
||||
|
||||
/**
|
||||
* kfifo_dma_out_prepare - setup a scatterlist for DMA output
|
||||
* @fifo: address of the fifo to be used
|
||||
* @sgl: pointer to the scatterlist array
|
||||
* @nents: number of entries in the scatterlist array
|
||||
* @len: number of elements to transfer
|
||||
*
|
||||
* This macro fills a scatterlist for DMA output which at most @len bytes
|
||||
* to transfer.
|
||||
* It returns the number entries in the scatterlist array.
|
||||
* A zero means there is no space available and the scatterlist is not filled.
|
||||
*
|
||||
* Note that with only one concurrent reader and one concurrent
|
||||
* writer, you don't need extra locking to use these macros.
|
||||
*/
|
||||
#define kfifo_dma_out_prepare(fifo, sgl, nents, len) \
|
||||
({ \
|
||||
typeof((fifo) + 1) __tmp = (fifo); \
|
||||
struct scatterlist *__sgl = (sgl); \
|
||||
int __nents = (nents); \
|
||||
unsigned int __len = (len); \
|
||||
const size_t __recsize = sizeof(*__tmp->rectype); \
|
||||
struct __kfifo *__kfifo = &__tmp->kfifo; \
|
||||
(__recsize) ? \
|
||||
__kfifo_dma_out_prepare_r(__kfifo, __sgl, __nents, __len, __recsize) : \
|
||||
__kfifo_dma_out_prepare(__kfifo, __sgl, __nents, __len); \
|
||||
})
|
||||
|
||||
/**
|
||||
* kfifo_dma_out_finish - finish a DMA OUT operation
|
||||
* @fifo: address of the fifo to be used
|
||||
* @len: number of bytes transferred
|
||||
*
|
||||
* This macro finish a DMA OUT operation. The out counter will be updated by
|
||||
* the len parameter. No error checking will be done.
|
||||
*
|
||||
* Note that with only one concurrent reader and one concurrent
|
||||
* writer, you don't need extra locking to use these macros.
|
||||
*/
|
||||
#define kfifo_dma_out_finish(fifo, len) \
|
||||
(void)({ \
|
||||
typeof((fifo) + 1) __tmp = (fifo); \
|
||||
unsigned int __len = (len); \
|
||||
const size_t __recsize = sizeof(*__tmp->rectype); \
|
||||
struct __kfifo *__kfifo = &__tmp->kfifo; \
|
||||
if (__recsize) \
|
||||
__kfifo_dma_out_finish_r(__kfifo, __recsize); \
|
||||
else \
|
||||
__kfifo->out += __len / sizeof(*__tmp->type); \
|
||||
})
|
||||
|
||||
/**
|
||||
* kfifo_out_peek - gets some data from the fifo
|
||||
* @fifo: address of the fifo to be used
|
||||
* @buf: pointer to the storage buffer
|
||||
* @n: max. number of elements to get
|
||||
*
|
||||
* This macro get the data from the fifo and return the numbers of elements
|
||||
* copied. The data is not removed from the fifo.
|
||||
*
|
||||
* Note that with only one concurrent reader and one concurrent
|
||||
* writer, you don't need extra locking to use these macro.
|
||||
*/
|
||||
#define kfifo_out_peek(fifo, buf, n) \
|
||||
__kfifo_uint_must_check_helper( \
|
||||
({ \
|
||||
typeof((fifo) + 1) __tmp = (fifo); \
|
||||
typeof(__tmp->ptr) __buf = (buf); \
|
||||
unsigned long __n = (n); \
|
||||
const size_t __recsize = sizeof(*__tmp->rectype); \
|
||||
struct __kfifo *__kfifo = &__tmp->kfifo; \
|
||||
(__recsize) ? \
|
||||
__kfifo_out_peek_r(__kfifo, __buf, __n, __recsize) : \
|
||||
__kfifo_out_peek(__kfifo, __buf, __n); \
|
||||
}) \
|
||||
)
|
||||
|
||||
extern int __kfifo_alloc(struct __kfifo *fifo, unsigned int size,
|
||||
size_t esize, gfp_t gfp_mask);
|
||||
|
||||
extern void __kfifo_free(struct __kfifo *fifo);
|
||||
|
||||
extern int __kfifo_init(struct __kfifo *fifo, void *buffer,
|
||||
unsigned int size, size_t esize);
|
||||
|
||||
extern unsigned int __kfifo_in(struct __kfifo *fifo,
|
||||
const void *buf, unsigned int len);
|
||||
|
||||
extern unsigned int __kfifo_out(struct __kfifo *fifo,
|
||||
void *buf, unsigned int len);
|
||||
|
||||
extern int __kfifo_from_user(struct __kfifo *fifo,
|
||||
const void __user *from, unsigned long len, unsigned int *copied);
|
||||
|
||||
extern int __kfifo_to_user(struct __kfifo *fifo,
|
||||
void __user *to, unsigned long len, unsigned int *copied);
|
||||
|
||||
extern unsigned int __kfifo_dma_in_prepare(struct __kfifo *fifo,
|
||||
struct scatterlist *sgl, int nents, unsigned int len);
|
||||
|
||||
extern unsigned int __kfifo_dma_out_prepare(struct __kfifo *fifo,
|
||||
struct scatterlist *sgl, int nents, unsigned int len);
|
||||
|
||||
extern unsigned int __kfifo_out_peek(struct __kfifo *fifo,
|
||||
void *buf, unsigned int len);
|
||||
|
||||
extern unsigned int __kfifo_in_r(struct __kfifo *fifo,
|
||||
const void *buf, unsigned int len, size_t recsize);
|
||||
|
||||
extern unsigned int __kfifo_out_r(struct __kfifo *fifo,
|
||||
void *buf, unsigned int len, size_t recsize);
|
||||
|
||||
extern int __kfifo_from_user_r(struct __kfifo *fifo,
|
||||
const void __user *from, unsigned long len, unsigned int *copied,
|
||||
size_t recsize);
|
||||
|
||||
extern int __kfifo_to_user_r(struct __kfifo *fifo, void __user *to,
|
||||
unsigned long len, unsigned int *copied, size_t recsize);
|
||||
|
||||
extern unsigned int __kfifo_dma_in_prepare_r(struct __kfifo *fifo,
|
||||
struct scatterlist *sgl, int nents, unsigned int len, size_t recsize);
|
||||
|
||||
extern void __kfifo_dma_in_finish_r(struct __kfifo *fifo,
|
||||
unsigned int len, size_t recsize);
|
||||
|
||||
extern unsigned int __kfifo_dma_out_prepare_r(struct __kfifo *fifo,
|
||||
struct scatterlist *sgl, int nents, unsigned int len, size_t recsize);
|
||||
|
||||
extern void __kfifo_dma_out_finish_r(struct __kfifo *fifo, size_t recsize);
|
||||
|
||||
extern unsigned int __kfifo_len_r(struct __kfifo *fifo, size_t recsize);
|
||||
|
||||
extern void __kfifo_skip_r(struct __kfifo *fifo, size_t recsize);
|
||||
|
||||
extern unsigned int __kfifo_out_peek_r(struct __kfifo *fifo,
|
||||
void *buf, unsigned int len, size_t recsize);
|
||||
|
||||
extern unsigned int __kfifo_max_r(unsigned int len, size_t recsize);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,57 @@
|
||||
#ifndef _LINUX_KTHREAD_H
|
||||
#define _LINUX_KTHREAD_H
|
||||
/*
|
||||
* Minimal kthread emulation for KolibriOS.
|
||||
*
|
||||
* The GPU scheduler (drivers/video/drm/amdgpu/scheduler) is the only user in
|
||||
* the DRM tree. KolibriOS kernel threads are created with CreateKernelThread(),
|
||||
* which takes no argument, so kthread_run() stashes the payload in a small
|
||||
* pid-indexed table and the trampoline picks it up. Park/stop are cooperative
|
||||
* flags polled by the thread body, matching how the scheduler uses them.
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/rwsem.h>
|
||||
|
||||
/*
|
||||
* Placeholder address space. Drivers reach it as current->mm on their userptr
|
||||
* paths only, which KolibriOS never enters (no ioctl surface for user code).
|
||||
*/
|
||||
struct mm_struct {
|
||||
struct rw_semaphore mmap_sem;
|
||||
};
|
||||
|
||||
struct task_struct {
|
||||
int (*threadfn)(void *data);
|
||||
void *data;
|
||||
int pid;
|
||||
volatile int should_stop;
|
||||
volatile int should_park;
|
||||
volatile int parked;
|
||||
char comm[16];
|
||||
struct mm_struct *mm;
|
||||
};
|
||||
|
||||
struct task_struct *kthread_create_kos(int (*threadfn)(void *data),
|
||||
void *data, const char *name);
|
||||
int kthread_stop(struct task_struct *k);
|
||||
bool kthread_should_stop(void);
|
||||
bool kthread_should_park(void);
|
||||
void kthread_parkme(void);
|
||||
int kthread_park(struct task_struct *k);
|
||||
void kthread_unpark(struct task_struct *k);
|
||||
struct task_struct *kthread_current(void);
|
||||
|
||||
#define kthread_run(threadfn, data, namefmt, ...) \
|
||||
kthread_create_kos((threadfn), (data), (namefmt))
|
||||
|
||||
#define kthread_create(threadfn, data, namefmt, ...) \
|
||||
kthread_create_kos((threadfn), (data), (namefmt))
|
||||
|
||||
static inline void wake_up_process(struct task_struct *k) { }
|
||||
static inline void get_task_struct(struct task_struct *k) { }
|
||||
static inline void put_task_struct(struct task_struct *k) { }
|
||||
|
||||
#endif /* _LINUX_KTHREAD_H */
|
||||
@@ -0,0 +1,24 @@
|
||||
#ifndef _LINUX_MFD_CORE_H
|
||||
#define _LINUX_MFD_CORE_H
|
||||
/*
|
||||
* No multi-function-device bus on KolibriOS. amdgpu_acp.h embeds an
|
||||
* mfd_cell pointer in struct amdgpu_acp; the ACP block itself is not built.
|
||||
*/
|
||||
#include <linux/types.h>
|
||||
struct device;
|
||||
struct resource;
|
||||
|
||||
struct mfd_cell {
|
||||
const char *name;
|
||||
int id;
|
||||
void *platform_data;
|
||||
size_t pdata_size;
|
||||
int num_resources;
|
||||
const struct resource *resources;
|
||||
};
|
||||
|
||||
static inline int mfd_add_hotplug_devices(struct device *parent,
|
||||
const struct mfd_cell *cells, int n)
|
||||
{ return -ENODEV; }
|
||||
static inline void mfd_remove_devices(struct device *parent) { }
|
||||
#endif
|
||||
@@ -8,6 +8,12 @@
|
||||
#define nth_page(page,n) ((void*)(((page_to_phys(page)>>12)+(n))<<12))
|
||||
|
||||
#define __page_to_pfn(page) (page_to_phys(page)>>12)
|
||||
/*
|
||||
* A struct page * here is just the physical address (see page_to_phys() in
|
||||
* <linux/kernel.h>), so the reverse direction is the same shift back.
|
||||
*/
|
||||
#define __pfn_to_page(pfn) ((struct page *)((dma_addr_t)(pfn) << 12))
|
||||
#define pfn_to_page(pfn) __pfn_to_page(pfn)
|
||||
|
||||
/* to align the pointer to the (next) page boundary */
|
||||
#define PAGE_ALIGN(addr) ALIGN(addr, PAGE_SIZE)
|
||||
|
||||
@@ -26,4 +26,14 @@
|
||||
|
||||
struct module {};
|
||||
|
||||
/*
|
||||
* Nothing is a module here - everything is linked into the one image - so the
|
||||
* reference count can never drop and a request for another module can never be
|
||||
* satisfied. Implemented in the driver's kos_* glue.
|
||||
*/
|
||||
extern int request_module(const char *name, ...);
|
||||
extern int try_module_get(struct module *module);
|
||||
extern void module_put(struct module *module);
|
||||
|
||||
|
||||
#endif /* _LINUX_MODULE_H */
|
||||
@@ -77,6 +77,15 @@ void __attribute__ ((fastcall)) __attribute__ ((dllimport))
|
||||
void __attribute__ ((fastcall)) __attribute__ ((dllimport))
|
||||
mutex_unlock(struct mutex*)__asm__("MutexUnlock");
|
||||
|
||||
/*
|
||||
* mutex_init() is the DDK's MutexInit(); these two are the spellings upstream
|
||||
* code reaches for when it wants a lockdep class, which this port does not
|
||||
* have. Both end up in the same place.
|
||||
*/
|
||||
extern void __mutex_init(struct mutex *lock, const char *name,
|
||||
struct lock_class_key *key);
|
||||
extern void mutex_lock_nested(struct mutex *lock, unsigned int subclass);
|
||||
|
||||
static inline int mutex_lock_interruptible(struct mutex *lock)
|
||||
{
|
||||
mutex_lock(lock);
|
||||
|
||||
@@ -0,0 +1,10 @@
|
||||
#ifndef _LINUX_OF_DEVICE_H
|
||||
#define _LINUX_OF_DEVICE_H
|
||||
/* No device tree on x86; pulled in unconditionally by nvif/os.h. */
|
||||
struct device;
|
||||
struct of_device_id;
|
||||
|
||||
static inline const struct of_device_id *
|
||||
of_match_device(const struct of_device_id *m, const struct device *dev)
|
||||
{ return NULL; }
|
||||
#endif
|
||||
@@ -0,0 +1,8 @@
|
||||
#ifndef _LINUX_PAGEMAP_H
|
||||
#define _LINUX_PAGEMAP_H
|
||||
/* Only the shift/size helpers are used by the TTM/GEM paths on this port. */
|
||||
#include <linux/mm.h>
|
||||
#define PAGE_CACHE_SHIFT PAGE_SHIFT
|
||||
#define PAGE_CACHE_SIZE PAGE_SIZE
|
||||
#define PAGE_CACHE_MASK PAGE_MASK
|
||||
#endif
|
||||
@@ -275,6 +275,13 @@ struct pci_dev {
|
||||
struct pci_bus *bus; /* bus this device is on */
|
||||
struct pci_bus *subordinate; /* bus this device bridges to */
|
||||
|
||||
/*
|
||||
* Always NULL on this port: there is no driver model to bind through.
|
||||
* nouveau_drm.c reads it to decide whether the HDMI audio function is
|
||||
* claimed before powering the GPU down, and takes the safe branch.
|
||||
*/
|
||||
struct pci_driver *driver;
|
||||
|
||||
void *sysdata; /* hook for sys-specific extension */
|
||||
// struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
|
||||
struct pci_slot *slot; /* Physical slot this device is in */
|
||||
|
||||
@@ -0,0 +1,7 @@
|
||||
#ifndef _LINUX_PLATFORM_DEVICE_H
|
||||
#define _LINUX_PLATFORM_DEVICE_H
|
||||
/* No platform bus; amdgpu_drv.h only needs the type to exist. */
|
||||
#include <linux/device.h>
|
||||
struct platform_device { struct device dev; const char *name; int id; };
|
||||
struct platform_driver;
|
||||
#endif
|
||||
@@ -0,0 +1,12 @@
|
||||
#ifndef _LINUX_POWER_SUPPLY_H
|
||||
#define _LINUX_POWER_SUPPLY_H
|
||||
/*
|
||||
* No battery subsystem on KolibriOS. power_supply_is_system_supplied() is
|
||||
* already provided by <syscall.h>; only the enum labels are missing.
|
||||
*/
|
||||
enum {
|
||||
POWER_SUPPLY_TYPE_UNKNOWN = 0,
|
||||
POWER_SUPPLY_TYPE_BATTERY,
|
||||
POWER_SUPPLY_TYPE_MAINS,
|
||||
};
|
||||
#endif
|
||||
@@ -0,0 +1,22 @@
|
||||
#ifndef _LINUX_REBOOT_H
|
||||
#define _LINUX_REBOOT_H
|
||||
/*
|
||||
* No reboot notifier chain on this port. nvif/os.h includes this header for
|
||||
* every nvkm translation unit; nothing in the built set registers a notifier.
|
||||
*/
|
||||
#include <linux/notifier.h>
|
||||
|
||||
#define SYS_RESTART 0x0001
|
||||
#define SYS_HALT 0x0002
|
||||
#define SYS_POWER_OFF 0x0003
|
||||
|
||||
static inline int register_reboot_notifier(struct notifier_block *nb) { return 0; }
|
||||
static inline int unregister_reboot_notifier(struct notifier_block *nb) { return 0; }
|
||||
|
||||
/*
|
||||
* nvkm/subdev/therm/temp.c asks for this when the GPU passes its shutdown
|
||||
* threshold. There is no orderly shutdown to request on KolibriOS; the
|
||||
* driver's implementation logs and returns.
|
||||
*/
|
||||
extern int orderly_poweroff(bool force);
|
||||
#endif
|
||||
@@ -0,0 +1,18 @@
|
||||
#ifndef _LINUX_REGULATOR_CONSUMER_H
|
||||
#define _LINUX_REGULATOR_CONSUMER_H
|
||||
/* Tegra-only; see linux/clk.h for why this exists at all. */
|
||||
#include <linux/errno.h>
|
||||
#include <linux/err.h>
|
||||
|
||||
struct regulator;
|
||||
struct device;
|
||||
|
||||
static inline struct regulator *regulator_get(struct device *dev, const char *id)
|
||||
{ return ERR_PTR(-ENOENT); }
|
||||
static inline void regulator_put(struct regulator *r) { }
|
||||
static inline int regulator_enable(struct regulator *r) { return -ENOSYS; }
|
||||
static inline int regulator_disable(struct regulator *r) { return -ENOSYS; }
|
||||
static inline int regulator_get_voltage(struct regulator *r) { return -ENODEV; }
|
||||
static inline int regulator_set_voltage(struct regulator *r, int min_uV, int max_uV)
|
||||
{ return -ENODEV; }
|
||||
#endif
|
||||
@@ -0,0 +1,15 @@
|
||||
#ifndef _LINUX_RESET_H
|
||||
#define _LINUX_RESET_H
|
||||
/* Tegra-only; see linux/clk.h for why this exists at all. */
|
||||
#include <linux/errno.h>
|
||||
#include <linux/err.h>
|
||||
|
||||
struct reset_control;
|
||||
struct device;
|
||||
|
||||
static inline struct reset_control *reset_control_get(struct device *dev, const char *id)
|
||||
{ return ERR_PTR(-ENOENT); }
|
||||
static inline void reset_control_put(struct reset_control *rstc) { }
|
||||
static inline int reset_control_assert(struct reset_control *rstc) { return -ENOSYS; }
|
||||
static inline int reset_control_deassert(struct reset_control *rstc) { return -ENOSYS; }
|
||||
#endif
|
||||
@@ -49,4 +49,14 @@
|
||||
#define schedule_timeout(x) delay(x)
|
||||
#define MAX_SCHEDULE_TIMEOUT LONG_MAX
|
||||
|
||||
/*
|
||||
* No processes and no signals behind a driver thread: signal_pending() is
|
||||
* always false, so interruptible waits only ever end on their timeout, and
|
||||
* every task carries the singleton name set in kos_stubs.c.
|
||||
*/
|
||||
struct task_struct;
|
||||
extern int signal_pending(struct task_struct *p);
|
||||
extern void __set_current_state(int state);
|
||||
extern char *get_task_comm(char *buf, struct task_struct *tsk);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,19 @@
|
||||
#ifndef _LINUX_SCREEN_INFO_H
|
||||
#define _LINUX_SCREEN_INFO_H
|
||||
/*
|
||||
* nouveau_fbcon.c only uses this to decide whether it owns the boot console.
|
||||
* KolibriOS has no boot console to hand over, so the record stays empty.
|
||||
*/
|
||||
#include <linux/types.h>
|
||||
|
||||
struct screen_info {
|
||||
__u8 orig_video_isVGA;
|
||||
__u16 lfb_width;
|
||||
__u16 lfb_height;
|
||||
__u16 lfb_depth;
|
||||
__u32 lfb_base;
|
||||
__u32 lfb_size;
|
||||
};
|
||||
|
||||
extern struct screen_info screen_info;
|
||||
#endif
|
||||
@@ -0,0 +1,5 @@
|
||||
#ifndef _LINUX_SWIOTLB_H
|
||||
#define _LINUX_SWIOTLB_H
|
||||
/* No bounce buffers on this port; amdgpu_ttm.c only queries swiotlb_nr_tbl(). */
|
||||
static inline unsigned long swiotlb_nr_tbl(void) { return 0; }
|
||||
#endif
|
||||
@@ -0,0 +1,35 @@
|
||||
#ifndef _LINUX_TRACEPOINT_H
|
||||
#define _LINUX_TRACEPOINT_H
|
||||
/* Tracepoints compile away: amdgpu_trace.h expands to empty trace_*() calls. */
|
||||
/*
|
||||
* Each event still has to yield a callable trace_<name>(), because the driver
|
||||
* code calls it unconditionally - upstream generates one per event. Here they
|
||||
* expand to empty inlines, so the calls disappear at -O2 but the argument
|
||||
* expressions are still type-checked.
|
||||
*/
|
||||
#define TP_PROTO(args...) args
|
||||
#define TP_ARGS(args...) args
|
||||
#define TP_STRUCT__entry(args...)
|
||||
#define TP_fast_assign(args...)
|
||||
#define TP_printk(fmt, args...)
|
||||
#define TP_CONDITION(args...)
|
||||
|
||||
#define DECLARE_EVENT_CLASS(name, proto, args, tstruct, assign, print)
|
||||
|
||||
#define DEFINE_EVENT(tmpl, name, proto, args) \
|
||||
static inline void trace_##name(proto) { } \
|
||||
static inline bool trace_##name##_enabled(void) { return false; }
|
||||
|
||||
#define TRACE_EVENT(name, proto, args, tstruct, assign, print) \
|
||||
static inline void trace_##name(proto) { } \
|
||||
static inline bool trace_##name##_enabled(void) { return false; }
|
||||
|
||||
#define TRACE_EVENT_CONDITION(name, proto, args, cond, tstruct, assign, print) \
|
||||
static inline void trace_##name(proto) { } \
|
||||
static inline bool trace_##name##_enabled(void) { return false; }
|
||||
|
||||
#define DECLARE_TRACE(name, proto, args) \
|
||||
static inline void trace_##name(proto) { }
|
||||
#define EXPORT_TRACEPOINT_SYMBOL_GPL(name)
|
||||
#define EXPORT_TRACEPOINT_SYMBOL(name)
|
||||
#endif
|
||||
@@ -0,0 +1,5 @@
|
||||
#ifndef _LINUX_TTY_H
|
||||
#define _LINUX_TTY_H
|
||||
/* No tty layer; nouveau_fbcon.c includes it for console_lock() neighbours. */
|
||||
#include <linux/console.h>
|
||||
#endif
|
||||
@@ -188,6 +188,7 @@ static inline enum vga_switcheroo_handler_flags_t vga_switcheroo_handler_flags(v
|
||||
static inline int vga_switcheroo_lock_ddc(struct pci_dev *pdev) { return -ENODEV; }
|
||||
static inline int vga_switcheroo_unlock_ddc(struct pci_dev *pdev) { return -ENODEV; }
|
||||
static inline int vga_switcheroo_process_delayed_switch(void) { return 0; }
|
||||
static inline bool vga_switcheroo_client_probe_defer(struct pci_dev *pdev) { return false; }
|
||||
static inline enum vga_switcheroo_state vga_switcheroo_get_client_state(struct pci_dev *dev) { return VGA_SWITCHEROO_ON; }
|
||||
|
||||
static inline void vga_switcheroo_set_dynamic_switch(struct pci_dev *pdev, enum vga_switcheroo_state dynamic) {}
|
||||
|
||||
@@ -30,6 +30,12 @@ extern void *vmalloc(unsigned long size);
|
||||
extern void *vzalloc(unsigned long size);
|
||||
extern void vfree(const void *addr);
|
||||
|
||||
/*
|
||||
* kmalloc() and vmalloc() come from the same allocator on this port, so one
|
||||
* free serves both - which is what kvfree() means upstream too.
|
||||
*/
|
||||
extern void kvfree(const void *addr);
|
||||
|
||||
extern void *vmap(struct page **pages, unsigned int count,
|
||||
unsigned long flags, pgprot_t prot);
|
||||
extern void vunmap(const void *addr);
|
||||
|
||||
@@ -326,6 +326,30 @@ int autoremove_wake_function(wait_queue_t *wait, unsigned mode, int sync, void *
|
||||
|
||||
#define DEFINE_WAIT(name) DEFINE_WAIT_FUNC(name, autoremove_wake_function)
|
||||
|
||||
/*
|
||||
* The "_locked" variants are entered with wq.lock already held and must give
|
||||
* it up while waiting. That rules out the event-based path above, which takes
|
||||
* the lock itself, so these poll instead - the same trade the rest of this
|
||||
* header already makes.
|
||||
*
|
||||
* Because nothing ever blocks on an event here, wake_up_all_locked() has
|
||||
* nothing to signal: the waiter re-tests the condition on its next tick.
|
||||
*/
|
||||
#define wait_event_interruptible_locked(wq, condition) \
|
||||
({ \
|
||||
while (!(condition)) { \
|
||||
spin_unlock(&(wq).lock); \
|
||||
delay(1); \
|
||||
spin_lock(&(wq).lock); \
|
||||
} \
|
||||
0; \
|
||||
})
|
||||
|
||||
#define wait_event_locked(wq, condition) \
|
||||
wait_event_interruptible_locked(wq, condition)
|
||||
|
||||
#define wake_up_locked(q) do { } while (0)
|
||||
#define wake_up_all_locked(q) do { } while (0)
|
||||
|
||||
#endif
|
||||
|
||||
@@ -268,6 +268,9 @@ static inline bool mod_delayed_work(struct workqueue_struct *wq,
|
||||
(_work)->work.func = _func; \
|
||||
} while (0)
|
||||
|
||||
/* Defined in each driver's kos_kernel.c. */
|
||||
extern bool flush_work(struct work_struct *work);
|
||||
|
||||
static inline bool schedule_work(struct work_struct *work)
|
||||
{
|
||||
return queue_work(system_wq, work);
|
||||
|
||||
@@ -0,0 +1,5 @@
|
||||
#ifndef __SOC_TEGRA_FUSE_H
|
||||
#define __SOC_TEGRA_FUSE_H
|
||||
/* Tegra-only; nvif/os.h includes it unconditionally. */
|
||||
static inline int tegra_sku_info_dummy(void) { return 0; }
|
||||
#endif
|
||||
@@ -0,0 +1,5 @@
|
||||
#ifndef __SOC_TEGRA_PMC_H
|
||||
#define __SOC_TEGRA_PMC_H
|
||||
/* Tegra-only; nvif/os.h includes it unconditionally. */
|
||||
static inline int tegra_pmc_dummy(void) { return 0; }
|
||||
#endif
|
||||
@@ -0,0 +1,5 @@
|
||||
#ifndef _TRACE_DEFINE_TRACE_H
|
||||
#define _TRACE_DEFINE_TRACE_H
|
||||
/* Tracepoints are compiled out - see linux/tracepoint.h. */
|
||||
#undef TRACE_HEADER_MULTI_READ
|
||||
#endif
|
||||
@@ -0,0 +1,6 @@
|
||||
#ifndef _TRACE_EVENTS_FENCE_H
|
||||
#define _TRACE_EVENTS_FENCE_H
|
||||
/* Tracepoints are compiled out; nouveau_fence.c is the only includer. */
|
||||
struct fence;
|
||||
static inline void trace_fence_emit(struct fence *fence) { }
|
||||
#endif
|
||||
@@ -68,7 +68,14 @@
|
||||
((nr) << _IOC_NRSHIFT) | \
|
||||
((size) << _IOC_SIZESHIFT))
|
||||
|
||||
#ifndef __KERNEL__
|
||||
#ifdef __KERNEL__
|
||||
/* provoke compile error for invalid uses of size argument */
|
||||
extern unsigned int __invalid_size_argument_for_IOC;
|
||||
#define _IOC_TYPECHECK(t) \
|
||||
((sizeof(t) == sizeof(t[1]) && \
|
||||
sizeof(t) < (1 << _IOC_SIZEBITS)) ? \
|
||||
sizeof(t) : __invalid_size_argument_for_IOC)
|
||||
#else
|
||||
#define _IOC_TYPECHECK(t) (sizeof(t))
|
||||
#endif
|
||||
|
||||
|
||||
@@ -0,0 +1,662 @@
|
||||
/* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*-
|
||||
*
|
||||
* Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
|
||||
* Copyright 2000 VA Linux Systems, Inc., Fremont, California.
|
||||
* Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
|
||||
* Copyright 2014 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors:
|
||||
* Kevin E. Martin <martin@valinux.com>
|
||||
* Gareth Hughes <gareth@valinux.com>
|
||||
* Keith Whitwell <keith@tungstengraphics.com>
|
||||
*/
|
||||
|
||||
#ifndef __AMDGPU_DRM_H__
|
||||
#define __AMDGPU_DRM_H__
|
||||
|
||||
#include "drm.h"
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define DRM_AMDGPU_GEM_CREATE 0x00
|
||||
#define DRM_AMDGPU_GEM_MMAP 0x01
|
||||
#define DRM_AMDGPU_CTX 0x02
|
||||
#define DRM_AMDGPU_BO_LIST 0x03
|
||||
#define DRM_AMDGPU_CS 0x04
|
||||
#define DRM_AMDGPU_INFO 0x05
|
||||
#define DRM_AMDGPU_GEM_METADATA 0x06
|
||||
#define DRM_AMDGPU_GEM_WAIT_IDLE 0x07
|
||||
#define DRM_AMDGPU_GEM_VA 0x08
|
||||
#define DRM_AMDGPU_WAIT_CS 0x09
|
||||
#define DRM_AMDGPU_GEM_OP 0x10
|
||||
#define DRM_AMDGPU_GEM_USERPTR 0x11
|
||||
|
||||
#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
|
||||
#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
|
||||
#define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx)
|
||||
#define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list)
|
||||
#define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs)
|
||||
#define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info)
|
||||
#define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata)
|
||||
#define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle)
|
||||
#define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va)
|
||||
#define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs)
|
||||
#define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)
|
||||
#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
|
||||
|
||||
#define AMDGPU_GEM_DOMAIN_CPU 0x1
|
||||
#define AMDGPU_GEM_DOMAIN_GTT 0x2
|
||||
#define AMDGPU_GEM_DOMAIN_VRAM 0x4
|
||||
#define AMDGPU_GEM_DOMAIN_GDS 0x8
|
||||
#define AMDGPU_GEM_DOMAIN_GWS 0x10
|
||||
#define AMDGPU_GEM_DOMAIN_OA 0x20
|
||||
|
||||
/* Flag that CPU access will be required for the case of VRAM domain */
|
||||
#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)
|
||||
/* Flag that CPU access will not work, this VRAM domain is invisible */
|
||||
#define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1)
|
||||
/* Flag that USWC attributes should be used for GTT */
|
||||
#define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2)
|
||||
/* Flag that the memory should be in VRAM and cleared */
|
||||
#define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3)
|
||||
/* Flag that create shadow bo(GTT) while allocating vram bo */
|
||||
#define AMDGPU_GEM_CREATE_SHADOW (1 << 4)
|
||||
|
||||
struct drm_amdgpu_gem_create_in {
|
||||
/** the requested memory size */
|
||||
__u64 bo_size;
|
||||
/** physical start_addr alignment in bytes for some HW requirements */
|
||||
__u64 alignment;
|
||||
/** the requested memory domains */
|
||||
__u64 domains;
|
||||
/** allocation flags */
|
||||
__u64 domain_flags;
|
||||
};
|
||||
|
||||
struct drm_amdgpu_gem_create_out {
|
||||
/** returned GEM object handle */
|
||||
__u32 handle;
|
||||
__u32 _pad;
|
||||
};
|
||||
|
||||
union drm_amdgpu_gem_create {
|
||||
struct drm_amdgpu_gem_create_in in;
|
||||
struct drm_amdgpu_gem_create_out out;
|
||||
};
|
||||
|
||||
/** Opcode to create new residency list. */
|
||||
#define AMDGPU_BO_LIST_OP_CREATE 0
|
||||
/** Opcode to destroy previously created residency list */
|
||||
#define AMDGPU_BO_LIST_OP_DESTROY 1
|
||||
/** Opcode to update resource information in the list */
|
||||
#define AMDGPU_BO_LIST_OP_UPDATE 2
|
||||
|
||||
struct drm_amdgpu_bo_list_in {
|
||||
/** Type of operation */
|
||||
__u32 operation;
|
||||
/** Handle of list or 0 if we want to create one */
|
||||
__u32 list_handle;
|
||||
/** Number of BOs in list */
|
||||
__u32 bo_number;
|
||||
/** Size of each element describing BO */
|
||||
__u32 bo_info_size;
|
||||
/** Pointer to array describing BOs */
|
||||
__u64 bo_info_ptr;
|
||||
};
|
||||
|
||||
struct drm_amdgpu_bo_list_entry {
|
||||
/** Handle of BO */
|
||||
__u32 bo_handle;
|
||||
/** New (if specified) BO priority to be used during migration */
|
||||
__u32 bo_priority;
|
||||
};
|
||||
|
||||
struct drm_amdgpu_bo_list_out {
|
||||
/** Handle of resource list */
|
||||
__u32 list_handle;
|
||||
__u32 _pad;
|
||||
};
|
||||
|
||||
union drm_amdgpu_bo_list {
|
||||
struct drm_amdgpu_bo_list_in in;
|
||||
struct drm_amdgpu_bo_list_out out;
|
||||
};
|
||||
|
||||
/* context related */
|
||||
#define AMDGPU_CTX_OP_ALLOC_CTX 1
|
||||
#define AMDGPU_CTX_OP_FREE_CTX 2
|
||||
#define AMDGPU_CTX_OP_QUERY_STATE 3
|
||||
|
||||
/* GPU reset status */
|
||||
#define AMDGPU_CTX_NO_RESET 0
|
||||
/* this the context caused it */
|
||||
#define AMDGPU_CTX_GUILTY_RESET 1
|
||||
/* some other context caused it */
|
||||
#define AMDGPU_CTX_INNOCENT_RESET 2
|
||||
/* unknown cause */
|
||||
#define AMDGPU_CTX_UNKNOWN_RESET 3
|
||||
|
||||
struct drm_amdgpu_ctx_in {
|
||||
/** AMDGPU_CTX_OP_* */
|
||||
__u32 op;
|
||||
/** For future use, no flags defined so far */
|
||||
__u32 flags;
|
||||
__u32 ctx_id;
|
||||
__u32 _pad;
|
||||
};
|
||||
|
||||
union drm_amdgpu_ctx_out {
|
||||
struct {
|
||||
__u32 ctx_id;
|
||||
__u32 _pad;
|
||||
} alloc;
|
||||
|
||||
struct {
|
||||
/** For future use, no flags defined so far */
|
||||
__u64 flags;
|
||||
/** Number of resets caused by this context so far. */
|
||||
__u32 hangs;
|
||||
/** Reset status since the last call of the ioctl. */
|
||||
__u32 reset_status;
|
||||
} state;
|
||||
};
|
||||
|
||||
union drm_amdgpu_ctx {
|
||||
struct drm_amdgpu_ctx_in in;
|
||||
union drm_amdgpu_ctx_out out;
|
||||
};
|
||||
|
||||
/*
|
||||
* This is not a reliable API and you should expect it to fail for any
|
||||
* number of reasons and have fallback path that do not use userptr to
|
||||
* perform any operation.
|
||||
*/
|
||||
#define AMDGPU_GEM_USERPTR_READONLY (1 << 0)
|
||||
#define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1)
|
||||
#define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2)
|
||||
#define AMDGPU_GEM_USERPTR_REGISTER (1 << 3)
|
||||
|
||||
struct drm_amdgpu_gem_userptr {
|
||||
__u64 addr;
|
||||
__u64 size;
|
||||
/* AMDGPU_GEM_USERPTR_* */
|
||||
__u32 flags;
|
||||
/* Resulting GEM handle */
|
||||
__u32 handle;
|
||||
};
|
||||
|
||||
/* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */
|
||||
#define AMDGPU_TILING_ARRAY_MODE_SHIFT 0
|
||||
#define AMDGPU_TILING_ARRAY_MODE_MASK 0xf
|
||||
#define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4
|
||||
#define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f
|
||||
#define AMDGPU_TILING_TILE_SPLIT_SHIFT 9
|
||||
#define AMDGPU_TILING_TILE_SPLIT_MASK 0x7
|
||||
#define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12
|
||||
#define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7
|
||||
#define AMDGPU_TILING_BANK_WIDTH_SHIFT 15
|
||||
#define AMDGPU_TILING_BANK_WIDTH_MASK 0x3
|
||||
#define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17
|
||||
#define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3
|
||||
#define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19
|
||||
#define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3
|
||||
#define AMDGPU_TILING_NUM_BANKS_SHIFT 21
|
||||
#define AMDGPU_TILING_NUM_BANKS_MASK 0x3
|
||||
|
||||
#define AMDGPU_TILING_SET(field, value) \
|
||||
(((value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)
|
||||
#define AMDGPU_TILING_GET(value, field) \
|
||||
(((value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)
|
||||
|
||||
#define AMDGPU_GEM_METADATA_OP_SET_METADATA 1
|
||||
#define AMDGPU_GEM_METADATA_OP_GET_METADATA 2
|
||||
|
||||
/** The same structure is shared for input/output */
|
||||
struct drm_amdgpu_gem_metadata {
|
||||
/** GEM Object handle */
|
||||
__u32 handle;
|
||||
/** Do we want get or set metadata */
|
||||
__u32 op;
|
||||
struct {
|
||||
/** For future use, no flags defined so far */
|
||||
__u64 flags;
|
||||
/** family specific tiling info */
|
||||
__u64 tiling_info;
|
||||
__u32 data_size_bytes;
|
||||
__u32 data[64];
|
||||
} data;
|
||||
};
|
||||
|
||||
struct drm_amdgpu_gem_mmap_in {
|
||||
/** the GEM object handle */
|
||||
__u32 handle;
|
||||
__u32 _pad;
|
||||
};
|
||||
|
||||
struct drm_amdgpu_gem_mmap_out {
|
||||
/** mmap offset from the vma offset manager */
|
||||
__u64 addr_ptr;
|
||||
};
|
||||
|
||||
union drm_amdgpu_gem_mmap {
|
||||
struct drm_amdgpu_gem_mmap_in in;
|
||||
struct drm_amdgpu_gem_mmap_out out;
|
||||
};
|
||||
|
||||
struct drm_amdgpu_gem_wait_idle_in {
|
||||
/** GEM object handle */
|
||||
__u32 handle;
|
||||
/** For future use, no flags defined so far */
|
||||
__u32 flags;
|
||||
/** Absolute timeout to wait */
|
||||
__u64 timeout;
|
||||
};
|
||||
|
||||
struct drm_amdgpu_gem_wait_idle_out {
|
||||
/** BO status: 0 - BO is idle, 1 - BO is busy */
|
||||
__u32 status;
|
||||
/** Returned current memory domain */
|
||||
__u32 domain;
|
||||
};
|
||||
|
||||
union drm_amdgpu_gem_wait_idle {
|
||||
struct drm_amdgpu_gem_wait_idle_in in;
|
||||
struct drm_amdgpu_gem_wait_idle_out out;
|
||||
};
|
||||
|
||||
struct drm_amdgpu_wait_cs_in {
|
||||
/** Command submission handle */
|
||||
__u64 handle;
|
||||
/** Absolute timeout to wait */
|
||||
__u64 timeout;
|
||||
__u32 ip_type;
|
||||
__u32 ip_instance;
|
||||
__u32 ring;
|
||||
__u32 ctx_id;
|
||||
};
|
||||
|
||||
struct drm_amdgpu_wait_cs_out {
|
||||
/** CS status: 0 - CS completed, 1 - CS still busy */
|
||||
__u64 status;
|
||||
};
|
||||
|
||||
union drm_amdgpu_wait_cs {
|
||||
struct drm_amdgpu_wait_cs_in in;
|
||||
struct drm_amdgpu_wait_cs_out out;
|
||||
};
|
||||
|
||||
#define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0
|
||||
#define AMDGPU_GEM_OP_SET_PLACEMENT 1
|
||||
|
||||
/* Sets or returns a value associated with a buffer. */
|
||||
struct drm_amdgpu_gem_op {
|
||||
/** GEM object handle */
|
||||
__u32 handle;
|
||||
/** AMDGPU_GEM_OP_* */
|
||||
__u32 op;
|
||||
/** Input or return value */
|
||||
__u64 value;
|
||||
};
|
||||
|
||||
#define AMDGPU_VA_OP_MAP 1
|
||||
#define AMDGPU_VA_OP_UNMAP 2
|
||||
|
||||
/* Delay the page table update till the next CS */
|
||||
#define AMDGPU_VM_DELAY_UPDATE (1 << 0)
|
||||
|
||||
/* Mapping flags */
|
||||
/* readable mapping */
|
||||
#define AMDGPU_VM_PAGE_READABLE (1 << 1)
|
||||
/* writable mapping */
|
||||
#define AMDGPU_VM_PAGE_WRITEABLE (1 << 2)
|
||||
/* executable mapping, new for VI */
|
||||
#define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3)
|
||||
|
||||
struct drm_amdgpu_gem_va {
|
||||
/** GEM object handle */
|
||||
__u32 handle;
|
||||
__u32 _pad;
|
||||
/** AMDGPU_VA_OP_* */
|
||||
__u32 operation;
|
||||
/** AMDGPU_VM_PAGE_* */
|
||||
__u32 flags;
|
||||
/** va address to assign . Must be correctly aligned.*/
|
||||
__u64 va_address;
|
||||
/** Specify offset inside of BO to assign. Must be correctly aligned.*/
|
||||
__u64 offset_in_bo;
|
||||
/** Specify mapping size. Must be correctly aligned. */
|
||||
__u64 map_size;
|
||||
};
|
||||
|
||||
#define AMDGPU_HW_IP_GFX 0
|
||||
#define AMDGPU_HW_IP_COMPUTE 1
|
||||
#define AMDGPU_HW_IP_DMA 2
|
||||
#define AMDGPU_HW_IP_UVD 3
|
||||
#define AMDGPU_HW_IP_VCE 4
|
||||
#define AMDGPU_HW_IP_NUM 5
|
||||
|
||||
#define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1
|
||||
|
||||
#define AMDGPU_CHUNK_ID_IB 0x01
|
||||
#define AMDGPU_CHUNK_ID_FENCE 0x02
|
||||
#define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03
|
||||
|
||||
struct drm_amdgpu_cs_chunk {
|
||||
__u32 chunk_id;
|
||||
__u32 length_dw;
|
||||
__u64 chunk_data;
|
||||
};
|
||||
|
||||
struct drm_amdgpu_cs_in {
|
||||
/** Rendering context id */
|
||||
__u32 ctx_id;
|
||||
/** Handle of resource list associated with CS */
|
||||
__u32 bo_list_handle;
|
||||
__u32 num_chunks;
|
||||
__u32 _pad;
|
||||
/** this points to __u64 * which point to cs chunks */
|
||||
__u64 chunks;
|
||||
};
|
||||
|
||||
struct drm_amdgpu_cs_out {
|
||||
__u64 handle;
|
||||
};
|
||||
|
||||
union drm_amdgpu_cs {
|
||||
struct drm_amdgpu_cs_in in;
|
||||
struct drm_amdgpu_cs_out out;
|
||||
};
|
||||
|
||||
/* Specify flags to be used for IB */
|
||||
|
||||
/* This IB should be submitted to CE */
|
||||
#define AMDGPU_IB_FLAG_CE (1<<0)
|
||||
|
||||
/* CE Preamble */
|
||||
#define AMDGPU_IB_FLAG_PREAMBLE (1<<1)
|
||||
|
||||
struct drm_amdgpu_cs_chunk_ib {
|
||||
__u32 _pad;
|
||||
/** AMDGPU_IB_FLAG_* */
|
||||
__u32 flags;
|
||||
/** Virtual address to begin IB execution */
|
||||
__u64 va_start;
|
||||
/** Size of submission */
|
||||
__u32 ib_bytes;
|
||||
/** HW IP to submit to */
|
||||
__u32 ip_type;
|
||||
/** HW IP index of the same type to submit to */
|
||||
__u32 ip_instance;
|
||||
/** Ring index to submit to */
|
||||
__u32 ring;
|
||||
};
|
||||
|
||||
struct drm_amdgpu_cs_chunk_dep {
|
||||
__u32 ip_type;
|
||||
__u32 ip_instance;
|
||||
__u32 ring;
|
||||
__u32 ctx_id;
|
||||
__u64 handle;
|
||||
};
|
||||
|
||||
struct drm_amdgpu_cs_chunk_fence {
|
||||
__u32 handle;
|
||||
__u32 offset;
|
||||
};
|
||||
|
||||
struct drm_amdgpu_cs_chunk_data {
|
||||
union {
|
||||
struct drm_amdgpu_cs_chunk_ib ib_data;
|
||||
struct drm_amdgpu_cs_chunk_fence fence_data;
|
||||
};
|
||||
};
|
||||
|
||||
/**
|
||||
* Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU
|
||||
*
|
||||
*/
|
||||
#define AMDGPU_IDS_FLAGS_FUSION 0x1
|
||||
|
||||
/* indicate if acceleration can be working */
|
||||
#define AMDGPU_INFO_ACCEL_WORKING 0x00
|
||||
/* get the crtc_id from the mode object id? */
|
||||
#define AMDGPU_INFO_CRTC_FROM_ID 0x01
|
||||
/* query hw IP info */
|
||||
#define AMDGPU_INFO_HW_IP_INFO 0x02
|
||||
/* query hw IP instance count for the specified type */
|
||||
#define AMDGPU_INFO_HW_IP_COUNT 0x03
|
||||
/* timestamp for GL_ARB_timer_query */
|
||||
#define AMDGPU_INFO_TIMESTAMP 0x05
|
||||
/* Query the firmware version */
|
||||
#define AMDGPU_INFO_FW_VERSION 0x0e
|
||||
/* Subquery id: Query VCE firmware version */
|
||||
#define AMDGPU_INFO_FW_VCE 0x1
|
||||
/* Subquery id: Query UVD firmware version */
|
||||
#define AMDGPU_INFO_FW_UVD 0x2
|
||||
/* Subquery id: Query GMC firmware version */
|
||||
#define AMDGPU_INFO_FW_GMC 0x03
|
||||
/* Subquery id: Query GFX ME firmware version */
|
||||
#define AMDGPU_INFO_FW_GFX_ME 0x04
|
||||
/* Subquery id: Query GFX PFP firmware version */
|
||||
#define AMDGPU_INFO_FW_GFX_PFP 0x05
|
||||
/* Subquery id: Query GFX CE firmware version */
|
||||
#define AMDGPU_INFO_FW_GFX_CE 0x06
|
||||
/* Subquery id: Query GFX RLC firmware version */
|
||||
#define AMDGPU_INFO_FW_GFX_RLC 0x07
|
||||
/* Subquery id: Query GFX MEC firmware version */
|
||||
#define AMDGPU_INFO_FW_GFX_MEC 0x08
|
||||
/* Subquery id: Query SMC firmware version */
|
||||
#define AMDGPU_INFO_FW_SMC 0x0a
|
||||
/* Subquery id: Query SDMA firmware version */
|
||||
#define AMDGPU_INFO_FW_SDMA 0x0b
|
||||
/* number of bytes moved for TTM migration */
|
||||
#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f
|
||||
/* the used VRAM size */
|
||||
#define AMDGPU_INFO_VRAM_USAGE 0x10
|
||||
/* the used GTT size */
|
||||
#define AMDGPU_INFO_GTT_USAGE 0x11
|
||||
/* Information about GDS, etc. resource configuration */
|
||||
#define AMDGPU_INFO_GDS_CONFIG 0x13
|
||||
/* Query information about VRAM and GTT domains */
|
||||
#define AMDGPU_INFO_VRAM_GTT 0x14
|
||||
/* Query information about register in MMR address space*/
|
||||
#define AMDGPU_INFO_READ_MMR_REG 0x15
|
||||
/* Query information about device: rev id, family, etc. */
|
||||
#define AMDGPU_INFO_DEV_INFO 0x16
|
||||
/* visible vram usage */
|
||||
#define AMDGPU_INFO_VIS_VRAM_USAGE 0x17
|
||||
/* number of TTM buffer evictions */
|
||||
#define AMDGPU_INFO_NUM_EVICTIONS 0x18
|
||||
|
||||
#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
|
||||
#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
|
||||
#define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8
|
||||
#define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff
|
||||
|
||||
struct drm_amdgpu_query_fw {
|
||||
/** AMDGPU_INFO_FW_* */
|
||||
__u32 fw_type;
|
||||
/**
|
||||
* Index of the IP if there are more IPs of
|
||||
* the same type.
|
||||
*/
|
||||
__u32 ip_instance;
|
||||
/**
|
||||
* Index of the engine. Whether this is used depends
|
||||
* on the firmware type. (e.g. MEC, SDMA)
|
||||
*/
|
||||
__u32 index;
|
||||
__u32 _pad;
|
||||
};
|
||||
|
||||
/* Input structure for the INFO ioctl */
|
||||
struct drm_amdgpu_info {
|
||||
/* Where the return value will be stored */
|
||||
__u64 return_pointer;
|
||||
/* The size of the return value. Just like "size" in "snprintf",
|
||||
* it limits how many bytes the kernel can write. */
|
||||
__u32 return_size;
|
||||
/* The query request id. */
|
||||
__u32 query;
|
||||
|
||||
union {
|
||||
struct {
|
||||
__u32 id;
|
||||
__u32 _pad;
|
||||
} mode_crtc;
|
||||
|
||||
struct {
|
||||
/** AMDGPU_HW_IP_* */
|
||||
__u32 type;
|
||||
/**
|
||||
* Index of the IP if there are more IPs of the same
|
||||
* type. Ignored by AMDGPU_INFO_HW_IP_COUNT.
|
||||
*/
|
||||
__u32 ip_instance;
|
||||
} query_hw_ip;
|
||||
|
||||
struct {
|
||||
__u32 dword_offset;
|
||||
/** number of registers to read */
|
||||
__u32 count;
|
||||
__u32 instance;
|
||||
/** For future use, no flags defined so far */
|
||||
__u32 flags;
|
||||
} read_mmr_reg;
|
||||
|
||||
struct drm_amdgpu_query_fw query_fw;
|
||||
};
|
||||
};
|
||||
|
||||
struct drm_amdgpu_info_gds {
|
||||
/** GDS GFX partition size */
|
||||
__u32 gds_gfx_partition_size;
|
||||
/** GDS compute partition size */
|
||||
__u32 compute_partition_size;
|
||||
/** total GDS memory size */
|
||||
__u32 gds_total_size;
|
||||
/** GWS size per GFX partition */
|
||||
__u32 gws_per_gfx_partition;
|
||||
/** GSW size per compute partition */
|
||||
__u32 gws_per_compute_partition;
|
||||
/** OA size per GFX partition */
|
||||
__u32 oa_per_gfx_partition;
|
||||
/** OA size per compute partition */
|
||||
__u32 oa_per_compute_partition;
|
||||
__u32 _pad;
|
||||
};
|
||||
|
||||
struct drm_amdgpu_info_vram_gtt {
|
||||
__u64 vram_size;
|
||||
__u64 vram_cpu_accessible_size;
|
||||
__u64 gtt_size;
|
||||
};
|
||||
|
||||
struct drm_amdgpu_info_firmware {
|
||||
__u32 ver;
|
||||
__u32 feature;
|
||||
};
|
||||
|
||||
#define AMDGPU_VRAM_TYPE_UNKNOWN 0
|
||||
#define AMDGPU_VRAM_TYPE_GDDR1 1
|
||||
#define AMDGPU_VRAM_TYPE_DDR2 2
|
||||
#define AMDGPU_VRAM_TYPE_GDDR3 3
|
||||
#define AMDGPU_VRAM_TYPE_GDDR4 4
|
||||
#define AMDGPU_VRAM_TYPE_GDDR5 5
|
||||
#define AMDGPU_VRAM_TYPE_HBM 6
|
||||
#define AMDGPU_VRAM_TYPE_DDR3 7
|
||||
|
||||
struct drm_amdgpu_info_device {
|
||||
/** PCI Device ID */
|
||||
__u32 device_id;
|
||||
/** Internal chip revision: A0, A1, etc.) */
|
||||
__u32 chip_rev;
|
||||
__u32 external_rev;
|
||||
/** Revision id in PCI Config space */
|
||||
__u32 pci_rev;
|
||||
__u32 family;
|
||||
__u32 num_shader_engines;
|
||||
__u32 num_shader_arrays_per_engine;
|
||||
/* in KHz */
|
||||
__u32 gpu_counter_freq;
|
||||
__u64 max_engine_clock;
|
||||
__u64 max_memory_clock;
|
||||
/* cu information */
|
||||
__u32 cu_active_number;
|
||||
__u32 cu_ao_mask;
|
||||
__u32 cu_bitmap[4][4];
|
||||
/** Render backend pipe mask. One render backend is CB+DB. */
|
||||
__u32 enabled_rb_pipes_mask;
|
||||
__u32 num_rb_pipes;
|
||||
__u32 num_hw_gfx_contexts;
|
||||
__u32 _pad;
|
||||
__u64 ids_flags;
|
||||
/** Starting virtual address for UMDs. */
|
||||
__u64 virtual_address_offset;
|
||||
/** The maximum virtual address */
|
||||
__u64 virtual_address_max;
|
||||
/** Required alignment of virtual addresses. */
|
||||
__u32 virtual_address_alignment;
|
||||
/** Page table entry - fragment size */
|
||||
__u32 pte_fragment_size;
|
||||
__u32 gart_page_size;
|
||||
/** constant engine ram size*/
|
||||
__u32 ce_ram_size;
|
||||
/** video memory type info*/
|
||||
__u32 vram_type;
|
||||
/** video memory bit width*/
|
||||
__u32 vram_bit_width;
|
||||
/* vce harvesting instance */
|
||||
__u32 vce_harvest_config;
|
||||
};
|
||||
|
||||
struct drm_amdgpu_info_hw_ip {
|
||||
/** Version of h/w IP */
|
||||
__u32 hw_ip_version_major;
|
||||
__u32 hw_ip_version_minor;
|
||||
/** Capabilities */
|
||||
__u64 capabilities_flags;
|
||||
/** command buffer address start alignment*/
|
||||
__u32 ib_start_alignment;
|
||||
/** command buffer size alignment*/
|
||||
__u32 ib_size_alignment;
|
||||
/** Bitmask of available rings. Bit 0 means ring 0, etc. */
|
||||
__u32 available_rings;
|
||||
__u32 _pad;
|
||||
};
|
||||
|
||||
/*
|
||||
* Supported GPU families
|
||||
*/
|
||||
#define AMDGPU_FAMILY_UNKNOWN 0
|
||||
#define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */
|
||||
#define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */
|
||||
#define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */
|
||||
#define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */
|
||||
#define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,152 @@
|
||||
/*
|
||||
* Copyright 2005 Stephane Marchesin.
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef __NOUVEAU_DRM_H__
|
||||
#define __NOUVEAU_DRM_H__
|
||||
|
||||
#define DRM_NOUVEAU_EVENT_NVIF 0x80000000
|
||||
|
||||
#include "drm.h"
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define NOUVEAU_GEM_DOMAIN_CPU (1 << 0)
|
||||
#define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1)
|
||||
#define NOUVEAU_GEM_DOMAIN_GART (1 << 2)
|
||||
#define NOUVEAU_GEM_DOMAIN_MAPPABLE (1 << 3)
|
||||
#define NOUVEAU_GEM_DOMAIN_COHERENT (1 << 4)
|
||||
|
||||
#define NOUVEAU_GEM_TILE_COMP 0x00030000 /* nv50-only */
|
||||
#define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff00
|
||||
#define NOUVEAU_GEM_TILE_16BPP 0x00000001
|
||||
#define NOUVEAU_GEM_TILE_32BPP 0x00000002
|
||||
#define NOUVEAU_GEM_TILE_ZETA 0x00000004
|
||||
#define NOUVEAU_GEM_TILE_NONCONTIG 0x00000008
|
||||
|
||||
struct drm_nouveau_gem_info {
|
||||
__u32 handle;
|
||||
__u32 domain;
|
||||
__u64 size;
|
||||
__u64 offset;
|
||||
__u64 map_handle;
|
||||
__u32 tile_mode;
|
||||
__u32 tile_flags;
|
||||
};
|
||||
|
||||
struct drm_nouveau_gem_new {
|
||||
struct drm_nouveau_gem_info info;
|
||||
__u32 channel_hint;
|
||||
__u32 align;
|
||||
};
|
||||
|
||||
#define NOUVEAU_GEM_MAX_BUFFERS 1024
|
||||
struct drm_nouveau_gem_pushbuf_bo_presumed {
|
||||
__u32 valid;
|
||||
__u32 domain;
|
||||
__u64 offset;
|
||||
};
|
||||
|
||||
struct drm_nouveau_gem_pushbuf_bo {
|
||||
__u64 user_priv;
|
||||
__u32 handle;
|
||||
__u32 read_domains;
|
||||
__u32 write_domains;
|
||||
__u32 valid_domains;
|
||||
struct drm_nouveau_gem_pushbuf_bo_presumed presumed;
|
||||
};
|
||||
|
||||
#define NOUVEAU_GEM_RELOC_LOW (1 << 0)
|
||||
#define NOUVEAU_GEM_RELOC_HIGH (1 << 1)
|
||||
#define NOUVEAU_GEM_RELOC_OR (1 << 2)
|
||||
#define NOUVEAU_GEM_MAX_RELOCS 1024
|
||||
struct drm_nouveau_gem_pushbuf_reloc {
|
||||
__u32 reloc_bo_index;
|
||||
__u32 reloc_bo_offset;
|
||||
__u32 bo_index;
|
||||
__u32 flags;
|
||||
__u32 data;
|
||||
__u32 vor;
|
||||
__u32 tor;
|
||||
};
|
||||
|
||||
#define NOUVEAU_GEM_MAX_PUSH 512
|
||||
struct drm_nouveau_gem_pushbuf_push {
|
||||
__u32 bo_index;
|
||||
__u32 pad;
|
||||
__u64 offset;
|
||||
__u64 length;
|
||||
};
|
||||
|
||||
struct drm_nouveau_gem_pushbuf {
|
||||
__u32 channel;
|
||||
__u32 nr_buffers;
|
||||
__u64 buffers;
|
||||
__u32 nr_relocs;
|
||||
__u32 nr_push;
|
||||
__u64 relocs;
|
||||
__u64 push;
|
||||
__u32 suffix0;
|
||||
__u32 suffix1;
|
||||
__u64 vram_available;
|
||||
__u64 gart_available;
|
||||
};
|
||||
|
||||
#define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001
|
||||
#define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004
|
||||
struct drm_nouveau_gem_cpu_prep {
|
||||
__u32 handle;
|
||||
__u32 flags;
|
||||
};
|
||||
|
||||
struct drm_nouveau_gem_cpu_fini {
|
||||
__u32 handle;
|
||||
};
|
||||
|
||||
#define DRM_NOUVEAU_GETPARAM 0x00 /* deprecated */
|
||||
#define DRM_NOUVEAU_SETPARAM 0x01 /* deprecated */
|
||||
#define DRM_NOUVEAU_CHANNEL_ALLOC 0x02 /* deprecated */
|
||||
#define DRM_NOUVEAU_CHANNEL_FREE 0x03 /* deprecated */
|
||||
#define DRM_NOUVEAU_GROBJ_ALLOC 0x04 /* deprecated */
|
||||
#define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05 /* deprecated */
|
||||
#define DRM_NOUVEAU_GPUOBJ_FREE 0x06 /* deprecated */
|
||||
#define DRM_NOUVEAU_NVIF 0x07
|
||||
#define DRM_NOUVEAU_GEM_NEW 0x40
|
||||
#define DRM_NOUVEAU_GEM_PUSHBUF 0x41
|
||||
#define DRM_NOUVEAU_GEM_CPU_PREP 0x42
|
||||
#define DRM_NOUVEAU_GEM_CPU_FINI 0x43
|
||||
#define DRM_NOUVEAU_GEM_INFO 0x44
|
||||
|
||||
#define DRM_IOCTL_NOUVEAU_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, struct drm_nouveau_gem_new)
|
||||
#define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, struct drm_nouveau_gem_pushbuf)
|
||||
#define DRM_IOCTL_NOUVEAU_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_PREP, struct drm_nouveau_gem_cpu_prep)
|
||||
#define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct drm_nouveau_gem_cpu_fini)
|
||||
#define DRM_IOCTL_NOUVEAU_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info)
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __NOUVEAU_DRM_H__ */
|
||||
@@ -1754,8 +1754,14 @@ proc disk_read_write stdcall uses ebx esi edi, \
|
||||
mov eax, [numsectors]
|
||||
mov eax, [eax]
|
||||
; 2. The transfer length for SCSI_{READ,WRITE}10 commands can not be greater
|
||||
; than 0xFFFF, so split the request to slices with <= 0xFFFF sectors.
|
||||
max_sectors_at_time = 0xFFFF
|
||||
; than 0xFFFF sectors, but that is not the practical limit: the field size is
|
||||
; the only thing the standard bounds, while real sticks hang their firmware on
|
||||
; multi-megabyte single commands. The kernel disk cache asks for as much as
|
||||
; CACHE_MAX_ALLOC_SIZE (4 MB) in one call, i.e. 8192 sectors, and that is
|
||||
; exactly where such sticks stop answering and re-enumerate. Linux caps
|
||||
; usb-storage at 240 sectors (120 KB) for the same reason; do the same and
|
||||
; split larger requests into slices.
|
||||
max_sectors_at_time = 240
|
||||
.split:
|
||||
push eax ; .length_rest
|
||||
cmp eax, max_sectors_at_time
|
||||
|
||||
@@ -0,0 +1,188 @@
|
||||
/*
|
||||
* Copyright (C) 2009 Francisco Jerez.
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining
|
||||
* a copy of this software and associated documentation files (the
|
||||
* "Software"), to deal in the Software without restriction, including
|
||||
* without limitation the rights to use, copy, modify, merge, publish,
|
||||
* distribute, sublicense, and/or sell copies of the Software, and to
|
||||
* permit persons to whom the Software is furnished to do so, subject to
|
||||
* the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the
|
||||
* next paragraph) shall be included in all copies or substantial
|
||||
* portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
|
||||
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
|
||||
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
|
||||
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
|
||||
#include <drm/drm_encoder_slave.h>
|
||||
|
||||
/**
|
||||
* drm_i2c_encoder_init - Initialize an I2C slave encoder
|
||||
* @dev: DRM device.
|
||||
* @encoder: Encoder to be attached to the I2C device. You aren't
|
||||
* required to have called drm_encoder_init() before.
|
||||
* @adap: I2C adapter that will be used to communicate with
|
||||
* the device.
|
||||
* @info: Information that will be used to create the I2C device.
|
||||
* Required fields are @addr and @type.
|
||||
*
|
||||
* Create an I2C device on the specified bus (the module containing its
|
||||
* driver is transparently loaded) and attach it to the specified
|
||||
* &drm_encoder_slave. The @slave_funcs field will be initialized with
|
||||
* the hooks provided by the slave driver.
|
||||
*
|
||||
* If @info->platform_data is non-NULL it will be used as the initial
|
||||
* slave config.
|
||||
*
|
||||
* Returns 0 on success or a negative errno on failure, in particular,
|
||||
* -ENODEV is returned when no matching driver is found.
|
||||
*/
|
||||
int drm_i2c_encoder_init(struct drm_device *dev,
|
||||
struct drm_encoder_slave *encoder,
|
||||
struct i2c_adapter *adap,
|
||||
const struct i2c_board_info *info)
|
||||
{
|
||||
struct module *module = NULL;
|
||||
struct i2c_client *client;
|
||||
struct drm_i2c_encoder_driver *encoder_drv;
|
||||
int err = 0;
|
||||
|
||||
request_module("%s%s", I2C_MODULE_PREFIX, info->type);
|
||||
|
||||
client = i2c_new_device(adap, info);
|
||||
if (!client) {
|
||||
err = -ENOMEM;
|
||||
goto fail;
|
||||
}
|
||||
|
||||
if (!client->dev.driver) {
|
||||
err = -ENODEV;
|
||||
goto fail_unregister;
|
||||
}
|
||||
|
||||
module = client->dev.driver->owner;
|
||||
if (!try_module_get(module)) {
|
||||
err = -ENODEV;
|
||||
goto fail_unregister;
|
||||
}
|
||||
|
||||
encoder->bus_priv = client;
|
||||
|
||||
encoder_drv = to_drm_i2c_encoder_driver(to_i2c_driver(client->dev.driver));
|
||||
|
||||
err = encoder_drv->encoder_init(client, dev, encoder);
|
||||
if (err)
|
||||
goto fail_module_put;
|
||||
|
||||
if (info->platform_data)
|
||||
encoder->slave_funcs->set_config(&encoder->base,
|
||||
info->platform_data);
|
||||
|
||||
return 0;
|
||||
|
||||
fail_module_put:
|
||||
module_put(module);
|
||||
fail_unregister:
|
||||
i2c_unregister_device(client);
|
||||
fail:
|
||||
return err;
|
||||
}
|
||||
EXPORT_SYMBOL(drm_i2c_encoder_init);
|
||||
|
||||
/**
|
||||
* drm_i2c_encoder_destroy - Unregister the I2C device backing an encoder
|
||||
* @drm_encoder: Encoder to be unregistered.
|
||||
*
|
||||
* This should be called from the @destroy method of an I2C slave
|
||||
* encoder driver once I2C access is no longer needed.
|
||||
*/
|
||||
void drm_i2c_encoder_destroy(struct drm_encoder *drm_encoder)
|
||||
{
|
||||
struct drm_encoder_slave *encoder = to_encoder_slave(drm_encoder);
|
||||
struct i2c_client *client = drm_i2c_encoder_get_client(drm_encoder);
|
||||
struct module *module = client->dev.driver->owner;
|
||||
|
||||
i2c_unregister_device(client);
|
||||
encoder->bus_priv = NULL;
|
||||
|
||||
module_put(module);
|
||||
}
|
||||
EXPORT_SYMBOL(drm_i2c_encoder_destroy);
|
||||
|
||||
/*
|
||||
* Wrapper fxns which can be plugged in to drm_encoder_helper_funcs:
|
||||
*/
|
||||
|
||||
static inline const struct drm_encoder_slave_funcs *
|
||||
get_slave_funcs(struct drm_encoder *enc)
|
||||
{
|
||||
return to_encoder_slave(enc)->slave_funcs;
|
||||
}
|
||||
|
||||
void drm_i2c_encoder_dpms(struct drm_encoder *encoder, int mode)
|
||||
{
|
||||
get_slave_funcs(encoder)->dpms(encoder, mode);
|
||||
}
|
||||
EXPORT_SYMBOL(drm_i2c_encoder_dpms);
|
||||
|
||||
bool drm_i2c_encoder_mode_fixup(struct drm_encoder *encoder,
|
||||
const struct drm_display_mode *mode,
|
||||
struct drm_display_mode *adjusted_mode)
|
||||
{
|
||||
if (!get_slave_funcs(encoder)->mode_fixup)
|
||||
return true;
|
||||
|
||||
return get_slave_funcs(encoder)->mode_fixup(encoder, mode, adjusted_mode);
|
||||
}
|
||||
EXPORT_SYMBOL(drm_i2c_encoder_mode_fixup);
|
||||
|
||||
void drm_i2c_encoder_prepare(struct drm_encoder *encoder)
|
||||
{
|
||||
drm_i2c_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
|
||||
}
|
||||
EXPORT_SYMBOL(drm_i2c_encoder_prepare);
|
||||
|
||||
void drm_i2c_encoder_commit(struct drm_encoder *encoder)
|
||||
{
|
||||
drm_i2c_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
|
||||
}
|
||||
EXPORT_SYMBOL(drm_i2c_encoder_commit);
|
||||
|
||||
void drm_i2c_encoder_mode_set(struct drm_encoder *encoder,
|
||||
struct drm_display_mode *mode,
|
||||
struct drm_display_mode *adjusted_mode)
|
||||
{
|
||||
get_slave_funcs(encoder)->mode_set(encoder, mode, adjusted_mode);
|
||||
}
|
||||
EXPORT_SYMBOL(drm_i2c_encoder_mode_set);
|
||||
|
||||
enum drm_connector_status drm_i2c_encoder_detect(struct drm_encoder *encoder,
|
||||
struct drm_connector *connector)
|
||||
{
|
||||
return get_slave_funcs(encoder)->detect(encoder, connector);
|
||||
}
|
||||
EXPORT_SYMBOL(drm_i2c_encoder_detect);
|
||||
|
||||
void drm_i2c_encoder_save(struct drm_encoder *encoder)
|
||||
{
|
||||
get_slave_funcs(encoder)->save(encoder);
|
||||
}
|
||||
EXPORT_SYMBOL(drm_i2c_encoder_save);
|
||||
|
||||
void drm_i2c_encoder_restore(struct drm_encoder *encoder)
|
||||
{
|
||||
get_slave_funcs(encoder)->restore(encoder);
|
||||
}
|
||||
EXPORT_SYMBOL(drm_i2c_encoder_restore);
|
||||
+743
-49
File diff suppressed because it is too large.
Load diff
@@ -2405,11 +2405,12 @@ fat_Write:
|
||||
; hd_extend_file can return three error codes: FAT table error, device error or disk full.
|
||||
; First two cases are fatal errors, in third case we may write some data
|
||||
cmp al, ERROR_DISK_FULL
|
||||
jnz @f
|
||||
jnz .noWrite
|
||||
; correct number of bytes to write
|
||||
mov ecx, [edi+28]
|
||||
cmp ecx, ebx
|
||||
ja .length_ok
|
||||
.noWrite:
|
||||
push 0
|
||||
.ret:
|
||||
pop eax eax eax ecx ecx
|
||||
|
||||
@@ -118,7 +118,7 @@ SS_MORETOCOME = 0x4000
|
||||
SS_BLOCKED = 0x8000
|
||||
|
||||
|
||||
SOCKET_BUFFER_SIZE = 4096*8 ; must be 4096*(power of 2) where 'power of 2' is at least 8
|
||||
SOCKET_BUFFER_SIZE = 4096*32 ; must be 4096*(power of 2) where 'power of 2' is at least 8
|
||||
MAX_backlog = 20 ; maximum backlog for stream sockets
|
||||
|
||||
; Error Codes
|
||||
|
||||
@@ -181,6 +181,7 @@ con_cls
|
||||
con_get_cursor_pos
|
||||
con_set_cursor_pos
|
||||
;____TIME____
|
||||
clock
|
||||
mktime
|
||||
time
|
||||
localtime
|
||||
|
||||
@@ -1,11 +1,10 @@
|
||||
#ifndef _TIME_H_
|
||||
#define _TIME_H_
|
||||
|
||||
#include <sys/ksys.h>
|
||||
#include <stddef.h>
|
||||
|
||||
typedef unsigned long int clock_t;
|
||||
typedef unsigned long int time_t;
|
||||
#define clock() _ksys_get_clock()
|
||||
#define CLOCKS_PER_SEC 100
|
||||
|
||||
#pragma pack(push, 1)
|
||||
@@ -22,6 +21,7 @@ struct tm {
|
||||
};
|
||||
#pragma pack(pop)
|
||||
|
||||
DLLAPI clock_t clock(void);
|
||||
DLLAPI time_t mktime(struct tm* timeptr);
|
||||
DLLAPI time_t time(time_t* timer);
|
||||
DLLAPI struct tm* localtime(const time_t* timer);
|
||||
|
||||
@@ -119,6 +119,7 @@
|
||||
#include "math/sinh.c"
|
||||
#include "math/tanh.c"
|
||||
|
||||
#include "time/clock.c"
|
||||
#include "time/asctime.c"
|
||||
#include "time/difftime.c"
|
||||
#include "time/localtime.c"
|
||||
@@ -338,6 +339,7 @@ ksys_dll_t EXPORTS[] = {
|
||||
{ "con_cls", &con_cls },
|
||||
{ "con_get_cursor_pos", &con_get_cursor_pos },
|
||||
{ "con_set_cursor_pos", &con_set_cursor_pos },
|
||||
{ "clock", &clock },
|
||||
{ "mktime", &mktime },
|
||||
{ "time", &time },
|
||||
{ "localtime", &localtime },
|
||||
|
||||
@@ -0,0 +1,7 @@
|
||||
#include <time.h>
|
||||
#include <sys/ksys.h>
|
||||
|
||||
clock_t clock(void)
|
||||
{
|
||||
return _ksys_get_tick_count();
|
||||
}
|
||||
@@ -1178,17 +1178,18 @@ proc png_colorspace_set_gamma, png_ptr:dword, colorspace:dword, gAMA:dword
|
||||
; In 1.6.0 this test replaces the ones in pngrutil.c, in the gAMA chunk
|
||||
; handling code, which only required the value to be >0.
|
||||
|
||||
png_debug 1, 'in png_colorspace_set_gamma'
|
||||
; charp errmsg;
|
||||
|
||||
; if (gAMA < 16 || gAMA > 625000000)
|
||||
; errmsg = "gamma value out of range";
|
||||
|
||||
;# ifdef PNG_READ_gAMA_SUPPORTED
|
||||
if PNG_READ_gAMA_SUPPORTED eq 1
|
||||
; Allow the application to set the gamma value more than once
|
||||
; else if ((png_ptr->mode & PNG_IS_READ_STRUCT) != 0 &&
|
||||
; (colorspace->flags & PNG_COLORSPACE_FROM_gAMA) != 0)
|
||||
; errmsg = "duplicate";
|
||||
;# endif
|
||||
end if
|
||||
|
||||
; Do nothing if the colorspace is already invalid
|
||||
; else if ((colorspace->flags & PNG_COLORSPACE_INVALID) != 0)
|
||||
|
||||
@@ -161,8 +161,7 @@ proc png_set_gAMA_fixed uses eax edi esi, png_ptr:dword, info_ptr:dword, file_ga
|
||||
or esi,esi
|
||||
jz .end_f ;if (..== 0 || ..== 0) return
|
||||
|
||||
mov eax,esi
|
||||
add eax,png_info_def.colorspace
|
||||
lea eax,[esi+png_info_def.colorspace]
|
||||
stdcall png_colorspace_set_gamma, edi, eax, [file_gamma]
|
||||
stdcall png_colorspace_sync_info, edi, esi
|
||||
.end_f:
|
||||
@@ -593,8 +592,10 @@ endp
|
||||
|
||||
;void (png_structrp png_ptr, png_inforp info_ptr, png_colorp palette, int num_palette)
|
||||
align 4
|
||||
proc png_set_PLTE uses eax edi esi, png_ptr:dword, info_ptr:dword, palette:dword, num_palette:dword
|
||||
; uint_32 max_palette_length;
|
||||
proc png_set_PLTE uses eax ecx edi esi, png_ptr:dword, info_ptr:dword, palette:dword, num_palette:dword
|
||||
locals
|
||||
max_palette_length rd 1 ;uint_32
|
||||
endl
|
||||
|
||||
png_debug1 1, 'in %s storage function', 'PLTE'
|
||||
|
||||
@@ -605,31 +606,53 @@ proc png_set_PLTE uses eax edi esi, png_ptr:dword, info_ptr:dword, palette:dword
|
||||
or esi,esi
|
||||
jz .end_f ;if (..==0 || ..==0) return
|
||||
|
||||
; max_palette_length = (info_ptr->color_type == PNG_COLOR_TYPE_PALETTE) ?
|
||||
; (1 << info_ptr->bit_depth) : PNG_MAX_PALETTE_LENGTH;
|
||||
;max_palette_length = (..==..) ? .. : ..
|
||||
cmp byte[esi+png_info_def.color_type],PNG_COLOR_TYPE_PALETTE
|
||||
jne @f
|
||||
xor eax,eax
|
||||
inc eax
|
||||
movzx ecx,byte[esi+png_info_def.bit_depth]
|
||||
shl eax,cl
|
||||
mov [max_palette_length],eax
|
||||
jmp .end0
|
||||
@@:
|
||||
mov [max_palette_length],PNG_MAX_PALETTE_LENGTH
|
||||
.end0:
|
||||
|
||||
; if (num_palette < 0 || num_palette > (int) max_palette_length)
|
||||
; {
|
||||
; if (info_ptr->color_type == PNG_COLOR_TYPE_PALETTE)
|
||||
; png_error(png_ptr, "Invalid palette length");
|
||||
;if (..<0 || ..>..)
|
||||
cmp [num_palette],0
|
||||
jl @f
|
||||
mov eax,[max_palette_length]
|
||||
cmp [num_palette],eax
|
||||
jle .end1
|
||||
@@:
|
||||
cmp byte[edi+png_struct.color_type],PNG_COLOR_TYPE_PALETTE ;if (..==..)
|
||||
jne @f
|
||||
png_error edi, 'Invalid palette length'
|
||||
jmp .end1
|
||||
@@: ;else
|
||||
png_warning edi, 'Invalid palette length'
|
||||
jmp .end_f
|
||||
.end1:
|
||||
|
||||
; else
|
||||
; {
|
||||
; png_warning(png_ptr, "Invalid palette length");
|
||||
|
||||
; return;
|
||||
; }
|
||||
; }
|
||||
|
||||
; if ((num_palette > 0 && palette == NULL) ||
|
||||
; (num_palette == 0
|
||||
cmp [num_palette],0
|
||||
jle @f
|
||||
cmp [palette],0
|
||||
je .end2
|
||||
@@:
|
||||
cmp [num_palette],0
|
||||
jne .end3
|
||||
;if ((..>0 && ..==0) || (..==0
|
||||
if PNG_MNG_FEATURES_SUPPORTED eq 1
|
||||
; && (png_ptr->mng_features_permitted & PNG_FLAG_MNG_EMPTY_PLTE) == 0
|
||||
; && (.. & PNG_FLAG_MNG_EMPTY_PLTE) == 0
|
||||
mov eax,[edi+png_struct.mng_features_permitted]
|
||||
and eax,PNG_FLAG_MNG_EMPTY_PLTE
|
||||
jnz .end3
|
||||
end if
|
||||
; ))
|
||||
; {
|
||||
; png_error(png_ptr, "Invalid palette");
|
||||
; }
|
||||
;))
|
||||
.end2:
|
||||
png_error edi, 'Invalid palette'
|
||||
.end3:
|
||||
|
||||
; It may not actually be necessary to set png_ptr->palette here;
|
||||
; we do it for backward compatibility with the way the png_handle_tRNS
|
||||
@@ -644,14 +667,26 @@ end if
|
||||
; of num_palette entries, in case of an invalid PNG file or incorrect
|
||||
; call to png_set_PLTE() with too-large sample values.
|
||||
|
||||
; png_ptr->palette = png_calloc(png_ptr,
|
||||
; PNG_MAX_PALETTE_LENGTH * (sizeof (png_color)));
|
||||
stdcall png_calloc, edi, PNG_MAX_PALETTE_LENGTH*sizeof.png_color
|
||||
mov [edi+png_struct.palette],eax
|
||||
|
||||
; if (num_palette > 0)
|
||||
; memcpy(png_ptr->palette, palette, num_palette * (sizeof (png_color)));
|
||||
;if (..>0)
|
||||
cmp [num_palette],0
|
||||
jle @f
|
||||
push esi edi
|
||||
mov ecx,[num_palette]
|
||||
imul ecx,sizeof.png_color
|
||||
mov esi,[palette]
|
||||
mov edi,eax
|
||||
rep movsb ;memcpy(png_ptr->palette, palette, ...
|
||||
pop edi esi
|
||||
@@:
|
||||
mov eax,[edi+png_struct.palette]
|
||||
mov [esi+png_info_def.palette],eax
|
||||
; info_ptr->num_palette = png_ptr->num_palette = (uint_16)num_palette;
|
||||
|
||||
mov eax,[num_palette]
|
||||
mov [edi+png_struct.num_palette],ax
|
||||
mov [esi+png_info_def.num_palette],ax
|
||||
|
||||
or dword[esi+png_info_def.free_me], PNG_FREE_PLTE
|
||||
or dword[esi+png_info_def.valid], PNG_INFO_PLTE
|
||||
|
||||
@@ -1925,6 +1925,7 @@ locals
|
||||
aindex dd 0 ;int ;= 0
|
||||
y dd ? ;uint_32 ;= image->height
|
||||
endl
|
||||
png_debug 1, 'in png_write_image_16bit'
|
||||
mov ebx,[argument]
|
||||
mov [display],ebx
|
||||
mov edx,[ebx+png_image_write_control.image]
|
||||
@@ -2118,6 +2119,7 @@ locals
|
||||
y dd ? ;uint_32 ;= image->height
|
||||
component dd ? ;uint_32
|
||||
endl
|
||||
png_debug 1, 'in png_write_image_8bit'
|
||||
mov ebx,[argument]
|
||||
mov [display],ebx
|
||||
mov edx,[ebx+png_image_write_control.image]
|
||||
@@ -2257,9 +2259,11 @@ locals
|
||||
afirst dd 0
|
||||
bgr dd 0
|
||||
num_trans dd 0
|
||||
i dd ?
|
||||
palette rb 256*sizeof.png_color
|
||||
tRNS rb 256 ;byte[]
|
||||
endl
|
||||
png_debug 1, 'in png_image_set_PLTE'
|
||||
pushad
|
||||
mov edx,[display]
|
||||
mov ebx,[edx+png_image_write_control.image]
|
||||
@@ -2296,30 +2300,33 @@ if PNG_FORMAT_BGR_SUPPORTED eq 1
|
||||
@@:
|
||||
end if
|
||||
|
||||
; int i;
|
||||
|
||||
xor eax,eax
|
||||
mov ecx,(256*sizeof.png_color)/4
|
||||
mov edi,ebp
|
||||
sub edi,256+256*sizeof.png_color
|
||||
lea edi,[ebp-256-256*sizeof.png_color]
|
||||
rep stosd ;memset(palette, 0, ...
|
||||
not eax
|
||||
mov ecx,256/4
|
||||
;;mov edi,ebp ;if 'tRNS' after 'palette' this code can be comment
|
||||
;;sub edi,256
|
||||
;lea edi,[ebp-256] ;if 'tRNS' after 'palette' this code can be comment
|
||||
rep stosd ;memset(tRNS, 255, ...
|
||||
|
||||
|
||||
; for (i=num_trans=0; i<entries; ++i)
|
||||
; {
|
||||
mov [i],0
|
||||
lea edx,[ebp-256] ;edx=&tRNS
|
||||
lea edi,[edx-256*sizeof.png_color]
|
||||
align 4
|
||||
.cycle0: ;for (i=num_trans=0; i<entries; ++i)
|
||||
; This gets automatically converted to sRGB with reversal of the
|
||||
; pre-multiplication if the color-map has an alpha channel.
|
||||
|
||||
; if ((format & PNG_FORMAT_FLAG_LINEAR) != 0)
|
||||
; {
|
||||
; png_const_uint_16p entry = cmap;
|
||||
|
||||
; entry += i * channels;
|
||||
;if ((..&..) != 0)
|
||||
mov eax,[format]
|
||||
and eax,PNG_FORMAT_FLAG_LINEAR
|
||||
or eax,eax
|
||||
jz .end0
|
||||
mov esi,[cmap] ;esi=entry uint_16p
|
||||
mov eax,[channels]
|
||||
mov ecx,eax
|
||||
imul eax,[i]
|
||||
add esi,eax ;+=i*channels;
|
||||
|
||||
; if ((channels & 1) != 0) /* no alpha */
|
||||
; {
|
||||
@@ -2369,46 +2376,86 @@ end if
|
||||
; palette[i].blue = palette[i].red = palette[i].green =
|
||||
; png_unpremultiply(entry[afirst], alpha, reciprocal);
|
||||
; }
|
||||
; }
|
||||
jmp .end1
|
||||
.end0: ;else Color-map has sRGB values
|
||||
mov esi,[cmap] ;esi=entry
|
||||
mov eax,[channels]
|
||||
mov ecx,eax
|
||||
imul eax,[i]
|
||||
add esi,eax ;+=i*channels;
|
||||
|
||||
; else /* Color-map has sRGB values */
|
||||
; {
|
||||
; bytep entry = cmap;
|
||||
;switch (channels)
|
||||
cmp ecx,4
|
||||
jne .end2
|
||||
mov eax,[afirst]
|
||||
or eax,eax
|
||||
jz @f
|
||||
xor eax,eax
|
||||
jmp .end3
|
||||
@@:
|
||||
mov eax,3
|
||||
.end3:
|
||||
mov al,byte[esi+eax]
|
||||
mov byte[edx],al ;tRNS[i] = entry[afirst ? 0 : 3]
|
||||
cmp al,255 ;if (..<..)
|
||||
je @f
|
||||
mov eax,[i]
|
||||
inc eax
|
||||
mov [num_trans],eax
|
||||
@@:
|
||||
dec ecx ; FALL THROUGH
|
||||
.end2:
|
||||
cmp ecx,3
|
||||
jne @f
|
||||
add esi,[afirst]
|
||||
mov eax,[bgr]
|
||||
xor eax,2
|
||||
lea eax,[esi+eax]
|
||||
mov al,byte[eax]
|
||||
stosb ;palette[i].blue
|
||||
|
||||
; entry += i * channels;
|
||||
lea eax,[esi+1]
|
||||
mov al,byte[eax]
|
||||
stosb ;palette[i].green
|
||||
|
||||
; switch (channels)
|
||||
; {
|
||||
; case 4:
|
||||
; tRNS[i] = entry[afirst ? 0 : 3];
|
||||
; if (tRNS[i] < 255)
|
||||
; num_trans = i+1;
|
||||
; /* FALL THROUGH */
|
||||
; case 3:
|
||||
; palette[i].blue = entry[afirst + (2 ^ bgr)];
|
||||
; palette[i].green = entry[afirst + 1];
|
||||
; palette[i].red = entry[afirst + bgr];
|
||||
; break;
|
||||
|
||||
; case 2:
|
||||
; tRNS[i] = entry[1 ^ afirst];
|
||||
; if (tRNS[i] < 255)
|
||||
; num_trans = i+1;
|
||||
; /* FALL THROUGH */
|
||||
; case 1:
|
||||
; palette[i].blue = palette[i].red = palette[i].green =
|
||||
; entry[afirst];
|
||||
; break;
|
||||
|
||||
; default:
|
||||
; break;
|
||||
; }
|
||||
; }
|
||||
; }
|
||||
mov eax,[bgr]
|
||||
lea eax,[esi+eax]
|
||||
mov al,byte[eax]
|
||||
stosb ;palette[i].red
|
||||
jmp .end1
|
||||
@@:
|
||||
cmp ecx,2
|
||||
jne @f
|
||||
xor eax,eax
|
||||
inc eax
|
||||
xor eax,[afirst]
|
||||
mov al,byte[esi+eax]
|
||||
mov byte[edx],al ;tRNS[i] = entry[1 ^ afirst]
|
||||
cmp al,255 ;if (..<..)
|
||||
je @f
|
||||
mov eax,[i]
|
||||
inc eax
|
||||
mov [num_trans],eax
|
||||
@@:
|
||||
dec ecx; FALL THROUGH
|
||||
@@:
|
||||
cmp ecx,1
|
||||
jne .end1
|
||||
mov eax,[afirst]
|
||||
mov al,byte[esi+eax]
|
||||
stosb
|
||||
stosb
|
||||
stosb
|
||||
.end1:
|
||||
inc edx
|
||||
mov eax,[entries]
|
||||
inc [i]
|
||||
cmp [i],eax
|
||||
jl .cycle0
|
||||
.cycle0end:
|
||||
|
||||
mov ecx,[ebx+png_image.opaque]
|
||||
mov eax,ebp
|
||||
sub eax,256+256*sizeof.png_color
|
||||
lea eax,[ebp-256-256*sizeof.png_color]
|
||||
stdcall png_set_PLTE, [ecx+png_control.png_ptr], [ecx+png_control.info_ptr], eax, [entries]
|
||||
|
||||
cmp dword[num_trans],0
|
||||
@@ -2820,9 +2867,26 @@ png_debug1 2, 'IDAT compress all len = %d', [len]
|
||||
mov edi,[buf_f]
|
||||
mov esi,[buf]
|
||||
|
||||
cmp eax,PNG_COLOR_TYPE_PALETTE
|
||||
je .cycle7
|
||||
cmp eax,PNG_COLOR_TYPE_RGB
|
||||
je .cycle0
|
||||
cmp eax,PNG_COLOR_TYPE_RGB_ALPHA
|
||||
je .cycle5
|
||||
|
||||
.cycle7: ;8 bit image palette
|
||||
cmp edx,1
|
||||
jl .cycle0end
|
||||
mov ecx,ebx
|
||||
xor al,al
|
||||
stosb ;insert filter (0 - none)
|
||||
align 4
|
||||
rep movsb
|
||||
dec edx
|
||||
jmp .cycle7
|
||||
.cycle7end:
|
||||
jmp .cycle5end
|
||||
|
||||
.cycle0: ;24 bit image
|
||||
cmp edx,1
|
||||
jl .cycle0end
|
||||
|
||||
@@ -1063,8 +1063,8 @@ align 4
|
||||
proc png_write_PLTE, png_ptr:dword, palette:dword, num_pal:dword
|
||||
locals
|
||||
;max_palette_length dd ? ;uint_32
|
||||
i dd ?
|
||||
pal_ptr dd ? ;png_const_colorp
|
||||
;i dd ?
|
||||
;pal_ptr dd ? ;png_const_colorp
|
||||
buf rb 3 ;byte[3]
|
||||
endl
|
||||
png_debug 1, 'in png_write_PLTE'
|
||||
@@ -1085,16 +1085,16 @@ pushad
|
||||
;mov [max_palette_length],eax
|
||||
.end0:
|
||||
|
||||
if PNG_MNG_FEATURES_SUPPORTED eq 1
|
||||
cmp [num_pal],eax
|
||||
jg @f
|
||||
if PNG_MNG_FEATURES_SUPPORTED eq 1
|
||||
mov eax,[edi+png_struct.mng_features_permitted]
|
||||
and eax,PNG_FLAG_MNG_EMPTY_PLTE
|
||||
jnz .end1
|
||||
end if
|
||||
cmp [num_pal],0
|
||||
jne .end1
|
||||
@@:
|
||||
end if
|
||||
|
||||
cmp byte[edi+png_struct.color_type],PNG_COLOR_TYPE_PALETTE ;if (..==..)
|
||||
jne @f
|
||||
@@ -1118,31 +1118,24 @@ end if
|
||||
|
||||
imul eax,3
|
||||
stdcall png_write_chunk_header, edi, png_PLTE, eax
|
||||
if PNG_POINTER_INDEXING_SUPPORTED eq 1
|
||||
|
||||
; for (i = 0, pal_ptr = palette; i < num_pal; i++, pal_ptr++)
|
||||
; {
|
||||
; buf[0] = pal_ptr->red;
|
||||
; buf[1] = pal_ptr->green;
|
||||
; buf[2] = pal_ptr->blue;
|
||||
; png_write_chunk_data(png_ptr, buf, (png_size_t)3);
|
||||
; }
|
||||
mov ecx,[num_pal]
|
||||
or ecx,ecx
|
||||
jz .cycle0end
|
||||
mov esi,[palette]
|
||||
lea ebx,[ebp-3] ;ebx = &buf
|
||||
align 4
|
||||
.cycle0: ;for (;;)
|
||||
lodsb
|
||||
mov [ebx],al
|
||||
lodsb
|
||||
mov [ebx+1],al
|
||||
lodsb
|
||||
mov [ebx+2],al
|
||||
stdcall png_write_chunk_data, edi, ebx, 3
|
||||
loop .cycle0
|
||||
.cycle0end:
|
||||
|
||||
else
|
||||
; This is a little slower but some buggy compilers need to do this
|
||||
; instead
|
||||
|
||||
; pal_ptr=palette;
|
||||
|
||||
; for (i = 0; i < num_pal; i++)
|
||||
; {
|
||||
; buf[0] = pal_ptr[i].red;
|
||||
; buf[1] = pal_ptr[i].green;
|
||||
; buf[2] = pal_ptr[i].blue;
|
||||
; png_write_chunk_data(png_ptr, buf, (png_size_t)3);
|
||||
; }
|
||||
|
||||
end if
|
||||
stdcall png_write_chunk_end, edi
|
||||
or dword[edi+png_struct.mode], PNG_HAVE_PLTE
|
||||
.end_f:
|
||||
|
||||
@@ -1163,7 +1163,7 @@ local .l1
|
||||
|
||||
;;================================================================================================;;
|
||||
align 4
|
||||
proc img.encode.png uses ebx edx, _img:dword, _common:dword, _specific:dword
|
||||
proc img.encode.png uses ebx edx edi, _img:dword, _common:dword, _specific:dword
|
||||
;;------------------------------------------------------------------------------------------------;;
|
||||
;? Encode image into raw data in png format ;;
|
||||
;;------------------------------------------------------------------------------------------------;;
|
||||
@@ -1175,12 +1175,15 @@ proc img.encode.png uses ebx edx, _img:dword, _common:dword, _specific:dword
|
||||
;< ecx = error code / the size of encoded data ;;
|
||||
;;================================================================================================;;
|
||||
locals
|
||||
colormap dd 0
|
||||
encoded_file rd 1
|
||||
encoded_file_size rd 1
|
||||
simag png_image
|
||||
endl
|
||||
mov ebx,[_img]
|
||||
mov eax,[ebx+Image.Type]
|
||||
cmp eax,Image.bpp8i
|
||||
je @f
|
||||
cmp eax,Image.bpp24
|
||||
je @f
|
||||
cmp eax,Image.bpp32
|
||||
@@ -1192,16 +1195,27 @@ endl
|
||||
mov dword[edx+png_image.version],PNG_IMAGE_VERSION
|
||||
mov ecx,[ebx+Image.Width]
|
||||
mov [edx+png_image.width],ecx ;Image width in pixels (columns)
|
||||
cmp eax,Image.bpp8i
|
||||
jne @f
|
||||
mov dword[edx+png_image.format],PNG_FORMAT_RGBA_COLORMAP
|
||||
mov eax,ecx
|
||||
imul eax,[ebx+Image.Height]
|
||||
add eax,[ebx+Image.Data]
|
||||
add [colormap],eax
|
||||
stdcall get_pallete_colors,eax
|
||||
mov dword[edx+png_image.colormap_entries],eax
|
||||
jmp .init
|
||||
@@:
|
||||
cmp eax,Image.bpp24
|
||||
jne @f
|
||||
mov dword[edx+png_image.format],PNG_FORMAT_RGB
|
||||
imul ecx,3
|
||||
@@:
|
||||
cmp eax,Image.bpp32
|
||||
jne @f
|
||||
jne .init
|
||||
mov dword[edx+png_image.format],PNG_FORMAT_RGBA
|
||||
shl ecx,2
|
||||
@@:
|
||||
.init:
|
||||
mov eax,[ebx+Image.Height]
|
||||
mov [edx+png_image.height],eax ;Image height in pixels (rows)
|
||||
;mov dword[edx+png_image.flags],PNG_IMAGE_FLAG_???
|
||||
@@ -1221,7 +1235,7 @@ endl
|
||||
@@:
|
||||
mov [encoded_file],eax
|
||||
lea edi,[edx-4]
|
||||
stdcall png_image_write_to_memory, edx,eax,edi,0,[ebx+Image.Data],ecx,0
|
||||
stdcall png_image_write_to_memory, edx,eax,edi,0,[ebx+Image.Data],ecx,[colormap]
|
||||
mov eax,[encoded_file]
|
||||
mov ecx,[encoded_file_size]
|
||||
jmp .quit
|
||||
@@ -1231,3 +1245,31 @@ endl
|
||||
.quit:
|
||||
ret
|
||||
endp
|
||||
|
||||
|
||||
|
||||
;;================================================================================================;;
|
||||
align 4
|
||||
proc get_pallete_colors uses ecx edi, palette:dword
|
||||
;;------------------------------------------------------------------------------------------------;;
|
||||
;? Determine the palette size. Locate two adjacent zero-value colors; ;;
|
||||
;? this marks the end of the palette. ;;
|
||||
;;------------------------------------------------------------------------------------------------;;
|
||||
mov ecx,256-1
|
||||
mov edi,[palette]
|
||||
xor eax,eax
|
||||
@@:
|
||||
repne scasd
|
||||
or ecx,ecx
|
||||
jz .max_pal
|
||||
cmp [edi],eax ;second color check
|
||||
jne @b ;find again
|
||||
sub edi,[palette]
|
||||
shr edi,2
|
||||
mov eax,edi
|
||||
jmp @f
|
||||
.max_pal:
|
||||
mov eax,256
|
||||
@@:
|
||||
ret
|
||||
endp
|
||||
+262
-263
@@ -1,263 +1,262 @@
|
||||
driverlist:
|
||||
db 'RTL8139',0 ; Realtek 8139
|
||||
dd 0x813910ec
|
||||
dd 0x813810ec
|
||||
dd 0x12111113
|
||||
dd 0x13601500
|
||||
dd 0x13604033
|
||||
dd 0x13001186
|
||||
dd 0x13401186
|
||||
dd 0xab0613d1
|
||||
dd 0xa1171259
|
||||
dd 0xa11e1259
|
||||
dd 0xab0614ea
|
||||
dd 0xab0714ea
|
||||
dd 0x123411db
|
||||
dd 0x91301432
|
||||
dd 0x101202ac
|
||||
dd 0x0106018a
|
||||
dd 0x1211126c
|
||||
dd 0x81391743
|
||||
dd 0x8139021b
|
||||
dd 0x0 ; end
|
||||
|
||||
db 'RTL8029',0 ; Realtek 8029 (PCI NE2000)
|
||||
dd 0x802910ec
|
||||
dd 0x0
|
||||
|
||||
db 'I8255X',0 ; Intel eepro100
|
||||
dd 0x10298086
|
||||
dd 0x10308086
|
||||
;dd 0x10318086
|
||||
;dd 0x10328086
|
||||
;dd 0x10338086
|
||||
;dd 0x10348086
|
||||
;dd 0x10388086
|
||||
dd 0x10398086
|
||||
;dd 0x103A8086
|
||||
;dd 0x103B8086
|
||||
;dd 0x103C8086
|
||||
;dd 0x103D8086
|
||||
;dd 0x103E8086
|
||||
;dd 0x10508086
|
||||
;dd 0x10518086
|
||||
;dd 0x10528086
|
||||
;dd 0x10538086
|
||||
;dd 0x10548086
|
||||
;dd 0x10558086
|
||||
;dd 0x10568086
|
||||
;dd 0x10578086
|
||||
;dd 0x10598086
|
||||
;dd 0x10648086
|
||||
;dd 0x10658086
|
||||
;dd 0x10668086
|
||||
;dd 0x10678086
|
||||
dd 0x10688086
|
||||
;dd 0x10698086
|
||||
;dd 0x106A8086
|
||||
;dd 0x106B8086
|
||||
;dd 0x10918086
|
||||
;dd 0x10928086
|
||||
;dd 0x10938086
|
||||
;dd 0x10948086
|
||||
;dd 0x10958086
|
||||
;dd 0x10fe8086
|
||||
dd 0x12098086
|
||||
dd 0x12298086
|
||||
dd 0x24498086
|
||||
;dd 0x24598086
|
||||
;dd 0x245D8086
|
||||
;dd 0x27DC8086
|
||||
dd 0x0
|
||||
|
||||
db 'RTL8169',0 ; Realtek 8169
|
||||
dd 0x816710ec
|
||||
dd 0x816810ec
|
||||
dd 0x816910ec
|
||||
dd 0x011616ec
|
||||
dd 0x43001186
|
||||
dd 0x813610ec
|
||||
dd 0x0
|
||||
|
||||
db '3C59X',0 ; 3Com 59x
|
||||
dd 0x590010b7
|
||||
dd 0x592010b7
|
||||
dd 0x597010b7
|
||||
dd 0x595010b7
|
||||
dd 0x595110b7
|
||||
dd 0x595210b7
|
||||
dd 0x900010b7
|
||||
dd 0x900110b7
|
||||
dd 0x900410b7
|
||||
dd 0x900510b7
|
||||
dd 0x900610b7
|
||||
dd 0x900A10b7
|
||||
dd 0x905010b7
|
||||
dd 0x905110b7
|
||||
dd 0x905510b7
|
||||
dd 0x905810b7
|
||||
dd 0x905A10b7
|
||||
dd 0x920010b7
|
||||
dd 0x980010b7
|
||||
dd 0x980510b7
|
||||
dd 0x764610b7
|
||||
dd 0x505510b7
|
||||
dd 0x605510b7
|
||||
dd 0x605610b7
|
||||
dd 0x5b5710b7
|
||||
dd 0x505710b7
|
||||
dd 0x515710b7
|
||||
dd 0x525710b7
|
||||
dd 0x656010b7
|
||||
dd 0x656210b7
|
||||
dd 0x656410b7
|
||||
dd 0x450010b7
|
||||
dd 0x0
|
||||
|
||||
db 'SIS900',0
|
||||
dd 0x09001039
|
||||
dd 0x70161039
|
||||
dd 0x0
|
||||
|
||||
db 'PCNET32',0
|
||||
dd 0x20001022
|
||||
dd 0x26251022
|
||||
dd 0x20011022
|
||||
dd 0x0
|
||||
|
||||
db 'FORCEDETH',0 ; nVidia nForce
|
||||
dd 0x006610de
|
||||
dd 0x01c310de
|
||||
dd 0x00D610de
|
||||
dd 0x008610de
|
||||
dd 0x008c10de
|
||||
dd 0x00e610de
|
||||
dd 0x00df10de
|
||||
dd 0x005610de
|
||||
dd 0x005710de
|
||||
dd 0x003710de
|
||||
dd 0x003810de
|
||||
dd 0x026810de
|
||||
dd 0x026910de
|
||||
dd 0x037210de
|
||||
dd 0x037310de
|
||||
dd 0x03e510de
|
||||
dd 0x03e610de
|
||||
dd 0x03ee10de
|
||||
dd 0x03ef10de
|
||||
dd 0x045010de
|
||||
dd 0x045110de
|
||||
dd 0x045210de
|
||||
dd 0x045310de
|
||||
dd 0x054c10de
|
||||
dd 0x054d10de
|
||||
dd 0x054e10de
|
||||
dd 0x054f10de
|
||||
dd 0x07dc10de
|
||||
dd 0x07dd10de
|
||||
dd 0x07de10de
|
||||
dd 0x07df10de
|
||||
dd 0x076010de
|
||||
dd 0x076110de
|
||||
dd 0x076210de
|
||||
dd 0x076310de
|
||||
dd 0x0ab010de
|
||||
dd 0x0ab110de
|
||||
dd 0x0ab210de
|
||||
dd 0x0ab310de
|
||||
dd 0x0d7d10de
|
||||
dd 0x0
|
||||
|
||||
db 'MTD80X',0 ; Myson / Surecom
|
||||
dd 0x08031516
|
||||
dd 0x08001516
|
||||
dd 0x08911516
|
||||
dd 0x0
|
||||
|
||||
db 'DEC21X4X',0
|
||||
dd 0x00021011
|
||||
dd 0x00091011
|
||||
dd 0x00141011
|
||||
dd 0x00191011
|
||||
dd 0x000211AD
|
||||
dd 0x051210D9
|
||||
dd 0x053110D9
|
||||
dd 0x1400125B
|
||||
dd 0x09851317
|
||||
dd 0x0
|
||||
|
||||
db 'R6040',0 ; eBox integrated network
|
||||
dd 0x604017F3
|
||||
dd 0x0
|
||||
|
||||
db 'I8254X',0
|
||||
dd 0x10008086 ; 82542 (Fiber)
|
||||
dd 0x10018086 ; 82543GC (Fiber)
|
||||
dd 0x10048086 ; 82543GC (Copper)
|
||||
dd 0x10088086 ; 82544EI (Copper)
|
||||
dd 0x10098086 ; 82544EI (Fiber)
|
||||
dd 0x100A8086 ; 82540EM
|
||||
dd 0x100C8086 ; 82544GC (Copper)
|
||||
dd 0x100D8086 ; 82544GC (LOM)
|
||||
dd 0x100E8086 ; 82540EM
|
||||
dd 0x100F8086 ; 82545EM (Copper)
|
||||
dd 0x10108086 ; 82546EB (Copper)
|
||||
dd 0x10118086 ; 82545EM (Fiber)
|
||||
dd 0x10128086 ; 82546EB (Fiber)
|
||||
dd 0x10138086 ; 82541EI
|
||||
dd 0x10148086 ; 82541ER
|
||||
dd 0x10158086 ; 82540EM (LOM)
|
||||
dd 0x10168086 ; 82540EP (Mobile)
|
||||
dd 0x10178086 ; 82540EP
|
||||
dd 0x10188086 ; 82541EI
|
||||
dd 0x10198086 ; 82547EI
|
||||
dd 0x101a8086 ; 82547EI (Mobile)
|
||||
dd 0x101d8086 ; 82546EB
|
||||
dd 0x101e8086 ; 82540EP (Mobile)
|
||||
dd 0x10268086 ; 82545GM
|
||||
dd 0x10278086 ; 82545GM
|
||||
dd 0x10288086 ; 82545GM
|
||||
dd 0x105b8086 ; 82546GB (Copper)
|
||||
dd 0x10758086 ; 82547GI
|
||||
dd 0x10768086 ; 82541GI
|
||||
dd 0x10778086 ; 82541GI
|
||||
dd 0x10788086 ; 82541ER
|
||||
dd 0x10798086 ; 82546GB
|
||||
dd 0x107a8086 ; 82546GB
|
||||
dd 0x107b8086 ; 82546GB
|
||||
dd 0x107c8086 ; 82541PI
|
||||
dd 0x10b58086 ; 82546GB (Copper)
|
||||
dd 0x11078086 ; 82544EI
|
||||
dd 0x11128086 ; 82544GC
|
||||
dd 0x15A18086 ; I218-V
|
||||
dd 0x0
|
||||
|
||||
db 'RHINE', 0 ; VIA Rhine
|
||||
dd 0x30431106
|
||||
dd 0x61001106
|
||||
dd 0x30651106
|
||||
dd 0x31061106
|
||||
dd 0x30531106
|
||||
dd 0x0
|
||||
|
||||
db 'AR81XX', 0
|
||||
dd 0x10631969 ; AR8131
|
||||
;dd 0x10621969 ; AR8132
|
||||
;dd 0x10731969 ; AR8151 V1
|
||||
;dd 0x10831969 ; AR8151 V2
|
||||
;dd 0x20601969 ; AR8152 V1
|
||||
dd 0x20621969 ; AR8152 V2
|
||||
dd 0x10911969 ; AR8161
|
||||
;dd 0xe0911969 ; E2200
|
||||
;dd 0xe0a11969 ; E2400
|
||||
;dd 0xe0b11969 ; E2500
|
||||
dd 0x10901969 ; AR8162
|
||||
dd 0x10A11969 ; AR8171 (QCA8171)
|
||||
dd 0x10A01969 ; AR8172 (QCA8172)
|
||||
dd 0x0
|
||||
|
||||
db 'MAR_YUK2',0
|
||||
dd 0x436311AB ; 88E8055
|
||||
dd 0x0
|
||||
|
||||
dd 0x0 ; driverlist end
|
||||
driverlist:
|
||||
db 'RTL8139',0 ; Realtek 8139
|
||||
dd 0x813910ec
|
||||
dd 0x813810ec
|
||||
dd 0x12111113
|
||||
dd 0x13601500
|
||||
dd 0x13604033
|
||||
dd 0x13001186
|
||||
dd 0x13401186
|
||||
dd 0xab0613d1
|
||||
dd 0xa1171259
|
||||
dd 0xa11e1259
|
||||
dd 0xab0614ea
|
||||
dd 0xab0714ea
|
||||
dd 0x123411db
|
||||
dd 0x91301432
|
||||
dd 0x101202ac
|
||||
dd 0x0106018a
|
||||
dd 0x1211126c
|
||||
dd 0x81391743
|
||||
dd 0x8139021b
|
||||
dd 0x0 ; end
|
||||
|
||||
db 'RTL8029',0 ; Realtek 8029 (PCI NE2000)
|
||||
dd 0x802910ec
|
||||
dd 0x0
|
||||
|
||||
db 'I8255X',0 ; Intel eepro100
|
||||
dd 0x10298086
|
||||
dd 0x10308086
|
||||
;dd 0x10318086
|
||||
;dd 0x10328086
|
||||
;dd 0x10338086
|
||||
;dd 0x10348086
|
||||
;dd 0x10388086
|
||||
dd 0x10398086
|
||||
;dd 0x103A8086
|
||||
;dd 0x103B8086
|
||||
;dd 0x103C8086
|
||||
;dd 0x103D8086
|
||||
;dd 0x103E8086
|
||||
;dd 0x10508086
|
||||
;dd 0x10518086
|
||||
;dd 0x10528086
|
||||
;dd 0x10538086
|
||||
;dd 0x10548086
|
||||
;dd 0x10558086
|
||||
;dd 0x10568086
|
||||
;dd 0x10578086
|
||||
;dd 0x10598086
|
||||
;dd 0x10648086
|
||||
;dd 0x10658086
|
||||
;dd 0x10668086
|
||||
;dd 0x10678086
|
||||
dd 0x10688086
|
||||
;dd 0x10698086
|
||||
;dd 0x106A8086
|
||||
;dd 0x106B8086
|
||||
;dd 0x10918086
|
||||
;dd 0x10928086
|
||||
;dd 0x10938086
|
||||
;dd 0x10948086
|
||||
;dd 0x10958086
|
||||
;dd 0x10fe8086
|
||||
dd 0x12098086
|
||||
dd 0x12298086
|
||||
dd 0x24498086
|
||||
;dd 0x24598086
|
||||
;dd 0x245D8086
|
||||
;dd 0x27DC8086
|
||||
dd 0x0
|
||||
|
||||
db 'RTL8169',0 ; Realtek 8169
|
||||
dd 0x816710ec
|
||||
dd 0x816810ec
|
||||
dd 0x816910ec
|
||||
dd 0x011616ec
|
||||
dd 0x43001186
|
||||
dd 0x813610ec
|
||||
dd 0x0
|
||||
|
||||
db '3C59X',0 ; 3Com 59x
|
||||
dd 0x590010b7
|
||||
dd 0x592010b7
|
||||
dd 0x597010b7
|
||||
dd 0x595010b7
|
||||
dd 0x595110b7
|
||||
dd 0x595210b7
|
||||
dd 0x900010b7
|
||||
dd 0x900110b7
|
||||
dd 0x900410b7
|
||||
dd 0x900510b7
|
||||
dd 0x900610b7
|
||||
dd 0x900A10b7
|
||||
dd 0x905010b7
|
||||
dd 0x905110b7
|
||||
dd 0x905510b7
|
||||
dd 0x905810b7
|
||||
dd 0x905A10b7
|
||||
dd 0x920010b7
|
||||
dd 0x980010b7
|
||||
dd 0x980510b7
|
||||
dd 0x764610b7
|
||||
dd 0x505510b7
|
||||
dd 0x605510b7
|
||||
dd 0x605610b7
|
||||
dd 0x5b5710b7
|
||||
dd 0x505710b7
|
||||
dd 0x515710b7
|
||||
dd 0x525710b7
|
||||
dd 0x656010b7
|
||||
dd 0x656210b7
|
||||
dd 0x656410b7
|
||||
dd 0x450010b7
|
||||
dd 0x0
|
||||
|
||||
db 'SIS900',0
|
||||
dd 0x09001039
|
||||
dd 0x70161039
|
||||
dd 0x0
|
||||
|
||||
db 'PCNET32',0
|
||||
dd 0x20001022
|
||||
dd 0x26251022
|
||||
dd 0x20011022
|
||||
dd 0x0
|
||||
|
||||
db 'FORCEDETH',0 ; nVidia nForce
|
||||
dd 0x006610de
|
||||
dd 0x01c310de
|
||||
dd 0x00D610de
|
||||
dd 0x008610de
|
||||
dd 0x008c10de
|
||||
dd 0x00e610de
|
||||
dd 0x00df10de
|
||||
dd 0x005610de
|
||||
dd 0x005710de
|
||||
dd 0x003710de
|
||||
dd 0x003810de
|
||||
dd 0x026810de
|
||||
dd 0x026910de
|
||||
dd 0x037210de
|
||||
dd 0x037310de
|
||||
dd 0x03e510de
|
||||
dd 0x03e610de
|
||||
dd 0x03ee10de
|
||||
dd 0x03ef10de
|
||||
dd 0x045010de
|
||||
dd 0x045110de
|
||||
dd 0x045210de
|
||||
dd 0x045310de
|
||||
dd 0x054c10de
|
||||
dd 0x054d10de
|
||||
dd 0x054e10de
|
||||
dd 0x054f10de
|
||||
dd 0x07dc10de
|
||||
dd 0x07dd10de
|
||||
dd 0x07de10de
|
||||
dd 0x07df10de
|
||||
dd 0x076010de
|
||||
dd 0x076110de
|
||||
dd 0x076210de
|
||||
dd 0x076310de
|
||||
dd 0x0ab010de
|
||||
dd 0x0ab110de
|
||||
dd 0x0ab210de
|
||||
dd 0x0ab310de
|
||||
dd 0x0d7d10de
|
||||
dd 0x0
|
||||
|
||||
db 'MTD80X',0 ; Myson / Surecom
|
||||
dd 0x08031516
|
||||
dd 0x08001516
|
||||
dd 0x08911516
|
||||
dd 0x0
|
||||
|
||||
db 'DEC21X4X',0
|
||||
dd 0x00021011
|
||||
dd 0x00091011
|
||||
dd 0x00141011
|
||||
dd 0x00191011
|
||||
dd 0x000211AD
|
||||
dd 0x051210D9
|
||||
dd 0x053110D9
|
||||
dd 0x1400125B
|
||||
dd 0x09851317
|
||||
dd 0x0
|
||||
|
||||
db 'R6040',0 ; eBox integrated network
|
||||
dd 0x604017F3
|
||||
dd 0x0
|
||||
|
||||
db 'I8254X',0
|
||||
dd 0x10008086 ; 82542 (Fiber)
|
||||
dd 0x10018086 ; 82543GC (Fiber)
|
||||
dd 0x10048086 ; 82543GC (Copper)
|
||||
dd 0x10088086 ; 82544EI (Copper)
|
||||
dd 0x10098086 ; 82544EI (Fiber)
|
||||
dd 0x100A8086 ; 82540EM
|
||||
dd 0x100C8086 ; 82544GC (Copper)
|
||||
dd 0x100D8086 ; 82544GC (LOM)
|
||||
dd 0x100E8086 ; 82540EM
|
||||
dd 0x100F8086 ; 82545EM (Copper)
|
||||
dd 0x10108086 ; 82546EB (Copper)
|
||||
dd 0x10118086 ; 82545EM (Fiber)
|
||||
dd 0x10128086 ; 82546EB (Fiber)
|
||||
dd 0x10138086 ; 82541EI
|
||||
dd 0x10148086 ; 82541ER
|
||||
dd 0x10158086 ; 82540EM (LOM)
|
||||
dd 0x10168086 ; 82540EP (Mobile)
|
||||
dd 0x10178086 ; 82540EP
|
||||
dd 0x10188086 ; 82541EI
|
||||
dd 0x10198086 ; 82547EI
|
||||
dd 0x101a8086 ; 82547EI (Mobile)
|
||||
dd 0x101d8086 ; 82546EB
|
||||
dd 0x101e8086 ; 82540EP (Mobile)
|
||||
dd 0x10268086 ; 82545GM
|
||||
dd 0x10278086 ; 82545GM
|
||||
dd 0x10288086 ; 82545GM
|
||||
dd 0x105b8086 ; 82546GB (Copper)
|
||||
dd 0x10758086 ; 82547GI
|
||||
dd 0x10768086 ; 82541GI
|
||||
dd 0x10778086 ; 82541GI
|
||||
dd 0x10788086 ; 82541ER
|
||||
dd 0x10798086 ; 82546GB
|
||||
dd 0x107a8086 ; 82546GB
|
||||
dd 0x107b8086 ; 82546GB
|
||||
dd 0x107c8086 ; 82541PI
|
||||
dd 0x10b58086 ; 82546GB (Copper)
|
||||
dd 0x11078086 ; 82544EI
|
||||
dd 0x11128086 ; 82544GC
|
||||
dd 0x15A18086 ; I218-V
|
||||
dd 0x0
|
||||
|
||||
db 'RHINE', 0 ; VIA Rhine
|
||||
dd 0x30431106
|
||||
dd 0x61001106
|
||||
dd 0x30651106
|
||||
dd 0x31061106
|
||||
dd 0x30531106
|
||||
dd 0x0
|
||||
|
||||
|
||||
db 'AR81XX', 0
|
||||
dd 0x10631969 ; AR8131
|
||||
;dd 0x10621969 ; AR8132
|
||||
;dd 0x10731969 ; AR8151 V1
|
||||
;dd 0x10831969 ; AR8151 V2
|
||||
;dd 0x20601969 ; AR8152 V1
|
||||
dd 0x20621969 ; AR8152 V2
|
||||
dd 0x10911969 ; AR8161
|
||||
;dd 0xe0911969 ; E2200
|
||||
;dd 0xe0a11969 ; E2400
|
||||
;dd 0xe0b11969 ; E2500
|
||||
dd 0x10901969 ; AR8162
|
||||
dd 0x10A11969 ; AR8171 (QCA8171)
|
||||
dd 0x10A01969 ; AR8172 (QCA8172)
|
||||
|
||||
|
||||
dd 0x0
|
||||
|
||||
dd 0x0 ; driverlist end
|
||||
@@ -189,6 +189,8 @@ key:
|
||||
mcall 2
|
||||
cmp ah, ' '
|
||||
je button.noclose
|
||||
cmp ah, 9 ; Tab
|
||||
je button.noclose
|
||||
cmp ah, 51 ; F2
|
||||
je open_boardlog
|
||||
jmp still
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;; ;;
|
||||
;; Copyright (C) KolibriOS team 2014. All rights reserved. ;;
|
||||
;; Copyright (C) KolibriOS team 2014-2026. All rights reserved. ;;
|
||||
;; Distributed under terms of the GNU General Public License ;;
|
||||
;; ;;
|
||||
;; terminal for KolibriOS ;;
|
||||
@@ -28,18 +28,35 @@ use32
|
||||
include '../../proc32.inc'
|
||||
include '../../macros.inc'
|
||||
include '../../dll.inc'
|
||||
include '../../KOSfuncs.inc'
|
||||
include '../../develop/libraries/box_lib/box_lib.mac'
|
||||
include '../../../drivers/serial/common.inc'
|
||||
|
||||
|
||||
START:
|
||||
|
||||
mcall 68, 11
|
||||
mcall SF_SYS_MISC, SSF_HEAP_INIT
|
||||
|
||||
stdcall dll.Load, @IMPORT
|
||||
or eax, eax
|
||||
jnz exit
|
||||
|
||||
mcall 40, EVM_MOUSE + EVM_MOUSE_FILTER + EVM_REDRAW + EVM_BUTTON + EVM_KEY
|
||||
call serial_port_init
|
||||
test eax, eax
|
||||
jnz .drv_inited
|
||||
mov [errormsg], err_serial_sys
|
||||
jmp .drv_check_end
|
||||
.drv_inited:
|
||||
push 0
|
||||
stdcall serial_port_get_version, esp
|
||||
pop eax
|
||||
shr eax, 16
|
||||
cmp ax, SERIAL_COMPATIBLE_API_VER
|
||||
jle .drv_check_end
|
||||
mov [errormsg], err_serial_ver
|
||||
.drv_check_end:
|
||||
|
||||
mcall SF_SET_EVENTS_MASK, EVM_MOUSE + EVM_MOUSE_FILTER + EVM_REDRAW + EVM_BUTTON + EVM_KEY
|
||||
|
||||
invoke init_checkbox, ch1
|
||||
|
||||
@@ -47,7 +64,7 @@ red_win:
|
||||
call draw_window
|
||||
|
||||
mainloop:
|
||||
mcall 10
|
||||
mcall SF_WAIT_EVENT
|
||||
|
||||
dec eax
|
||||
jz red_win
|
||||
@@ -71,18 +88,18 @@ mainloop:
|
||||
jmp mainloop
|
||||
|
||||
button:
|
||||
mcall 17
|
||||
mcall SF_GET_BUTTON
|
||||
|
||||
cmp ah, 0x10 ; connect button
|
||||
je open_connection
|
||||
|
||||
test ah , ah
|
||||
test ah, ah
|
||||
jz mainloop
|
||||
exit:
|
||||
mcall -1
|
||||
mcall SF_TERMINATE_PROCESS
|
||||
|
||||
key:
|
||||
mcall 2
|
||||
mcall SF_GET_KEY
|
||||
|
||||
cmp ah, 13 ; enter key
|
||||
je open_connection
|
||||
@@ -98,20 +115,20 @@ key:
|
||||
|
||||
draw_window:
|
||||
; get system colors
|
||||
mcall 48, 3, sc, 40
|
||||
mcall SF_STYLE_SETTINGS, SSF_GET_COLORS, sc, sizeof.system_colors
|
||||
|
||||
mcall 12,1
|
||||
mcall SF_REDRAW, SSF_BEGIN_DRAW
|
||||
mov edx, [sc.work]
|
||||
or edx, 0x34000000
|
||||
xor esi, esi
|
||||
mov edi, str_title
|
||||
mcall 0, 50 shl 16 + 415, 30 shl 16 + 195
|
||||
mcall SF_CREATE_WINDOW, <50, 415>, <30, 195>
|
||||
|
||||
mov ebx, 5 shl 16 + 12
|
||||
mov ecx, 0x90000000
|
||||
or ecx, [sc.work_text]
|
||||
mov edx, str_port
|
||||
mcall 4
|
||||
mcall SF_DRAW_TEXT
|
||||
add ebx, 25
|
||||
mov edx, str_speed
|
||||
mcall
|
||||
@@ -144,21 +161,21 @@ draw_window:
|
||||
invoke check_box_draw, ch1
|
||||
|
||||
mov esi, [sc.work_button]
|
||||
mcall 8, 280 shl 16 + 100, 115 shl 16 + 22, 0x10
|
||||
mcall SF_DEFINE_BUTTON, <280, 100>, <115, 22>, 0x10
|
||||
|
||||
mov ecx, 0x90000000
|
||||
or ecx, [sc.work_button_text]
|
||||
mcall 4, 315 shl 16 + 119, , str_open
|
||||
mcall SF_DRAW_TEXT, <315, 119>, , str_open
|
||||
|
||||
|
||||
mov edx, [sc.work_graph]
|
||||
mcall 38, 0 shl 16 + 405, 145 shl 16 + 145
|
||||
mcall SF_DRAW_LINE, <0, 405>, <145, 145>
|
||||
|
||||
mov ecx, 0x90000000
|
||||
or ecx, [sc.work_text]
|
||||
mcall 4, 5 shl 16 + 150, , [errormsg]
|
||||
mcall SF_DRAW_TEXT, <5, 150>, , [errormsg]
|
||||
|
||||
mcall 12, 2
|
||||
mcall SF_REDRAW, SSF_END_DRAW
|
||||
ret
|
||||
|
||||
|
||||
@@ -166,187 +183,120 @@ open_connection:
|
||||
|
||||
mov [errormsg], err_none ; clear previous error message
|
||||
|
||||
; Read the serial port name, and convert it to a port number
|
||||
cmp byte[ed_port+4], 0
|
||||
jne .port_error
|
||||
mov eax, dword[ed_port]
|
||||
or eax, 0x20202020 ; convert to lowercase
|
||||
cmp eax, 'com1'
|
||||
je .com1
|
||||
cmp eax, 'com2'
|
||||
je .com2
|
||||
cmp eax, 'com3'
|
||||
je .com3
|
||||
cmp eax, 'com4'
|
||||
je .com4
|
||||
.port_error:
|
||||
mov [errormsg], err_port
|
||||
jmp red_win
|
||||
|
||||
.com1:
|
||||
mov [port], 0x3f8
|
||||
jmp .port_ok
|
||||
.com2:
|
||||
mov [port], 0x2f8
|
||||
jmp .port_ok
|
||||
.com3:
|
||||
mov [port], 0x3e8
|
||||
jmp .port_ok
|
||||
.com4:
|
||||
mov [port], 0x2e8
|
||||
.port_ok:
|
||||
|
||||
; reserve the com port so we can work with it
|
||||
xor ebx, ebx
|
||||
movzx ecx, [port]
|
||||
mov edx, ecx
|
||||
add edx, 7
|
||||
mcall 46
|
||||
test eax, eax
|
||||
jz .port_reserved
|
||||
mov [errormsg], err_reserve
|
||||
jmp red_win
|
||||
.port_reserved:
|
||||
|
||||
; disable com interrupts
|
||||
; (We cannot receive them on the application level :( )
|
||||
mov dx, [port]
|
||||
inc dx
|
||||
mov al, 0
|
||||
out dx, al
|
||||
|
||||
; Set speed:
|
||||
; Convert the ascii decimal number that user entered
|
||||
; So we can do some math with it
|
||||
; Baud rate
|
||||
mov esi, ed_speed
|
||||
xor eax, eax
|
||||
xor ebx, ebx
|
||||
.convert_loop:
|
||||
lodsb
|
||||
test al, al
|
||||
jz .convert_done
|
||||
sub al, '0'
|
||||
jb .invalid_speed
|
||||
cmp al, 9
|
||||
ja .invalid_speed
|
||||
lea ebx, [ebx + 4*ebx]
|
||||
shl ebx, 1
|
||||
add ebx, eax
|
||||
jmp .convert_loop
|
||||
.invalid_speed:
|
||||
call free_port
|
||||
mov [errormsg], err_speed
|
||||
jmp red_win
|
||||
.convert_done:
|
||||
call str_to_uint
|
||||
test eax, eax
|
||||
jnz .speed_bad
|
||||
test ebx, ebx
|
||||
jz .invalid_speed
|
||||
|
||||
; We now have the speed setting in ebx
|
||||
; calculate the divisor latch value as 115200/ebx
|
||||
xor edx, edx
|
||||
mov eax, 115200
|
||||
div ebx
|
||||
test edx, edx
|
||||
jnz .invalid_speed
|
||||
cmp eax, 0xffff
|
||||
ja .invalid_speed
|
||||
mov bx, ax
|
||||
|
||||
; enable Divisor latch
|
||||
mov dx, [port]
|
||||
add dx, 3
|
||||
mov al, 1 shl 7 ; dlab bit
|
||||
out dx, al
|
||||
|
||||
; Set divisor latch value
|
||||
mov dx, [port]
|
||||
mov al, bl
|
||||
out dx, al
|
||||
inc dx
|
||||
mov al, bh
|
||||
out dx, al
|
||||
|
||||
; Check the parity type
|
||||
xor bl, bl
|
||||
cmp [option_group1], op1 ; none
|
||||
je .parity_ok
|
||||
|
||||
mov bl, 001b shl 3
|
||||
cmp [option_group1], op2 ; odd
|
||||
je .parity_ok
|
||||
|
||||
mov bl, 011b shl 3
|
||||
cmp [option_group1], op3 ; even
|
||||
je .parity_ok
|
||||
|
||||
mov bl, 101b shl 3
|
||||
cmp [option_group1], op4 ; mark
|
||||
je .parity_ok
|
||||
|
||||
mov bl, 111b shl 3
|
||||
cmp [option_group1], op5 ; space
|
||||
je .parity_ok
|
||||
jmp exit2 ; something went terribly wrong
|
||||
.parity_ok:
|
||||
|
||||
; Check number of stop bits
|
||||
cmp [ed_stop], '1'
|
||||
je .stop_ok
|
||||
cmp [ed_stop], '2'
|
||||
jne .invalid_stop
|
||||
or bl, 1 shl 2 ; number of stop bits
|
||||
jmp .stop_ok
|
||||
.invalid_stop:
|
||||
call free_port
|
||||
mov [errormsg], err_stopbits
|
||||
jnz .speed_ok
|
||||
.speed_bad:
|
||||
mov [errormsg], err_conf
|
||||
jmp red_win
|
||||
.stop_ok:
|
||||
.speed_ok:
|
||||
mov [port_conf + SP_CONF.baudrate], ebx
|
||||
|
||||
; Check number of data bits
|
||||
mov al, [ed_data]
|
||||
cmp al, '8'
|
||||
ja .invalid_data
|
||||
sub al, '5'
|
||||
jae .data_ok
|
||||
cmp al, '5'
|
||||
jb .invalid_data
|
||||
jmp .data_ok
|
||||
.invalid_data:
|
||||
call free_port
|
||||
mov [errormsg], err_databits
|
||||
jmp red_win
|
||||
.data_ok:
|
||||
or al, bl
|
||||
; Program data bits, stop bits and parity in the UART
|
||||
mov dx, [port]
|
||||
add dx, 3 ; Line Control Register
|
||||
out dx, al
|
||||
sub al, '0'
|
||||
mov [port_conf + SP_CONF.word_size], al
|
||||
|
||||
; clear + enable fifo (64 bytes), 1 byte trigger level
|
||||
mov dx, [port]
|
||||
inc dx
|
||||
inc dx
|
||||
mov al, 0x7 + 1 shl 5
|
||||
out dx, al
|
||||
; Check the parity type
|
||||
mov bl, SERIAL_CONF_PARITY_NONE
|
||||
cmp [option_group1], op1
|
||||
je .parity_ok
|
||||
|
||||
; flow control
|
||||
mov dx, [port]
|
||||
add dx, 4
|
||||
mov al, 0xb
|
||||
out dx, al
|
||||
mov bl, SERIAL_CONF_PARITY_ODD
|
||||
cmp [option_group1], op2
|
||||
je .parity_ok
|
||||
|
||||
mov bl, SERIAL_CONF_PARITY_EVEN
|
||||
cmp [option_group1], op3
|
||||
je .parity_ok
|
||||
|
||||
mov bl, SERIAL_CONF_PARITY_MARK
|
||||
cmp [option_group1], op4
|
||||
je .parity_ok
|
||||
|
||||
mov bl, SERIAL_CONF_PARITY_SPACE
|
||||
cmp [option_group1], op5
|
||||
je .parity_ok
|
||||
jmp exit2 ; something went terribly wrong
|
||||
.parity_ok:
|
||||
mov [port_conf + SP_CONF.parity], bl
|
||||
|
||||
; Check number of stop bits
|
||||
mov bl, SERIAL_CONF_STOP_BITS_1
|
||||
cmp [ed_stop], '1'
|
||||
je .stop_ok
|
||||
|
||||
mov bl, SERIAL_CONF_STOP_BITS_2
|
||||
cmp [ed_stop], '2'
|
||||
je .stop_ok
|
||||
|
||||
mov [errormsg], err_stopbits
|
||||
jmp red_win
|
||||
.stop_ok:
|
||||
mov [port_conf + SP_CONF.stop_bits], bl
|
||||
|
||||
; Check port id
|
||||
mov esi, ed_port
|
||||
cmp byte [esi], 0
|
||||
jz .port_bad
|
||||
call str_to_uint
|
||||
test eax, eax
|
||||
jz .port_ok
|
||||
.port_bad:
|
||||
mov [errormsg], err_port
|
||||
jmp red_win
|
||||
.port_ok:
|
||||
|
||||
lea ecx, [port_conf]
|
||||
lea edx, [port_handle]
|
||||
stdcall serial_port_open, ebx, ecx, edx
|
||||
test eax, eax
|
||||
jz .opened
|
||||
|
||||
mov [errormsg], err_port
|
||||
cmp eax, SERIAL_API_ERR_PORT_INVALID
|
||||
jz red_win
|
||||
|
||||
mov [errormsg], err_reserve
|
||||
cmp eax, SERIAL_API_ERR_PORT_BUSY
|
||||
jz red_win
|
||||
|
||||
mov [errormsg], err_conf
|
||||
cmp eax, SERIAL_API_ERR_CONF
|
||||
jz red_win
|
||||
|
||||
mov [errormsg], err_unknown
|
||||
jmp red_win
|
||||
|
||||
; Hide our GUI window and open the console
|
||||
mcall 40, 0 ; disable all events
|
||||
mcall 67, 0, 0, 0, 0 ; hide window
|
||||
mcall 12, 1
|
||||
mcall 12, 2
|
||||
.opened:
|
||||
mcall SF_SET_EVENTS_MASK, 0 ; disable all events
|
||||
mcall SF_CHANGE_WINDOW, 0, 0, 0, 0 ; hide window
|
||||
mcall SF_REDRAW, SSF_BEGIN_DRAW
|
||||
mcall SF_REDRAW, SSF_END_DRAW
|
||||
|
||||
invoke con_start, 1
|
||||
invoke con_init, 80, 25, 80, 25, str_title
|
||||
|
||||
console_loop:
|
||||
mcall 5, 1 ; wait 10 ms
|
||||
mcall SF_SLEEP, 1 ; wait 10 ms
|
||||
|
||||
invoke con_get_flags
|
||||
test eax, 0x200 ; con window closed?
|
||||
jnz exit2
|
||||
jnz .close_port
|
||||
|
||||
.tx_loop:
|
||||
invoke con_kbhit
|
||||
@@ -354,50 +304,56 @@ console_loop:
|
||||
jz .rx_loop
|
||||
|
||||
invoke con_getch2 ; get the pressed key from buffer
|
||||
mov dx, [port]
|
||||
out dx, al
|
||||
and eax, 0xff
|
||||
mov [port_buf], eax
|
||||
mov [port_data_cnt], 1
|
||||
stdcall serial_port_write, [port_handle], port_buf, port_data_cnt
|
||||
|
||||
test [ch1.flags], ch_flag_en ; does user want us to echo locally?
|
||||
je .tx_loop
|
||||
|
||||
and eax, 0xff
|
||||
push eax
|
||||
invoke con_write_asciiz, esp ; print the character
|
||||
pop eax
|
||||
invoke con_write_asciiz, port_buf ; print the character
|
||||
jmp .tx_loop
|
||||
|
||||
.rx_loop:
|
||||
mov dx, [port]
|
||||
add dx, 5 ; Line status register
|
||||
in al, dx
|
||||
test al, 1 ; Data ready?
|
||||
jz console_loop
|
||||
|
||||
mov dx, [port] ; Read character from buffer
|
||||
in al, dx
|
||||
|
||||
and eax, 0xff
|
||||
push eax
|
||||
invoke con_write_asciiz, esp ; print the character
|
||||
pop eax
|
||||
|
||||
mov [port_buf], 0
|
||||
mov [port_data_cnt], 3
|
||||
stdcall serial_port_read, [port_handle], port_buf, port_data_cnt
|
||||
test eax, eax
|
||||
jnz console_loop ; an error occured
|
||||
mov ebx, [port_data_cnt]
|
||||
test ebx, ebx
|
||||
jz console_loop ; no data yet
|
||||
invoke con_write_asciiz, port_buf
|
||||
jmp .rx_loop
|
||||
|
||||
|
||||
.close_port:
|
||||
stdcall serial_port_close, [port_handle]
|
||||
|
||||
exit2:
|
||||
mcall SF_TERMINATE_PROCESS
|
||||
|
||||
call free_port
|
||||
mcall -1 ; exit
|
||||
|
||||
free_port:
|
||||
|
||||
str_to_uint:
|
||||
; esi = source string
|
||||
; eax = 0 if success
|
||||
; ebx = result number
|
||||
xor eax, eax
|
||||
xor ebx, ebx
|
||||
inc ebx
|
||||
movzx ecx, [port]
|
||||
mov edx, ecx
|
||||
add edx, 7
|
||||
mcall 46
|
||||
|
||||
.loop:
|
||||
lodsb
|
||||
test al, al
|
||||
jz .done
|
||||
sub al, '0'
|
||||
jb .done
|
||||
cmp al, 9
|
||||
ja .done
|
||||
lea ebx, [ebx + 4 * ebx]
|
||||
shl ebx, 1
|
||||
add ebx, eax
|
||||
jmp .loop
|
||||
.done:
|
||||
ret
|
||||
|
||||
;-------------------------
|
||||
@@ -428,13 +384,13 @@ import console,\
|
||||
con_get_flags, 'con_get_flags',\
|
||||
con_kbhit, 'con_kbhit'
|
||||
|
||||
edit1 edit_box 60, 112, 10, 0xffffff, 0x6f9480, 0, 0, 0x10000000, 8, ed_port, mouse_dd, ed_focus, 4, 4
|
||||
edit1 edit_box 60, 112, 10, 0xffffff, 0x6f9480, 0, 0, 0x10000000, 5, ed_port, mouse_dd, ed_focus, 1, 1
|
||||
edit2 edit_box 60, 112, 35, 0xffffff, 0x6a9480, 0, 0, 0x10000000, 7, ed_speed, mouse_dd, ed_figure_only, 4, 4
|
||||
edit3 edit_box 60, 112, 60, 0xffffff, 0x6a9480, 0, 0, 0x10000000, 1, ed_data, mouse_dd, ed_figure_only, 1, 1
|
||||
edit4 edit_box 60, 112, 85, 0xffffff, 0x6a9480, 0, 0, 0x10000000, 1, ed_stop, mouse_dd, ed_figure_only, 1, 1
|
||||
editboxes_end:
|
||||
|
||||
ed_port db "COM1",0,0,0,0,0,0
|
||||
ed_port db "0",0,0,0,0,0,0
|
||||
ed_speed db "9600",0,0,0
|
||||
ed_data db "8",0
|
||||
ed_stop db "1",0
|
||||
@@ -483,15 +439,26 @@ errormsg dd err_none
|
||||
err_none db 0
|
||||
err_port db 'Invalid serial port.', 0
|
||||
err_reserve db 'The port is already in use.', 0
|
||||
err_speed db 'Incorrect speed setting.', 0
|
||||
err_conf db 'Incorrect port setting.', 0
|
||||
err_stopbits db 'Invalid number of stop bits. Must be 1 or 2.', 0
|
||||
err_databits db 'Invalid number of data bits. Must be between 5 and 8.', 0
|
||||
err_unknown db 'An unknown error.', 0
|
||||
err_serial_sys db 'Error loading serial driver.', 0
|
||||
err_serial_ver db 'Incompatible serial driver version.', 0
|
||||
|
||||
port_conf:
|
||||
dd port_conf_end - port_conf
|
||||
dd 9600
|
||||
db 8, SERIAL_CONF_STOP_BITS_1, SERIAL_CONF_PARITY_NONE, SERIAL_CONF_FLOW_CTRL_NONE
|
||||
port_conf_end:
|
||||
|
||||
I_END:
|
||||
|
||||
mouse_dd dd ?
|
||||
echo db ?
|
||||
port dw ?
|
||||
sc system_colors
|
||||
port_handle dd ?
|
||||
port_buf dd ?
|
||||
port_data_cnt dd ?
|
||||
|
||||
IM_END:
|
||||
Reference in new issue
Block a user